public inbox for libc-ports@sourceware.org
 help / color / mirror / Atom feed
* [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
@ 2013-03-11 23:31 Roland McGrath
  2013-03-12  0:30 ` Joseph S. Myers
  0 siblings, 1 reply; 9+ messages in thread
From: Roland McGrath @ 2013-03-11 23:31 UTC (permalink / raw)
  To: Joseph Myers; +Cc: libc-ports

I have a target that is ARMv7-A but the OS does not permit any Thumb code.
(My OS-specific sysdep.h will #define NO_THUMB.)

This changes the memchr implementation to be usable without Thumb.
Tested on armv7l-linux-gnueabihf: no test regressions, and the only
changes in the code seen in disassembly are to the register allocation
(what was r4,r5,r6 is now r6,r4,r5).  I also tested the changes by
locally hacking in #define NO_THUMB at the top of the file, and verified
no test regressions with that build (and eyeball verified that it really
did build the ARM-not-Thumb version of the code).

OK?


Thanks,
Roland


ports/
2013-03-11  Roland McGrath  <roland@hack.frob.com>

	* sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use
	is r4,r5 rather than r5,r6.
	[NO_THUMB]: Use .arm rather than .thumb, .thumb_func.
	Avoid cbz/cnbz instructions.

--- a/ports/sysdeps/arm/armv6t2/memchr.S
+++ b/ports/sysdeps/arm/armv6t2/memchr.S
@@ -42,10 +42,12 @@
 	.syntax unified
 
 	.text
+#ifdef NO_THUMB
+	.arm
+#else
 	.thumb
-
-@ ---------------------------------------------------------------------------
 	.thumb_func
+#endif
 	.global memchr
 	.type memchr,%function
 ENTRY(memchr)
@@ -83,20 +85,28 @@ ENTRY(memchr)
 
 	orr	r1, r1, r1, lsl #8	@ expand the match word across to all bytes
 	orr	r1, r1, r1, lsl #16
-	bic	r4, r2, #7	@ Number of double words to work with * 8
+	bic	r6, r2, #7	@ Number of double words to work with * 8
 	mvns	r7, #0		@ all F's
 	movs	r3, #0
 
 15:
-	ldrd 	r5,r6, [r0],#8
-	subs	r4, r4, #8
-	eor	r5,r5, r1	@ Get it so that r5,r6 have 00's where the bytes match the target
-	eor	r6,r6, r1
+	ldrd 	r4,r5, [r0],#8
+#ifndef NO_THUMB
+	subs	r6, r6, #8
+#endif
+	eor	r4,r4, r1	@ Get it so that r4,r5 have 00's where the bytes match the target
+	eor	r5,r5, r1
+	uadd8	r4, r4, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r4, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
 	uadd8	r5, r5, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
-	sel	r5, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
-	uadd8	r6, r6, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
-	sel	r6, r5, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
-	cbnz	r6, 60f
+	sel	r5, r4, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+#ifndef NO_THUMB
+	cbnz	r5, 60f
+#else
+	cmp	r5, #0
+	bne	60f
+	subs	r6, r6, #8
+#endif
 	bne	15b		@ (Flags from the subs above) If not run out of bytes then go around again
 
 	pop	{r4,r5,r6,r7}
@@ -110,13 +120,24 @@ ENTRY(memchr)
 	and	r2,r2,#7	@ Leave the count remaining as the number after the double words have been done
 
 20:
+#ifndef NO_THUMB
 	cbz	r2, 40f		@ 0 length or hit the end already then not found
+#else
+	cmp	r2, #0
+	beq	40f
+#endif
 
 21:  @ Post aligned section, or just a short call
 	ldrb	r3,[r0],#1
+#ifndef NO_THUMB
 	subs	r2,r2,#1
 	eor	r3,r3,r1	@ r3 = 0 if match - doesn't break flags from sub
 	cbz	r3, 50f
+#else
+	eors	r3, r3, r1
+	beq	50f
+	subs	r2, r2, #1
+#endif
 	bne	21b		@ on r2 flags
 
 40:
@@ -129,22 +150,22 @@ ENTRY(memchr)
 
 60:  @ We're here because the fast path found a hit - now we have to track down exactly which word it was
      @ r0 points to the start of the double word after the one that was tested
-     @ r5 has the 00/ff pattern for the first word, r6 has the chained value
+     @ r4 has the 00/ff pattern for the first word, r5 has the chained value
 	cfi_restore_state
-	cmp	r5, #0
+	cmp	r4, #0
 	itte	eq
-	moveq	r5, r6		@ the end is in the 2nd word
+	moveq	r4, r5		@ the end is in the 2nd word
 	subeq	r0,r0,#3	@ Points to 2nd byte of 2nd word
 	subne	r0,r0,#7	@ or 2nd byte of 1st word
 
 	@ r0 currently points to the 2nd byte of the word containing the hit
-	tst	r5, # CHARTSTMASK(0)	@ 1st character
+	tst	r4, # CHARTSTMASK(0)	@ 1st character
 	bne	61f
 	adds	r0,r0,#1
-	tst	r5, # CHARTSTMASK(1)	@ 2nd character
+	tst	r4, # CHARTSTMASK(1)	@ 2nd character
 	ittt	eq
 	addeq	r0,r0,#1
-	tsteq	r5, # (3<<15)		@ 2nd & 3rd character
+	tsteq	r4, # (3<<15)		@ 2nd & 3rd character
 	@ If not the 3rd must be the last one
 	addeq	r0,r0,#1
 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
  2013-03-11 23:31 [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
@ 2013-03-12  0:30 ` Joseph S. Myers
  2013-03-12  6:09   ` Richard Henderson
  0 siblings, 1 reply; 9+ messages in thread
From: Joseph S. Myers @ 2013-03-12  0:30 UTC (permalink / raw)
  To: Roland McGrath; +Cc: libc-ports

On Mon, 11 Mar 2013, Roland McGrath wrote:

> This changes the memchr implementation to be usable without Thumb.

I'm not clear on how the register allocation changes relate to making this 
implementation usable without Thumb.

-- 
Joseph S. Myers
joseph@codesourcery.com

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
  2013-03-12  0:30 ` Joseph S. Myers
@ 2013-03-12  6:09   ` Richard Henderson
  2013-03-12 15:58     ` Joseph S. Myers
  0 siblings, 1 reply; 9+ messages in thread
From: Richard Henderson @ 2013-03-12  6:09 UTC (permalink / raw)
  To: Joseph S. Myers; +Cc: Roland McGrath, libc-ports

On 2013-03-11 17:30, Joseph S. Myers wrote:
> On Mon, 11 Mar 2013, Roland McGrath wrote:
>
>> This changes the memchr implementation to be usable without Thumb.
>
> I'm not clear on how the register allocation changes relate to making this
> implementation usable without Thumb.
>

This re ldrd.  ARM mode requires r2 = r + 1, and r even.
Thumb2 allows arbitrary r2.


r~

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
  2013-03-12  6:09   ` Richard Henderson
@ 2013-03-12 15:58     ` Joseph S. Myers
  2013-03-12 17:07       ` [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation Roland McGrath
  2013-03-12 17:08       ` [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
  0 siblings, 2 replies; 9+ messages in thread
From: Joseph S. Myers @ 2013-03-12 15:58 UTC (permalink / raw)
  To: Richard Henderson; +Cc: Roland McGrath, libc-ports

On Mon, 11 Mar 2013, Richard Henderson wrote:

> On 2013-03-11 17:30, Joseph S. Myers wrote:
> > On Mon, 11 Mar 2013, Roland McGrath wrote:
> > 
> > > This changes the memchr implementation to be usable without Thumb.
> > 
> > I'm not clear on how the register allocation changes relate to making this
> > implementation usable without Thumb.
> > 
> 
> This re ldrd.  ARM mode requires r2 = r + 1, and r even.
> Thumb2 allows arbitrary r2.

Thanks.  In that case I think the register allocation part of the patch 
should be separated from the cbz/cbnz part to make each change easier to 
review.

-- 
Joseph S. Myers
joseph@codesourcery.com

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation.
  2013-03-12 15:58     ` Joseph S. Myers
@ 2013-03-12 17:07       ` Roland McGrath
  2013-03-12 23:20         ` Joseph S. Myers
  2013-03-12 17:08       ` [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
  1 sibling, 1 reply; 9+ messages in thread
From: Roland McGrath @ 2013-03-12 17:07 UTC (permalink / raw)
  To: Joseph S. Myers; +Cc: Richard Henderson, libc-ports

ports/ChangeLog.arm
2013-03-12  Roland McGrath  <roland@hack.frob.com>

	* sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use
	is r4,r5 rather than r5,r6; this way ARM mode will allow that ldrd.

--- a/ports/sysdeps/arm/armv6t2/memchr.S
+++ b/ports/sysdeps/arm/armv6t2/memchr.S
@@ -83,20 +83,20 @@ ENTRY(memchr)
 
 	orr	r1, r1, r1, lsl #8	@ expand the match word across to all bytes
 	orr	r1, r1, r1, lsl #16
-	bic	r4, r2, #7	@ Number of double words to work with * 8
+	bic	r6, r2, #7	@ Number of double words to work with * 8
 	mvns	r7, #0		@ all F's
 	movs	r3, #0
 
 15:
-	ldrd 	r5,r6, [r0],#8
-	subs	r4, r4, #8
-	eor	r5,r5, r1	@ Get it so that r5,r6 have 00's where the bytes match the target
-	eor	r6,r6, r1
+	ldrd 	r4,r5, [r0],#8
+	subs	r6, r6, #8
+	eor	r4,r4, r1	@ Get it so that r4,r5 have 00's where the bytes match the target
+	eor	r5,r5, r1
+	uadd8	r4, r4, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r4, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
 	uadd8	r5, r5, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
-	sel	r5, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
-	uadd8	r6, r6, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
-	sel	r6, r5, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
-	cbnz	r6, 60f
+	sel	r5, r4, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+	cbnz	r5, 60f
 	bne	15b		@ (Flags from the subs above) If not run out of bytes then go around again
 
 	pop	{r4,r5,r6,r7}
@@ -129,22 +129,22 @@ ENTRY(memchr)
 
 60:  @ We're here because the fast path found a hit - now we have to track down exactly which word it was
      @ r0 points to the start of the double word after the one that was tested
-     @ r5 has the 00/ff pattern for the first word, r6 has the chained value
+     @ r4 has the 00/ff pattern for the first word, r5 has the chained value
 	cfi_restore_state
-	cmp	r5, #0
+	cmp	r4, #0
 	itte	eq
-	moveq	r5, r6		@ the end is in the 2nd word
+	moveq	r4, r5		@ the end is in the 2nd word
 	subeq	r0,r0,#3	@ Points to 2nd byte of 2nd word
 	subne	r0,r0,#7	@ or 2nd byte of 1st word
 
 	@ r0 currently points to the 2nd byte of the word containing the hit
-	tst	r5, # CHARTSTMASK(0)	@ 1st character
+	tst	r4, # CHARTSTMASK(0)	@ 1st character
 	bne	61f
 	adds	r0,r0,#1
-	tst	r5, # CHARTSTMASK(1)	@ 2nd character
+	tst	r4, # CHARTSTMASK(1)	@ 2nd character
 	ittt	eq
 	addeq	r0,r0,#1
-	tsteq	r5, # (3<<15)		@ 2nd & 3rd character
+	tsteq	r4, # (3<<15)		@ 2nd & 3rd character
 	@ If not the 3rd must be the last one
 	addeq	r0,r0,#1
 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
  2013-03-12 15:58     ` Joseph S. Myers
  2013-03-12 17:07       ` [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation Roland McGrath
@ 2013-03-12 17:08       ` Roland McGrath
  2013-03-12 23:21         ` Joseph S. Myers
  1 sibling, 1 reply; 9+ messages in thread
From: Roland McGrath @ 2013-03-12 17:08 UTC (permalink / raw)
  To: Joseph S. Myers; +Cc: Richard Henderson, libc-ports

ports/ChangeLog.arm
	* sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
	Use .arm rather than .thumb, .thumb_func.  Avoid cbz/cnbz instructions.

--- a/ports/sysdeps/arm/armv6t2/memchr.S
+++ b/ports/sysdeps/arm/armv6t2/memchr.S
@@ -42,10 +42,12 @@
 	.syntax unified
 
 	.text
+#ifdef NO_THUMB
+	.arm
+#else
 	.thumb
-
-@ ---------------------------------------------------------------------------
 	.thumb_func
+#endif
 	.global memchr
 	.type memchr,%function
 ENTRY(memchr)
@@ -89,14 +91,22 @@ ENTRY(memchr)
 
 15:
 	ldrd 	r4,r5, [r0],#8
+#ifndef NO_THUMB
 	subs	r6, r6, #8
+#endif
 	eor	r4,r4, r1	@ Get it so that r4,r5 have 00's where the bytes match the target
 	eor	r5,r5, r1
 	uadd8	r4, r4, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
 	sel	r4, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
 	uadd8	r5, r5, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
 	sel	r5, r4, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+#ifndef NO_THUMB
 	cbnz	r5, 60f
+#else
+	cmp	r5, #0
+	bne	60f
+	subs	r6, r6, #8
+#endif
 	bne	15b		@ (Flags from the subs above) If not run out of bytes then go around again
 
 	pop	{r4,r5,r6,r7}
@@ -110,13 +120,24 @@ ENTRY(memchr)
 	and	r2,r2,#7	@ Leave the count remaining as the number after the double words have been done
 
 20:
+#ifndef NO_THUMB
 	cbz	r2, 40f		@ 0 length or hit the end already then not found
+#else
+	cmp	r2, #0
+	beq	40f
+#endif
 
 21:  @ Post aligned section, or just a short call
 	ldrb	r3,[r0],#1
+#ifndef NO_THUMB
 	subs	r2,r2,#1
 	eor	r3,r3,r1	@ r3 = 0 if match - doesn't break flags from sub
 	cbz	r3, 50f
+#else
+	eors	r3, r3, r1
+	beq	50f
+	subs	r2, r2, #1
+#endif
 	bne	21b		@ on r2 flags
 
 40:

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation.
  2013-03-12 17:07       ` [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation Roland McGrath
@ 2013-03-12 23:20         ` Joseph S. Myers
  2013-03-13  0:06           ` Roland McGrath
  0 siblings, 1 reply; 9+ messages in thread
From: Joseph S. Myers @ 2013-03-12 23:20 UTC (permalink / raw)
  To: Roland McGrath; +Cc: Richard Henderson, libc-ports

On Tue, 12 Mar 2013, Roland McGrath wrote:

> ports/ChangeLog.arm
> 2013-03-12  Roland McGrath  <roland@hack.frob.com>
> 
> 	* sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use
> 	is r4,r5 rather than r5,r6; this way ARM mode will allow that ldrd.

OK.

-- 
Joseph S. Myers
joseph@codesourcery.com

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
  2013-03-12 17:08       ` [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
@ 2013-03-12 23:21         ` Joseph S. Myers
  0 siblings, 0 replies; 9+ messages in thread
From: Joseph S. Myers @ 2013-03-12 23:21 UTC (permalink / raw)
  To: Roland McGrath; +Cc: Richard Henderson, libc-ports

On Tue, 12 Mar 2013, Roland McGrath wrote:

> ports/ChangeLog.arm
> 	* sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
> 	Use .arm rather than .thumb, .thumb_func.  Avoid cbz/cnbz instructions.

OK.

-- 
Joseph S. Myers
joseph@codesourcery.com

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation.
  2013-03-12 23:20         ` Joseph S. Myers
@ 2013-03-13  0:06           ` Roland McGrath
  0 siblings, 0 replies; 9+ messages in thread
From: Roland McGrath @ 2013-03-13  0:06 UTC (permalink / raw)
  To: Joseph S. Myers; +Cc: Richard Henderson, libc-ports

Committed these two.

Thanks,
Roland

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2013-03-13  0:06 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-03-11 23:31 [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
2013-03-12  0:30 ` Joseph S. Myers
2013-03-12  6:09   ` Richard Henderson
2013-03-12 15:58     ` Joseph S. Myers
2013-03-12 17:07       ` [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation Roland McGrath
2013-03-12 23:20         ` Joseph S. Myers
2013-03-13  0:06           ` Roland McGrath
2013-03-12 17:08       ` [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Roland McGrath
2013-03-12 23:21         ` Joseph S. Myers

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).