Level sensitive ARM interrupts

Level sensitive ARM interrupts

[Robert Shideleff]

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This patch makes arm interrupts level sensitive, as they are in hardware. The 
nirq and nfiq pins are no longer callbacks, but rather simple input pins. 
They are 'pulled' to high at processor invocation and reset. Their level is 
'sense()-ed' at the beginning of each step.

The patch file was taken from within the sid/component/cgen-cpu/arm7t 
directory.

This is necessary for proper operation of eCos, and for the ability to model 
interrupts as they occur in actual hardware.

Bob
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Re: Level sensitive ARM interrupts

[Robert Shideleff]

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Forgot the attachment. (as usual)

On Friday 02 July 2004 02:37 pm, Robert Shideleff wrote:
> This patch makes arm interrupts level sensitive, as they are in hardware.
> The nirq and nfiq pins are no longer callbacks, but rather simple input
> pins. They are 'pulled' to high at processor invocation and reset. Their
> level is 'sense()-ed' at the beginning of each step.
>
> The patch file was taken from within the sid/component/cgen-cpu/arm7t
> directory.
>
> This is necessary for proper operation of eCos, and for the ability to
> model interrupts as they occur in actual hardware.
>
> Bob
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Index: arm7f.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/arm7t/arm7f.cxx,v
retrieving revision 1.3
diff -u -r1.3 arm7f.cxx
--- arm7f.cxx	28 Jun 2001 21:52:56 -0000	1.3
+++ arm7f.cxx	2 Jul 2004 18:34:26 -0000
@@ -17,8 +17,6 @@
 arm7f_cpu::arm7f_cpu ():
   arm_engine (32768),   // XXX: tune size
   thumb_engine (32768), // XXX: tune size
-  nfiq_pin (this, & arm7f_cpu::do_nfiq_pin),
-  nirq_pin (this, & arm7f_cpu::do_nirq_pin),
   initialized_p (false)
 {
   // ??? One might want to quibble over the case of these pins (nFIQ?).
@@ -87,6 +85,10 @@
 
   // Add register access for debugger
   this->create_gdb_register_attrs (26, "7;11;13;14;15;25", & this->hardware.h_pc);
+
+  // These need to be 'pulled' high if they are not connected.
+  nirq_pin.driven(1);
+  nfiq_pin.driven(1);
 }
 
 string
@@ -168,6 +170,10 @@
   this->initialized_p = true;
 
   this->triggerpoint_manager.check_and_dispatch ();
+
+  // These need to be 'pulled' high if they are not connected.
+  nirq_pin.driven(1);
+  nfiq_pin.driven(1);
 }
 
 
@@ -182,6 +188,18 @@
       return;
     }
 
+  // Check for currently asserted interrupt pins. Interrupts are only checked for at each
+  // step size block of instructions.
+  if(!this->h_fbit_get() && !nfiq_pin.sense())
+    queue_eit (EIT_FIQ);
+ 
+  if(!this->h_ibit_get() && !nirq_pin.sense())
+    queue_eit (EIT_IRQ);
+
+  // If an eit is queued, process it now.
+  if (this->pending_eit != EIT_NONE)
+    this->process_eit (this->pending_eit);
+
   if (this->engine_type == ENGINE_PBB)
     {
       if (this->h_tbit_get ())
@@ -412,10 +430,6 @@
 {
   assert (! this->h_tbit_get ());
 
-  // If an eit is queued, process it now.
-  if (this->pending_eit != EIT_NONE)
-    this->process_eit (this->pending_eit);
-
   while (true)
     {
       // Fetch/decode the instruction  ------------------------------
@@ -482,10 +496,6 @@
 {
   assert (this->h_tbit_get ());
 
-  // If an eit is queued, process it now.
-  if (this->pending_eit != EIT_NONE)
-    this->process_eit (this->pending_eit);
-
   while (true)
     {
       // Fetch/decode the instruction  ------------------------------
@@ -553,10 +563,6 @@
       || this->enable_step_trap_p)
     return this->step_arm ();
 
-  // If an eit is queued, process it now.
-  if (this->pending_eit != EIT_NONE)
-    this->process_eit (this->pending_eit);
-
   try
     {
       // This function takes care of step_insn_count.
@@ -583,10 +589,6 @@
       || this->enable_step_trap_p)
     return this->step_thumb ();
 
-  // If an eit is queued, process it now.
-  if (this->pending_eit != EIT_NONE)
-    this->process_eit (this->pending_eit);
-
   try
     {
       // This function takes care of step_insn_count.
@@ -961,46 +963,6 @@
 \f
 // EIT (exception, interrupt, and trap) pins.
 
-void
-arm7f_cpu::do_nfiq_pin (host_int_4 value)
-{
-  // FIXME: Should be able to catch high-low transition but can't do
-  // that with callback_pin.
-  //if (nfiq_pin.sense () == value)
-  //  return;
-  if (value)
-    return;
-
-  // nFIQ has been driven low.
-
-  // Are FIQ interrupts disabled?
-  if (this->h_fbit_get ())
-    return;
-
-  // Queue the interrupt.
-  this->queue_eit (EIT_FIQ);
-}
-
-void
-arm7f_cpu::do_nirq_pin (host_int_4 value)
-{
-  // FIXME: Should be able to catch high-low transition but can't do
-  // that with callback_pin.
-  //if (nirq_pin.sense () == value)
-  //  return;
-  if (value)
-    return;
-
-  // nIRQ has been driven low.
-
-  // Are IRQ interrupts disabled?
-  if (this->h_ibit_get ())
-    return;
-
-  // Queue the interrupt.
-  this->queue_eit (EIT_IRQ);
-}
-
 \f
 // Miscellaneous pins.
 
Index: arm7f.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/arm7t/arm7f.h,v
retrieving revision 1.3
diff -u -r1.3 arm7f.h
--- arm7f.h	8 Jan 2003 03:17:27 -0000	1.3
+++ arm7f.h	2 Jul 2004 18:34:26 -0000
@@ -158,10 +158,8 @@
   // FIQ/IRQ are generated by driving these pins (low).
   // It is synchronous if ISYNC is high, asynchronous if ISYNC is low.
   // If asynchronous, a cycle delay for synchronization is incurred.
-  callback_pin<arm7f_cpu> nfiq_pin;
-  void do_nfiq_pin (host_int_4 value);
-  callback_pin<arm7f_cpu> nirq_pin;
-  void do_nirq_pin (host_int_4 value);
+  input_pin nfiq_pin;
+  input_pin nirq_pin;
 
   // cpu is reset by driving this pin low
 #if 0
Index: hw-cpu-arm7t.xml
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml,v
retrieving revision 1.1
diff -u -r1.1 hw-cpu-arm7t.xml
--- hw-cpu-arm7t.xml	3 Aug 2001 01:47:52 -0000	1.1
+++ hw-cpu-arm7t.xml	2 Jul 2004 18:34:26 -0000
@@ -56,7 +56,9 @@
       <pin>step!</pin> pin is next invoked.  Note that this may not be
       the next instruction if the
       <attribute>step-insn-count</attribute> attribute is greater than
-      one.</p>
+      one. Also note that these pins are level sensitive, so interrupts
+      will occur repeatedly until the pin is driven non-zero. They are
+      'pulled' to one (high) at processor invocation and reset.</p>
     </behavior>
 
 

Re: Level sensitive ARM interrupts

[Ben Elliston]

Robert Shideleff <bigbob@shideleff.com> writes:

> This patch makes arm interrupts level sensitive, as they are in hardware.
> The nirq and nfiq pins are no longer callbacks, but rather simple input
> pins. They are 'pulled' to high at processor invocation and reset. Their
> level is 'sense()-ed' at the beginning of each step.
>
> The patch file was taken from within the sid/component/cgen-cpu/arm7t
> directory.
>
> This is necessary for proper operation of eCos, and for the ability to
> model interrupts as they occur in actual hardware.

There are a number of ARM-related interrupt tests which, from
recollection, passed.  Does your patch suggest that the tests are
wrong?  If so, can you update them, too?

Ben

Re: Level sensitive ARM interrupts

[Frank Ch. Eigler]

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Hi, Robert -

On Wed, Aug 04, 2004 at 11:17:45AM -0400, Robert Shideleff wrote:
> Oh yeah. Sorry, but I've been pretty busy lately. I've got all of the 
> approvals and here is the updated patch.
> 
> By the way, I've found SID to be extremely useful, even after hardware is 
> available.
> [...]

Thank you very much; your patch is committed to CVS.


- FChE

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