* [PATCH v4 0/6] Support Intel Sierra Forest Instructions
@ 2022-10-31 3:05 Haochen Jiang
2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools
Hi all,
These six patches are our v4 patch for new ISAs.
For these six patches, only minor fixes are done comparing to v3.
All the comments mentioned in previous thread are fixed, including:
1. Add _ANY_ back to all ISAs.
2. Share the test dump file between 32/64 bits for WRMSRNS/MSRLIST.
3. Adjust the insertion in opcodes/i386-opc.tbl for AVX-IFMA and
AVX-VNNI-INT8.
4. Remove SwapSource usage in CMPccXADD and use cpuarch to handle
the special encoding in CMPccXADD.
Thanks for all the discussion and reviews. Ok for trunk?
BTW, there are still two patches pending for revise so they are
not included in this series. AVX-NE-CONVERT will be sent out soon
and RAO-INT still pending for the discussion on suffixes usage.
BRs,
Haochen
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 1/6] Support Intel AVX-IFMA 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:52 ` H.J. Lu 2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang ` (4 subsequent siblings) 5 siblings, 1 reply; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools, Hongyu Wang From: Hongyu Wang <hongyu.wang@intel.com> x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 7 +- gas/testsuite/gas/i386/avx-ifma-intel.d | 37 + gas/testsuite/gas/i386/avx-ifma-inval.l | 3 + gas/testsuite/gas/i386/avx-ifma-inval.s | 7 + gas/testsuite/gas/i386/avx-ifma.d | 37 + gas/testsuite/gas/i386/avx-ifma.s | 40 + gas/testsuite/gas/i386/i386.exp | 6 + gas/testsuite/gas/i386/noavx512-1.l | 24 +- .../gas/i386/x86-64-avx-ifma-intel.d | 34 + .../gas/i386/x86-64-avx-ifma-inval.l | 4 + .../gas/i386/x86-64-avx-ifma-inval.s | 8 + gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 + gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 + opcodes/i386-dis-evex.h | 4 +- opcodes/i386-dis.c | 16 +- opcodes/i386-gen.c | 7 +- opcodes/i386-init.h | 524 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7810 +++++++++-------- 22 files changed, 4477 insertions(+), 4161 deletions(-) create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s create mode 100644 gas/testsuite/gas/i386/avx-ifma.d create mode 100644 gas/testsuite/gas/i386/avx-ifma.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s diff --git a/gas/NEWS b/gas/NEWS index d7f6a267d9..121aaa80c5 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel AVX-IFMA instructions. + * Add support for Intel PREFETCHI instructions. * Add support for Intel AMX-FP16 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 59745efb4b..adbc22de8d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1096,6 +1096,7 @@ static const arch_entry cpu_arch[] = SUBARCH (hreset, HRESET, ANY_HRESET, false), SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), + SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 55a587bfc1..7bdbd26538 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -195,6 +195,7 @@ accept various extension mnemonics. For example, @code{avx_vnni}, @code{avx512_fp16}, @code{prefetchi}, +@code{avx_ifma}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -828,9 +829,9 @@ prefix which generates REX prefix unconditionally. @samp{@{nooptimize@}} -- disable instruction size optimization. @end itemize -Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix +Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix by default. The pseudo @samp{@{vex@}} prefix can be used to encode -mnemonics of Intel VNNI instructions with the VEX prefix. +mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. @cindex conversion instructions, i386 @cindex i386 conversion instructions @@ -1488,7 +1489,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} -@item @samp{.prefetchi} +@item @samp{.prefetchi} @tab @samp{.avx_ifma} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d new file mode 100644 index 0000000000..b56ba847bf --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-intel.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dw -Mintel +#name: i386 AVX IFMA insns (Intel disassembly) +#source: avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq zmm0,zmm0,zmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 +#pass diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l new file mode 100644 index 0000000000..5294c2ca73 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: unsupported .* `vpmadd52huq' +.*:7: Error: operand .* `vpmadd52huq' diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s new file mode 100644 index 0000000000..4b763b6e45 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma-inval.s @@ -0,0 +1,7 @@ +# Check illegal in AVXIFMA instructions + + .text + .arch .noavx512ifma +_start: + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} + vpmadd52huq %zmm2, %zmm4, %zmm2 diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d new file mode 100644 index 0000000000..c84b4caad8 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dw +#name: i386 AVX IFMA insns +#source: avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq %zmm0,%zmm0,%zmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 +#pass diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s new file mode 100644 index 0000000000..81046966d7 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-ifma.s @@ -0,0 +1,40 @@ + .allow_index_reg + +.macro test_insn mnemonic + \mnemonic %xmm2, %xmm4, %xmm2 + {evex} \mnemonic %xmm2, %xmm4, %xmm2 + {vex} \mnemonic %xmm2, %xmm4, %xmm2 + {vex} \mnemonic (%ecx), %xmm4, %xmm2 + \mnemonic %ymm2, %ymm4, %ymm2 + {evex} \mnemonic %ymm2, %ymm4, %ymm2 + {vex} \mnemonic %ymm2, %ymm4, %ymm2 + {vex} \mnemonic (%ecx), %ymm4, %ymm2 +.endm + + .text +_start: + test_insn vpmadd52huq + test_insn vpmadd52luq + + .arch .noavx512vl + + vpmadd52huq %zmm0, %zmm0, %zmm0 + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .noavx512ifma + + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .noavx512f + + vpmadd52huq %ymm0, %ymm0, %ymm0 + vpmadd52huq %xmm0, %xmm0, %xmm0 + + .arch default + .arch .avx_ifma + vpmadd52huq %xmm2, %xmm4, %xmm2 + vpmadd52huq %ymm2, %ymm4, %ymm2 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 22233d7483..96ab1a02d1 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -474,6 +474,9 @@ if [gas_32_check] then { run_list_test "avx512_bf16_vl-inval" run_dump_test "avx-vnni" run_list_test "avx-vnni-inval" + run_dump_test "avx-ifma" + run_dump_test "avx-ifma-intel" + run_list_test "avx-ifma-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1142,6 +1145,9 @@ if [gas_64_check] then { run_dump_test "x86-64-amx-fp16" run_dump_test "x86-64-amx-fp16-intel" run_dump_test "x86-64-amx-fp16-bad" + run_dump_test "x86-64-avx-ifma" + run_dump_test "x86-64-avx-ifma-intel" + run_list_test "x86-64-avx-ifma-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l index 15a6fc689b..a289b23619 100644 --- a/gas/testsuite/gas/i386/noavx512-1.l +++ b/gas/testsuite/gas/i386/noavx512-1.l @@ -37,9 +37,9 @@ .*:120: Error: .*not supported.* .*:121: Error: .*not supported.* .*:122: Error: .*not supported.* -.*:126: Error: .*not supported.* -.*:127: Error: .*not supported.* -.*:128: Error: .*not supported.* +.*:126: Error: .*operand .* +.*:127: Error: .*unsupported .* +.*:128: Error: .*unsupported .* .*:135: Error: .*operand size mismatch.* .*:136: Error: .*unsupported masking.* .*:137: Error: .*unsupported masking.* @@ -50,9 +50,9 @@ .*:142: Error: .*not supported.* .*:143: Error: .*not supported.* .*:144: Error: .*not supported.* -.*:148: Error: .*not supported.* -.*:149: Error: .*not supported.* -.*:150: Error: .*not supported.* +.*:148: Error: .*operand .* +.*:149: Error: .*unsupported .* +.*:150: Error: .*unsupported .* .*:151: Error: .*not supported.* .*:157: Error: .*operand size mismatch.* .*:158: Error: .*unsupported masking.* @@ -64,9 +64,9 @@ .*:164: Error: .*not supported.* .*:165: Error: .*not supported.* .*:166: Error: .*not supported.* -.*:170: Error: .*not supported.* -.*:171: Error: .*not supported.* -.*:172: Error: .*not supported.* +.*:170: Error: .*operand .* +.*:171: Error: .*unsupported .* +.*:172: Error: .*unsupported .* .*:173: Error: .*not supported.* .*:174: Error: .*not supported.* .*:175: Error: .*not supported.* @@ -84,9 +84,9 @@ .*:189: Error: .*bad register name.* .*:190: Error: .*unknown vector operation.* .*:191: Error: .*unknown vector operation.* -.*:192: Error: .*not supported.* -.*:193: Error: .*not supported.* -.*:194: Error: .*not supported.* +.*:192: Error: .*bad register name.* +.*:193: Error: .*unknown vector operation.* +.*:194: Error: .*unknown vector operation.* .*:195: Error: .*not supported.* .*:196: Error: .*not supported.* .*:197: Error: .*not supported.* diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d new file mode 100644 index 0000000000..0b3b053e5d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw -Mintel +#name: x86-64 AVX IFMA insns (Intel disassembly) +#source: x86-64-avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l new file mode 100644 index 0000000000..fad43f6768 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l @@ -0,0 +1,4 @@ +.* Assembler messages: +.*:6: Error: unsupported .* `vpmadd52huq' +.*:7: Error: unsupported .* `vpmadd52huq' +.*:8: Error: operand .* `vpmadd52huq' diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s new file mode 100644 index 0000000000..76da0f1a37 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s @@ -0,0 +1,8 @@ +# Check illegal in AVXIFMA instructions + + .text + .arch .noavx512ifma +_start: + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} + vpmadd52huq %xmm22, %xmm4, %xmm2{%k1} + vpmadd52huq %zmm2, %zmm4, %zmm2 diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d new file mode 100644 index 0000000000..b1670b68b6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw +#name: x86-64 AVX IFMA insns +#source: x86-64-avx-ifma.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s new file mode 100644 index 0000000000..bfc524a103 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s @@ -0,0 +1,23 @@ + .allow_index_reg + +.macro test_insn mnemonic + \mnemonic %xmm12, %xmm4, %xmm2 + {evex} \mnemonic %xmm12, %xmm4, %xmm2 + {vex} \mnemonic %xmm12, %xmm4, %xmm2 + {vex} \mnemonic (%rcx), %xmm4, %xmm2 + \mnemonic %xmm22, %xmm4, %xmm2 + \mnemonic %ymm12, %ymm4, %ymm2 + {evex} \mnemonic %ymm12, %ymm4, %ymm2 + {vex} \mnemonic %ymm12, %ymm4, %ymm2 + {vex} \mnemonic (%rcx), %ymm4, %ymm2 + \mnemonic %ymm22, %ymm4, %ymm2 +.endm + + .text +_start: + test_insn vpmadd52huq + test_insn vpmadd52luq + + .arch .avx_ifma + vpmadd52huq %xmm12, %xmm4, %xmm2 + vpmadd52huq %ymm12, %ymm4, %ymm2 diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 070af858f5..65935a328c 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -495,8 +495,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, - { "vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, + { VEX_W_TABLE (VEX_W_0F38B4) }, + { VEX_W_TABLE (VEX_W_0F38B5) }, { "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, { "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, /* B8 */ diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index fb197c40ea..ba232939d7 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1534,6 +1534,8 @@ enum VEX_W_0F385E_X86_64_P_3, VEX_W_0F3878, VEX_W_0F3879, + VEX_W_0F38B4, + VEX_W_0F38B5, VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1, @@ -6316,8 +6318,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38B4) }, + { VEX_W_TABLE (VEX_W_0F38B5) }, { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, /* b8 */ @@ -7631,6 +7633,16 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3879 */ { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, }, + { + /* VEX_W_0F38B4 */ + { Bad_Opcode }, + { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, + }, + { + /* VEX_W_0F38B5 */ + { Bad_Opcode }, + { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, + }, { /* VEX_W_0F38CF */ { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index c6837dbb4c..dd759fbc7c 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -247,6 +247,8 @@ static initializer cpu_flag_init[] = "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" }, { "CPU_PREFETCHI_FLAGS", "CpuPREFETCHI"}, + { "CPU_AVX_IFMA_FLAGS", + "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -374,7 +376,7 @@ static initializer cpu_flag_init[] = { "CPU_ANY_AVX_FLAGS", "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, { "CPU_ANY_AVX2_FLAGS", - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" }, + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" }, { "CPU_ANY_AVX512F_FLAGS", "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, { "CPU_ANY_AVX512CD_FLAGS", @@ -445,6 +447,8 @@ static initializer cpu_flag_init[] = "CpuAVX512_FP16" }, { "CPU_ANY_PREFETCHI_FLAGS", "CpuPREFETCHI" }, + { "CPU_ANY_AVX_IFMA_FLAGS", + "CpuAVX_IFMA" }, }; static initializer operand_type_init[] = @@ -647,6 +651,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_VNNI), BITFIELD (CpuAVX512_FP16), BITFIELD (CpuPREFETCHI), + BITFIELD (CpuAVX_IFMA), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 0875f787cc..7cd601e924 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -211,6 +211,8 @@ enum CpuAVX512_FP16, /* PREFETCHI instruction required */ CpuPREFETCHI, + /* Intel AVX IFMA Instructions support required. */ + CpuAVX_IFMA, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -393,6 +395,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_vnni:1; unsigned int cpuavx512_fp16:1; unsigned int cpuprefetchi:1; + unsigned int cpuavx_ifma:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 00bbf57ccf..489a5335e2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2811,6 +2811,13 @@ vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|Ve // AVX512IFMA instructions end +// AVX-IFMA instructions. + +vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } + +// AVX-IFMA instructions end. + // AVX512VBMI instructions vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/6] Support Intel AVX-IFMA 2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang @ 2022-10-31 16:52 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:52 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich, Hongyu Wang On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > From: Hongyu Wang <hongyu.wang@intel.com> > > x86: Support Intel AVX-IFMA > > Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is > cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions > are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX > encoding for Intel IFMA instructions. > > gas/ > > * NEWS: Support Intel AVX-IFMA. > * config/tc-i386.c (cpu_arch): Add avx_ifma. > * doc/c-i386.texi: Document .avx_ifma. > * testsuite/gas/i386/avx-ifma.d: New file. > * testsuite/gas/i386/avx-ifma-intel.d: Likewise. > * testsuite/gas/i386/avx-ifma.s: Likewise. > * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. > * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. > * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. > * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. > > opcodes/ > > * i386-dis.c (PREFIX_VEX_0F38B4): New. > (PREFIX_VEX_0F38B5): Likewise. > (VEX_W_0F38B4_P_2): Likewise. > (VEX_W_0F38B5_P_2): Likewise. > (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. > (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. > * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. > * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in > CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and > CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. > (cpu_flags): Add CpuAVX_IFMA. > * i386-opc.h (CpuAVX_IFMA): New. > (i386_cpu_flags): Add cpuavx_ifma. > * i386-opc.tbl: Add Intel AVX IFMA instructions. > * i386-init.h: Regenerated. > * i386-tbl.h: Likewise. > > Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 7 +- > gas/testsuite/gas/i386/avx-ifma-intel.d | 37 + > gas/testsuite/gas/i386/avx-ifma-inval.l | 3 + > gas/testsuite/gas/i386/avx-ifma-inval.s | 7 + > gas/testsuite/gas/i386/avx-ifma.d | 37 + > gas/testsuite/gas/i386/avx-ifma.s | 40 + > gas/testsuite/gas/i386/i386.exp | 6 + > gas/testsuite/gas/i386/noavx512-1.l | 24 +- > .../gas/i386/x86-64-avx-ifma-intel.d | 34 + > .../gas/i386/x86-64-avx-ifma-inval.l | 4 + > .../gas/i386/x86-64-avx-ifma-inval.s | 8 + > gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 + > gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 + > opcodes/i386-dis-evex.h | 4 +- > opcodes/i386-dis.c | 16 +- > opcodes/i386-gen.c | 7 +- > opcodes/i386-init.h | 524 +- > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 7 + > opcodes/i386-tbl.h | 7810 +++++++++-------- > 22 files changed, 4477 insertions(+), 4161 deletions(-) > create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d > create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l > create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s > create mode 100644 gas/testsuite/gas/i386/avx-ifma.d > create mode 100644 gas/testsuite/gas/i386/avx-ifma.s > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s > > diff --git a/gas/NEWS b/gas/NEWS > index d7f6a267d9..121aaa80c5 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel AVX-IFMA instructions. > + > * Add support for Intel PREFETCHI instructions. > > * Add support for Intel AMX-FP16 instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 59745efb4b..adbc22de8d 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1096,6 +1096,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (hreset, HRESET, ANY_HRESET, false), > SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), > SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), > + SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 55a587bfc1..7bdbd26538 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -195,6 +195,7 @@ accept various extension mnemonics. For example, > @code{avx_vnni}, > @code{avx512_fp16}, > @code{prefetchi}, > +@code{avx_ifma}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -828,9 +829,9 @@ prefix which generates REX prefix unconditionally. > @samp{@{nooptimize@}} -- disable instruction size optimization. > @end itemize > > -Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix > +Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix > by default. The pseudo @samp{@{vex@}} prefix can be used to encode > -mnemonics of Intel VNNI instructions with the VEX prefix. > +mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. > > @cindex conversion instructions, i386 > @cindex i386 conversion instructions > @@ -1488,7 +1489,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > -@item @samp{.prefetchi} > +@item @samp{.prefetchi} @tab @samp{.avx_ifma} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d > new file mode 100644 > index 0000000000..b56ba847bf > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ifma-intel.d > @@ -0,0 +1,37 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 AVX IFMA insns (Intel disassembly) > +#source: avx-ifma.s > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\] > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\] > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\] > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\] > +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq zmm0,zmm0,zmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq ymm0,ymm0,ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq xmm0,xmm0,xmm0 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2 > +#pass > diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l > new file mode 100644 > index 0000000000..5294c2ca73 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ifma-inval.l > @@ -0,0 +1,3 @@ > +.* Assembler messages: > +.*:6: Error: unsupported .* `vpmadd52huq' > +.*:7: Error: operand .* `vpmadd52huq' > diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s > new file mode 100644 > index 0000000000..4b763b6e45 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ifma-inval.s > @@ -0,0 +1,7 @@ > +# Check illegal in AVXIFMA instructions > + > + .text > + .arch .noavx512ifma > +_start: > + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} > + vpmadd52huq %zmm2, %zmm4, %zmm2 > diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d > new file mode 100644 > index 0000000000..c84b4caad8 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ifma.d > @@ -0,0 +1,37 @@ > +#as: > +#objdump: -dw > +#name: i386 AVX IFMA insns > +#source: avx-ifma.s > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 b5 c0[ ]*vpmadd52huq %zmm0,%zmm0,%zmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 fd b5 c0[ ]*\{vex\} vpmadd52huq %ymm0,%ymm0,%ymm0 > +[ ]*[a-f0-9]+:[ ]*c4 e2 f9 b5 c0[ ]*\{vex\} vpmadd52huq %xmm0,%xmm0,%xmm0 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2 > +#pass > diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s > new file mode 100644 > index 0000000000..81046966d7 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-ifma.s > @@ -0,0 +1,40 @@ > + .allow_index_reg > + > +.macro test_insn mnemonic > + \mnemonic %xmm2, %xmm4, %xmm2 > + {evex} \mnemonic %xmm2, %xmm4, %xmm2 > + {vex} \mnemonic %xmm2, %xmm4, %xmm2 > + {vex} \mnemonic (%ecx), %xmm4, %xmm2 > + \mnemonic %ymm2, %ymm4, %ymm2 > + {evex} \mnemonic %ymm2, %ymm4, %ymm2 > + {vex} \mnemonic %ymm2, %ymm4, %ymm2 > + {vex} \mnemonic (%ecx), %ymm4, %ymm2 > +.endm > + > + .text > +_start: > + test_insn vpmadd52huq > + test_insn vpmadd52luq > + > + .arch .noavx512vl > + > + vpmadd52huq %zmm0, %zmm0, %zmm0 > + vpmadd52huq %ymm0, %ymm0, %ymm0 > + vpmadd52huq %xmm0, %xmm0, %xmm0 > + > + .arch default > + .arch .noavx512ifma > + > + vpmadd52huq %ymm0, %ymm0, %ymm0 > + vpmadd52huq %xmm0, %xmm0, %xmm0 > + > + .arch default > + .arch .noavx512f > + > + vpmadd52huq %ymm0, %ymm0, %ymm0 > + vpmadd52huq %xmm0, %xmm0, %xmm0 > + > + .arch default > + .arch .avx_ifma > + vpmadd52huq %xmm2, %xmm4, %xmm2 > + vpmadd52huq %ymm2, %ymm4, %ymm2 > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index 22233d7483..96ab1a02d1 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -474,6 +474,9 @@ if [gas_32_check] then { > run_list_test "avx512_bf16_vl-inval" > run_dump_test "avx-vnni" > run_list_test "avx-vnni-inval" > + run_dump_test "avx-ifma" > + run_dump_test "avx-ifma-intel" > + run_list_test "avx-ifma-inval" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1142,6 +1145,9 @@ if [gas_64_check] then { > run_dump_test "x86-64-amx-fp16" > run_dump_test "x86-64-amx-fp16-intel" > run_dump_test "x86-64-amx-fp16-bad" > + run_dump_test "x86-64-avx-ifma" > + run_dump_test "x86-64-avx-ifma-intel" > + run_list_test "x86-64-avx-ifma-inval" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l > index 15a6fc689b..a289b23619 100644 > --- a/gas/testsuite/gas/i386/noavx512-1.l > +++ b/gas/testsuite/gas/i386/noavx512-1.l > @@ -37,9 +37,9 @@ > .*:120: Error: .*not supported.* > .*:121: Error: .*not supported.* > .*:122: Error: .*not supported.* > -.*:126: Error: .*not supported.* > -.*:127: Error: .*not supported.* > -.*:128: Error: .*not supported.* > +.*:126: Error: .*operand .* > +.*:127: Error: .*unsupported .* > +.*:128: Error: .*unsupported .* > .*:135: Error: .*operand size mismatch.* > .*:136: Error: .*unsupported masking.* > .*:137: Error: .*unsupported masking.* > @@ -50,9 +50,9 @@ > .*:142: Error: .*not supported.* > .*:143: Error: .*not supported.* > .*:144: Error: .*not supported.* > -.*:148: Error: .*not supported.* > -.*:149: Error: .*not supported.* > -.*:150: Error: .*not supported.* > +.*:148: Error: .*operand .* > +.*:149: Error: .*unsupported .* > +.*:150: Error: .*unsupported .* > .*:151: Error: .*not supported.* > .*:157: Error: .*operand size mismatch.* > .*:158: Error: .*unsupported masking.* > @@ -64,9 +64,9 @@ > .*:164: Error: .*not supported.* > .*:165: Error: .*not supported.* > .*:166: Error: .*not supported.* > -.*:170: Error: .*not supported.* > -.*:171: Error: .*not supported.* > -.*:172: Error: .*not supported.* > +.*:170: Error: .*operand .* > +.*:171: Error: .*unsupported .* > +.*:172: Error: .*unsupported .* > .*:173: Error: .*not supported.* > .*:174: Error: .*not supported.* > .*:175: Error: .*not supported.* > @@ -84,9 +84,9 @@ > .*:189: Error: .*bad register name.* > .*:190: Error: .*unknown vector operation.* > .*:191: Error: .*unknown vector operation.* > -.*:192: Error: .*not supported.* > -.*:193: Error: .*not supported.* > -.*:194: Error: .*not supported.* > +.*:192: Error: .*bad register name.* > +.*:193: Error: .*unknown vector operation.* > +.*:194: Error: .*unknown vector operation.* > .*:195: Error: .*not supported.* > .*:196: Error: .*not supported.* > .*:197: Error: .*not supported.* > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d > new file mode 100644 > index 0000000000..0b3b053e5d > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d > @@ -0,0 +1,34 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86-64 AVX IFMA insns (Intel disassembly) > +#source: x86-64-avx-ifma.s > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\] > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\] > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\] > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\] > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12 > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l > new file mode 100644 > index 0000000000..fad43f6768 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l > @@ -0,0 +1,4 @@ > +.* Assembler messages: > +.*:6: Error: unsupported .* `vpmadd52huq' > +.*:7: Error: unsupported .* `vpmadd52huq' > +.*:8: Error: operand .* `vpmadd52huq' > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s > new file mode 100644 > index 0000000000..76da0f1a37 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s > @@ -0,0 +1,8 @@ > +# Check illegal in AVXIFMA instructions > + > + .text > + .arch .noavx512ifma > +_start: > + vpmadd52huq %xmm2, %xmm4, %xmm2{%k6} > + vpmadd52huq %xmm22, %xmm4, %xmm2{%k1} > + vpmadd52huq %zmm2, %zmm4, %zmm2 > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d > new file mode 100644 > index 0000000000..b1670b68b6 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d > @@ -0,0 +1,34 @@ > +#as: > +#objdump: -dw > +#name: x86-64 AVX IFMA insns > +#source: x86-64-avx-ifma.s > + > +.*: +file format .* > + > + > +Disassembly of section .text: > + > +0+ <_start>: > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2 > +[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2 > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s > new file mode 100644 > index 0000000000..bfc524a103 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s > @@ -0,0 +1,23 @@ > + .allow_index_reg > + > +.macro test_insn mnemonic > + \mnemonic %xmm12, %xmm4, %xmm2 > + {evex} \mnemonic %xmm12, %xmm4, %xmm2 > + {vex} \mnemonic %xmm12, %xmm4, %xmm2 > + {vex} \mnemonic (%rcx), %xmm4, %xmm2 > + \mnemonic %xmm22, %xmm4, %xmm2 > + \mnemonic %ymm12, %ymm4, %ymm2 > + {evex} \mnemonic %ymm12, %ymm4, %ymm2 > + {vex} \mnemonic %ymm12, %ymm4, %ymm2 > + {vex} \mnemonic (%rcx), %ymm4, %ymm2 > + \mnemonic %ymm22, %ymm4, %ymm2 > +.endm > + > + .text > +_start: > + test_insn vpmadd52huq > + test_insn vpmadd52luq > + > + .arch .avx_ifma > + vpmadd52huq %xmm12, %xmm4, %xmm2 > + vpmadd52huq %ymm12, %ymm4, %ymm2 > diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h > index 070af858f5..65935a328c 100644 > --- a/opcodes/i386-dis-evex.h > +++ b/opcodes/i386-dis-evex.h > @@ -495,8 +495,8 @@ static const struct dis386 evex_table[][256] = { > { Bad_Opcode }, > { Bad_Opcode }, > { Bad_Opcode }, > - { "vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, > - { "vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, > + { VEX_W_TABLE (VEX_W_0F38B4) }, > + { VEX_W_TABLE (VEX_W_0F38B5) }, > { "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, > { "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA }, > /* B8 */ > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index fb197c40ea..ba232939d7 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -1534,6 +1534,8 @@ enum > VEX_W_0F385E_X86_64_P_3, > VEX_W_0F3878, > VEX_W_0F3879, > + VEX_W_0F38B4, > + VEX_W_0F38B5, > VEX_W_0F38CF, > VEX_W_0F3A00_L_1, > VEX_W_0F3A01_L_1, > @@ -6316,8 +6318,8 @@ static const struct dis386 vex_table[][256] = { > { Bad_Opcode }, > { Bad_Opcode }, > { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > + { VEX_W_TABLE (VEX_W_0F38B4) }, > + { VEX_W_TABLE (VEX_W_0F38B5) }, > { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, > { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, > /* b8 */ > @@ -7631,6 +7633,16 @@ static const struct dis386 vex_w_table[][2] = { > /* VEX_W_0F3879 */ > { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, > }, > + { > + /* VEX_W_0F38B4 */ > + { Bad_Opcode }, > + { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, > + }, > + { > + /* VEX_W_0F38B5 */ > + { Bad_Opcode }, > + { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, > + }, > { > /* VEX_W_0F38CF */ > { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index c6837dbb4c..dd759fbc7c 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -247,6 +247,8 @@ static initializer cpu_flag_init[] = > "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" }, > { "CPU_PREFETCHI_FLAGS", > "CpuPREFETCHI"}, > + { "CPU_AVX_IFMA_FLAGS", > + "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -374,7 +376,7 @@ static initializer cpu_flag_init[] = > { "CPU_ANY_AVX_FLAGS", > "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, > { "CPU_ANY_AVX2_FLAGS", > - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" }, > + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" }, > { "CPU_ANY_AVX512F_FLAGS", > "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, > { "CPU_ANY_AVX512CD_FLAGS", > @@ -445,6 +447,8 @@ static initializer cpu_flag_init[] = > "CpuAVX512_FP16" }, > { "CPU_ANY_PREFETCHI_FLAGS", > "CpuPREFETCHI" }, > + { "CPU_ANY_AVX_IFMA_FLAGS", > + "CpuAVX_IFMA" }, > }; > > static initializer operand_type_init[] = > @@ -647,6 +651,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuAVX_VNNI), > BITFIELD (CpuAVX512_FP16), > BITFIELD (CpuPREFETCHI), > + BITFIELD (CpuAVX_IFMA), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 0875f787cc..7cd601e924 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -211,6 +211,8 @@ enum > CpuAVX512_FP16, > /* PREFETCHI instruction required */ > CpuPREFETCHI, > + /* Intel AVX IFMA Instructions support required. */ > + CpuAVX_IFMA, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -393,6 +395,7 @@ typedef union i386_cpu_flags > unsigned int cpuavx_vnni:1; > unsigned int cpuavx512_fp16:1; > unsigned int cpuprefetchi:1; > + unsigned int cpuavx_ifma:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 00bbf57ccf..489a5335e2 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -2811,6 +2811,13 @@ vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|Ve > > // AVX512IFMA instructions end > > +// AVX-IFMA instructions. > + > +vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > + > +// AVX-IFMA instructions end. > + > // AVX512VBMI instructions > > vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/6] Support Intel AVX-VNNI-INT8 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang 2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:53 ` H.J. Lu 2022-11-02 10:45 ` Jan Beulich 2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang ` (3 subsequent siblings) 5 siblings, 2 replies; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools, Cui,Lili From: "Cui,Lili" <lili.cui@intel.com> gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/avx-vnni-int8-intel.d | 71 ++ gas/testsuite/gas/i386/avx-vnni-int8.d | 71 ++ gas/testsuite/gas/i386/avx-vnni-int8.s | 127 +++ gas/testsuite/gas/i386/i386.exp | 4 + .../gas/i386/x86-64-avx-vnni-int8-intel.d | 71 ++ gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d | 71 ++ gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s | 127 +++ opcodes/i386-dis.c | 23 +- opcodes/i386-gen.c | 7 +- opcodes/i386-init.h | 140 +-- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 11 + opcodes/i386-tbl.h | 882 ++++++++++-------- 16 files changed, 1159 insertions(+), 457 deletions(-) create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8-intel.d create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.d create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s diff --git a/gas/NEWS b/gas/NEWS index 121aaa80c5..1547bfd469 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel AVX-VNNI-INT8 instructions. + * Add support for Intel AVX-IFMA instructions. * Add support for Intel PREFETCHI instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index adbc22de8d..26d8efb47e 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), + SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 7bdbd26538..029f5f2e04 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -196,6 +196,7 @@ accept various extension mnemonics. For example, @code{avx512_fp16}, @code{prefetchi}, @code{avx_ifma}, +@code{avx_vnni_int8}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1489,7 +1490,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} -@item @samp{.prefetchi} @tab @samp{.avx_ifma} +@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d new file mode 100644 index 0000000000..1d7d162f20 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d @@ -0,0 +1,71 @@ +#as: +#objdump: -dw -Mintel +#name: i386 AVX-VNNI-INT8 insns (Intel disassembly) +#source: avx-vnni-int8.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds ymm6,ymm5,ymm4 +\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds xmm6,xmm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] +\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\] +\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] +#pass diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.d b/gas/testsuite/gas/i386/avx-vnni-int8.d new file mode 100644 index 0000000000..cd4499e59f --- /dev/null +++ b/gas/testsuite/gas/i386/avx-vnni-int8.d @@ -0,0 +1,71 @@ +#as: +#objdump: -dw +#name: i386 AVX-VNNI-INT8 insns +#source: avx-vnni-int8.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd -0x800\(%edx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds -0x800\(%edx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud -0x800\(%edx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds -0x800\(%edx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud -0x800\(%edx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds %ymm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds %xmm4,%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds \(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%ecx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds -0x1000\(%edx\),%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds \(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds 0x7f0\(%ecx\),%xmm5,%xmm6 +\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds -0x800\(%edx\),%xmm5,%xmm6 +#pass diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.s b/gas/testsuite/gas/i386/avx-vnni-int8.s new file mode 100644 index 0000000000..e3cfeb6680 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-vnni-int8.s @@ -0,0 +1,127 @@ +# Check 32bit AVX-VNNI-INT8 instructions + + .allow_index_reg + .text +_start: + vpdpbssd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssd %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssd 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssd (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssd 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssd -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssd 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssd (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssd 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssd -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbssds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbssds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbssds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbsuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbsuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 + vpdpbuuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 + vpdpbuuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) + +.intel_syntax noprefix + vpdpbssd ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbssd xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbssd ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssd ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssd xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssd xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbssds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbssds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbssds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsud ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbsud xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbsud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbsuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbsuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuud ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbuud xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbuud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 + vpdpbuuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 + vpdpbuuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 + vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 96ab1a02d1..b75fe85cb3 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -477,6 +477,8 @@ if [gas_32_check] then { run_dump_test "avx-ifma" run_dump_test "avx-ifma-intel" run_list_test "avx-ifma-inval" + run_dump_test "avx-vnni-int8" + run_dump_test "avx-vnni-int8-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1148,6 +1150,8 @@ if [gas_64_check] then { run_dump_test "x86-64-avx-ifma" run_dump_test "x86-64-avx-ifma-intel" run_list_test "x86-64-avx-ifma-inval" + run_dump_test "x86-64-avx-vnni-int8" + run_dump_test "x86-64-avx-vnni-int8-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d new file mode 100644 index 0000000000..61c01124ef --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d @@ -0,0 +1,71 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 AVX-VNNI-INT8 insns (Intel disassembly) +#source: x86-64-avx-vnni-int8.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds ymm10,ymm9,ymm8 +\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds xmm10,xmm9,xmm8 +\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] +\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] +\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[r9\] +\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] +\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d new file mode 100644 index 0000000000..90faed581b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d @@ -0,0 +1,71 @@ +#as: +#objdump: -dw +#name: x86_64 AVX-VNNI-INT8 insns +#source: x86-64-avx-vnni-int8.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd -0x800\(%rdx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds -0x800\(%rdx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud -0x800\(%rdx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds -0x800\(%rdx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud -0x800\(%rdx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds %ymm8,%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds %xmm8,%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds \(%r9\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%rcx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds -0x1000\(%rdx\),%ymm9,%ymm10 +\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds \(%r9\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds 0x7f0\(%rcx\),%xmm9,%xmm10 +\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds -0x800\(%rdx\),%xmm9,%xmm10 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s new file mode 100644 index 0000000000..bc9145b26f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s @@ -0,0 +1,127 @@ +# Check 64bit AVX-VNNI-INT8 instructions + + .allow_index_reg + .text +_start: + vpdpbssd %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssd %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssd 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssd (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssd 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssd -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssd 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssd (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssd 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssd -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbssds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbssds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbssds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbsuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbsuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 + vpdpbuuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 + vpdpbuuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) + +.intel_syntax noprefix + vpdpbssd ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbssd xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbssd ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssd ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbssd ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssd ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssd xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssd xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbssd xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssd xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbssds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbssds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbssds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbssds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbssds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbssds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbssds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbssds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbssds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsud ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbsud xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbsud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbsud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbsud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbsuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbsuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbsuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuud ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbuud xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbuud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbuud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbuud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) + vpdpbuuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 + vpdpbuuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 + vpdpbuuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index ba232939d7..436d2e7a08 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1132,6 +1132,8 @@ enum PREFIX_VEX_0FF0, PREFIX_VEX_0F3849_X86_64, PREFIX_VEX_0F384B_X86_64, + PREFIX_VEX_0F3850_W_0, + PREFIX_VEX_0F3851_W_0, PREFIX_VEX_0F385C_X86_64, PREFIX_VEX_0F385E_X86_64, PREFIX_VEX_0F38F5_L_0, @@ -4014,6 +4016,21 @@ static const struct dis386 prefix_table[][4] = { { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, }, + /* PREFIX_VEX_0F3850_W_0 */ + { + { "vpdpbuud", { XM, Vex, EXx }, 0 }, + { "vpdpbsud", { XM, Vex, EXx }, 0 }, + { "%XVvpdpbusd", { XM, Vex, EXx }, 0 }, + { "vpdpbssd", { XM, Vex, EXx }, 0 }, + }, + + /* PREFIX_VEX_0F3851_W_0 */ + { + { "vpdpbuuds", { XM, Vex, EXx }, 0 }, + { "vpdpbsuds", { XM, Vex, EXx }, 0 }, + { "%XVvpdpbusds", { XM, Vex, EXx }, 0 }, + { "vpdpbssds", { XM, Vex, EXx }, 0 }, + }, /* PREFIX_VEX_0F385C_X86_64 */ { { Bad_Opcode }, @@ -7575,11 +7592,11 @@ static const struct dis386 vex_w_table[][2] = { }, { /* VEX_W_0F3850 */ - { "%XVvpdpbusd", { XM, Vex, EXx }, PREFIX_DATA }, + { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, }, { - /* VEX_W_0F3851 */ - { "%XVvpdpbusds", { XM, Vex, EXx }, PREFIX_DATA }, + /* VEX_W_0F3851_P_0 */ + { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, }, { /* VEX_W_0F3852 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index dd759fbc7c..21986220d6 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -249,6 +249,8 @@ static initializer cpu_flag_init[] = "CpuPREFETCHI"}, { "CPU_AVX_IFMA_FLAGS", "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, + { "CPU_AVX_VNNI_INT8_FLAGS", + "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -376,7 +378,7 @@ static initializer cpu_flag_init[] = { "CPU_ANY_AVX_FLAGS", "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, { "CPU_ANY_AVX2_FLAGS", - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" }, + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8" }, { "CPU_ANY_AVX512F_FLAGS", "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, { "CPU_ANY_AVX512CD_FLAGS", @@ -449,6 +451,8 @@ static initializer cpu_flag_init[] = "CpuPREFETCHI" }, { "CPU_ANY_AVX_IFMA_FLAGS", "CpuAVX_IFMA" }, + { "CPU_ANY_AVX_VNNI_INT8_FLAGS", + "CpuAVX_VNNI_INT8" }, }; static initializer operand_type_init[] = @@ -652,6 +656,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX512_FP16), BITFIELD (CpuPREFETCHI), BITFIELD (CpuAVX_IFMA), + BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 7cd601e924..905908749b 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -213,6 +213,8 @@ enum CpuPREFETCHI, /* Intel AVX IFMA Instructions support required. */ CpuAVX_IFMA, + /* Intel AVX VNNI-INT8 Instructions support required. */ + CpuAVX_VNNI_INT8, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -296,7 +298,7 @@ enum /* If you get a compiler error for zero width of the unused field, comment it out. */ -#define CpuUnused (CpuMax + 1) +// #define CpuUnused (CpuMax + 1) /* We can check if an instruction is available with array instead of bitfield. */ @@ -396,6 +398,7 @@ typedef union i386_cpu_flags unsigned int cpuavx512_fp16:1; unsigned int cpuprefetchi:1; unsigned int cpuavx_ifma:1; + unsigned int cpuavx_vnni_int8:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 489a5335e2..77a5787c4b 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2888,6 +2888,17 @@ vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckReg // AVX_VNNI instructions end +// AVX-VNNI-INT8 instructions. + +vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } + +// AVX-VNNI-INT8 instructions end. + // AVX512_BITALG instructions vpopcnt<bw>, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/6] Support Intel AVX-VNNI-INT8 2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang @ 2022-10-31 16:53 ` H.J. Lu 2022-11-02 10:45 ` Jan Beulich 1 sibling, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:53 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich, Cui,Lili On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > From: "Cui,Lili" <lili.cui@intel.com> > > gas/ > * NEWS: Support Intel AVX-VNNI-INT8. > * config/tc-i386.c: Add avx_vnni_int8. > * doc/c-i386.texi: Document avx_vnni_int8. > * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. > * testsuite/gas/i386/avx-vnni-int8.d: Likewise. > * testsuite/gas/i386/avx-vnni-int8.s: Likewise. > * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. > * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. > * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. > * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. > > opcodes/ > * i386-dis.c: (PREFIX_VEX_0F3850) New. > (PREFIX_VEX_0F3851): Likewise. > (VEX_W_0F3850_P_0): Likewise. > (VEX_W_0F3850_P_1): Likewise. > (VEX_W_0F3850_P_2): Likewise. > (VEX_W_0F3850_P_3): Likewise. > (VEX_W_0F3851_P_0): Likewise. > (VEX_W_0F3851_P_1): Likewise. > (VEX_W_0F3851_P_2): Likewise. > (VEX_W_0F3851_P_3): Likewise. > (VEX_W_0F3850): Delete. > (VEX_W_0F3851): Likewise. > (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. > (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, > delete VEX_W_0F3850 and VEX_W_0F3851. > (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 > VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 > and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. > * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS > and CPU_ANY_AVX_VNNI_INT8_FLAGS. > (cpu_flags): Add CpuAVX_VNNI_INT8. > * i386-opc.h (CpuAVX_VNNI_INT8): New. > * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. > * i386-init.h: Regenerated. > * i386-tbl.h: Likewise. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/avx-vnni-int8-intel.d | 71 ++ > gas/testsuite/gas/i386/avx-vnni-int8.d | 71 ++ > gas/testsuite/gas/i386/avx-vnni-int8.s | 127 +++ > gas/testsuite/gas/i386/i386.exp | 4 + > .../gas/i386/x86-64-avx-vnni-int8-intel.d | 71 ++ > gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d | 71 ++ > gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s | 127 +++ > opcodes/i386-dis.c | 23 +- > opcodes/i386-gen.c | 7 +- > opcodes/i386-init.h | 140 +-- > opcodes/i386-opc.h | 5 +- > opcodes/i386-opc.tbl | 11 + > opcodes/i386-tbl.h | 882 ++++++++++-------- > 16 files changed, 1159 insertions(+), 457 deletions(-) > create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8-intel.d > create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.d > create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.s > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d > create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s > > diff --git a/gas/NEWS b/gas/NEWS > index 121aaa80c5..1547bfd469 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel AVX-VNNI-INT8 instructions. > + > * Add support for Intel AVX-IFMA instructions. > > * Add support for Intel PREFETCHI instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index adbc22de8d..26d8efb47e 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), > SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > + SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 7bdbd26538..029f5f2e04 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -196,6 +196,7 @@ accept various extension mnemonics. For example, > @code{avx512_fp16}, > @code{prefetchi}, > @code{avx_ifma}, > +@code{avx_vnni_int8}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1489,7 +1490,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > -@item @samp{.prefetchi} @tab @samp{.avx_ifma} > +@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d > new file mode 100644 > index 0000000000..1d7d162f20 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d > @@ -0,0 +1,71 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 AVX-VNNI-INT8 insns (Intel disassembly) > +#source: avx-vnni-int8.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds ymm6,ymm5,ymm4 > +\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds xmm6,xmm5,xmm4 > +\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\] > +\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\] > +\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\] > +#pass > diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.d b/gas/testsuite/gas/i386/avx-vnni-int8.d > new file mode 100644 > index 0000000000..cd4499e59f > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-vnni-int8.d > @@ -0,0 +1,71 @@ > +#as: > +#objdump: -dw > +#name: i386 AVX-VNNI-INT8 insns > +#source: avx-vnni-int8.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd -0x800\(%edx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds -0x800\(%edx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud -0x800\(%edx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds -0x800\(%edx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud -0x800\(%edx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds %ymm4,%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds %xmm4,%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds \(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%ecx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds -0x1000\(%edx\),%ymm5,%ymm6 > +\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds \(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds 0x7f0\(%ecx\),%xmm5,%xmm6 > +\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds -0x800\(%edx\),%xmm5,%xmm6 > +#pass > diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.s b/gas/testsuite/gas/i386/avx-vnni-int8.s > new file mode 100644 > index 0000000000..e3cfeb6680 > --- /dev/null > +++ b/gas/testsuite/gas/i386/avx-vnni-int8.s > @@ -0,0 +1,127 @@ > +# Check 32bit AVX-VNNI-INT8 instructions > + > + .allow_index_reg > + .text > +_start: > + vpdpbssd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssd %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssd 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssd (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssd 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssd -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssd 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssd (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssd 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssd -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbssds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbssds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbssds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbsuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbsuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 > + vpdpbuuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 > + vpdpbuuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff) > + > +.intel_syntax noprefix > + vpdpbssd ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbssd xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbssd ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssd ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssd xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssd xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbssds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbssds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbssds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsud ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbsud xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbsud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbsuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbsuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuud ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbuud xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbuud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8 > + vpdpbuuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8 > + vpdpbuuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8 > + vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index 96ab1a02d1..b75fe85cb3 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -477,6 +477,8 @@ if [gas_32_check] then { > run_dump_test "avx-ifma" > run_dump_test "avx-ifma-intel" > run_list_test "avx-ifma-inval" > + run_dump_test "avx-vnni-int8" > + run_dump_test "avx-vnni-int8-intel" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1148,6 +1150,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-avx-ifma" > run_dump_test "x86-64-avx-ifma-intel" > run_list_test "x86-64-avx-ifma-inval" > + run_dump_test "x86-64-avx-vnni-int8" > + run_dump_test "x86-64-avx-vnni-int8-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d > new file mode 100644 > index 0000000000..61c01124ef > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d > @@ -0,0 +1,71 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 AVX-VNNI-INT8 insns (Intel disassembly) > +#source: x86-64-avx-vnni-int8.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds ymm10,ymm9,ymm8 > +\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds xmm10,xmm9,xmm8 > +\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\] > +\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\] > +\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\] > +\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[r9\] > +\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\] > +\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\] > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d > new file mode 100644 > index 0000000000..90faed581b > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d > @@ -0,0 +1,71 @@ > +#as: > +#objdump: -dw > +#name: x86_64 AVX-VNNI-INT8 insns > +#source: x86-64-avx-vnni-int8.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd -0x800\(%rdx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds -0x800\(%rdx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud -0x800\(%rdx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds -0x800\(%rdx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud -0x800\(%rdx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds %ymm8,%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds %xmm8,%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds \(%r9\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%rcx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds -0x1000\(%rdx\),%ymm9,%ymm10 > +\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds \(%r9\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds 0x7f0\(%rcx\),%xmm9,%xmm10 > +\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds -0x800\(%rdx\),%xmm9,%xmm10 > +#pass > diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s > new file mode 100644 > index 0000000000..bc9145b26f > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s > @@ -0,0 +1,127 @@ > +# Check 64bit AVX-VNNI-INT8 instructions > + > + .allow_index_reg > + .text > +_start: > + vpdpbssd %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssd %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssd 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssd (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssd 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssd -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssd 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssd (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssd 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssd -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbssds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbssds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbssds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbsuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbsuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8 > + vpdpbuuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8 > + vpdpbuuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff) > + > +.intel_syntax noprefix > + vpdpbssd ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbssd xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbssd ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssd ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbssd ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssd ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssd xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssd xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbssd xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssd xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbssds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbssds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbssds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbssds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbssds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbssds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbssds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbssds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbssds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsud ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbsud xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbsud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbsud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbsud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbsuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbsuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbsuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbsuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbsuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuud ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbuud xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbuud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbuud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbuud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > + vpdpbuuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8 > + vpdpbuuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8 > + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000) > + vpdpbuuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff) > + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8 > + vpdpbuuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8 > + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000) > + vpdpbuuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff) > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index ba232939d7..436d2e7a08 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -1132,6 +1132,8 @@ enum > PREFIX_VEX_0FF0, > PREFIX_VEX_0F3849_X86_64, > PREFIX_VEX_0F384B_X86_64, > + PREFIX_VEX_0F3850_W_0, > + PREFIX_VEX_0F3851_W_0, > PREFIX_VEX_0F385C_X86_64, > PREFIX_VEX_0F385E_X86_64, > PREFIX_VEX_0F38F5_L_0, > @@ -4014,6 +4016,21 @@ static const struct dis386 prefix_table[][4] = { > { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, > }, > > + /* PREFIX_VEX_0F3850_W_0 */ > + { > + { "vpdpbuud", { XM, Vex, EXx }, 0 }, > + { "vpdpbsud", { XM, Vex, EXx }, 0 }, > + { "%XVvpdpbusd", { XM, Vex, EXx }, 0 }, > + { "vpdpbssd", { XM, Vex, EXx }, 0 }, > + }, > + > + /* PREFIX_VEX_0F3851_W_0 */ > + { > + { "vpdpbuuds", { XM, Vex, EXx }, 0 }, > + { "vpdpbsuds", { XM, Vex, EXx }, 0 }, > + { "%XVvpdpbusds", { XM, Vex, EXx }, 0 }, > + { "vpdpbssds", { XM, Vex, EXx }, 0 }, > + }, > /* PREFIX_VEX_0F385C_X86_64 */ > { > { Bad_Opcode }, > @@ -7575,11 +7592,11 @@ static const struct dis386 vex_w_table[][2] = { > }, > { > /* VEX_W_0F3850 */ > - { "%XVvpdpbusd", { XM, Vex, EXx }, PREFIX_DATA }, > + { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, > }, > { > - /* VEX_W_0F3851 */ > - { "%XVvpdpbusds", { XM, Vex, EXx }, PREFIX_DATA }, > + /* VEX_W_0F3851_P_0 */ > + { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, > }, > { > /* VEX_W_0F3852 */ > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index dd759fbc7c..21986220d6 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -249,6 +249,8 @@ static initializer cpu_flag_init[] = > "CpuPREFETCHI"}, > { "CPU_AVX_IFMA_FLAGS", > "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, > + { "CPU_AVX_VNNI_INT8_FLAGS", > + "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -376,7 +378,7 @@ static initializer cpu_flag_init[] = > { "CPU_ANY_AVX_FLAGS", > "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, > { "CPU_ANY_AVX2_FLAGS", > - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" }, > + "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8" }, > { "CPU_ANY_AVX512F_FLAGS", > "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, > { "CPU_ANY_AVX512CD_FLAGS", > @@ -449,6 +451,8 @@ static initializer cpu_flag_init[] = > "CpuPREFETCHI" }, > { "CPU_ANY_AVX_IFMA_FLAGS", > "CpuAVX_IFMA" }, > + { "CPU_ANY_AVX_VNNI_INT8_FLAGS", > + "CpuAVX_VNNI_INT8" }, > }; > > static initializer operand_type_init[] = > @@ -652,6 +656,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuAVX512_FP16), > BITFIELD (CpuPREFETCHI), > BITFIELD (CpuAVX_IFMA), > + BITFIELD (CpuAVX_VNNI_INT8), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 7cd601e924..905908749b 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -213,6 +213,8 @@ enum > CpuPREFETCHI, > /* Intel AVX IFMA Instructions support required. */ > CpuAVX_IFMA, > + /* Intel AVX VNNI-INT8 Instructions support required. */ > + CpuAVX_VNNI_INT8, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -296,7 +298,7 @@ enum > > /* If you get a compiler error for zero width of the unused field, > comment it out. */ > -#define CpuUnused (CpuMax + 1) > +// #define CpuUnused (CpuMax + 1) > > /* We can check if an instruction is available with array instead > of bitfield. */ > @@ -396,6 +398,7 @@ typedef union i386_cpu_flags > unsigned int cpuavx512_fp16:1; > unsigned int cpuprefetchi:1; > unsigned int cpuavx_ifma:1; > + unsigned int cpuavx_vnni_int8:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 489a5335e2..77a5787c4b 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -2888,6 +2888,17 @@ vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckReg > > // AVX_VNNI instructions end > > +// AVX-VNNI-INT8 instructions. > + > +vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > +vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } > + > +// AVX-VNNI-INT8 instructions end. > + > // AVX512_BITALG instructions > > vpopcnt<bw>, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/6] Support Intel AVX-VNNI-INT8 2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang 2022-10-31 16:53 ` H.J. Lu @ 2022-11-02 10:45 ` Jan Beulich 1 sibling, 0 replies; 18+ messages in thread From: Jan Beulich @ 2022-11-02 10:45 UTC (permalink / raw) To: Haochen Jiang; +Cc: hjl.tools, Cui,Lili, binutils On 31.10.2022 04:05, Haochen Jiang wrote: > @@ -7575,11 +7592,11 @@ static const struct dis386 vex_w_table[][2] = { > }, > { > /* VEX_W_0F3850 */ > - { "%XVvpdpbusd", { XM, Vex, EXx }, PREFIX_DATA }, > + { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, > }, > { > - /* VEX_W_0F3851 */ > - { "%XVvpdpbusds", { XM, Vex, EXx }, PREFIX_DATA }, > + /* VEX_W_0F3851_P_0 */ > + { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, Note that the comment is now wrong - it shouldn't have been changed (just like the earlier one was left untouched). Jan ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/6] Support Intel CMPccXADD 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang 2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang 2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:54 ` H.J. Lu 2022-11-02 10:52 ` Jan Beulich 2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang ` (2 subsequent siblings) 5 siblings, 2 replies; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 3 +- gas/doc/c-i386.texi | 2 + gas/testsuite/gas/i386/cmpccxadd-inval.l | 5 + gas/testsuite/gas/i386/cmpccxadd-inval.s | 9 + gas/testsuite/gas/i386/i386.exp | 3 + .../gas/i386/x86-64-cmpccxadd-intel.d | 266 + gas/testsuite/gas/i386/x86-64-cmpccxadd.d | 266 + gas/testsuite/gas/i386/x86-64-cmpccxadd.s | 263 + opcodes/i386-dis.c | 147 +- opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 8280 +++++++++-------- 15 files changed, 5624 insertions(+), 4152 deletions(-) create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.l create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.d create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.s diff --git a/gas/NEWS b/gas/NEWS index 1547bfd469..7cdd429f0b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel CMPccXADD instructions. + * Add support for Intel AVX-VNNI-INT8 instructions. * Add support for Intel AVX-IFMA instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 26d8efb47e..9c0f86ac3d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] = SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), }; #undef SUBARCH @@ -8547,7 +8548,7 @@ build_modrm_byte (void) source operand is encoded in VEX prefix. */ gas_assert (mem != (unsigned int) ~0); - if (op > mem) + if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd) { vex_reg = op++; gas_assert (op < i.operands); diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 029f5f2e04..f98b9fbd9f 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -197,6 +197,7 @@ accept various extension mnemonics. For example, @code{prefetchi}, @code{avx_ifma}, @code{avx_vnni_int8}, +@code{cmpccxadd}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1491,6 +1492,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} +@item @samp{.cmpccxadd} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.l b/gas/testsuite/gas/i386/cmpccxadd-inval.l new file mode 100644 index 0000000000..32538867aa --- /dev/null +++ b/gas/testsuite/gas/i386/cmpccxadd-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:6: Error: `cmpbexadd' is only supported in 64-bit mode +.*:7: Error: `cmpbxadd' is only supported in 64-bit mode +.*:8: Error: `cmplexadd' is only supported in 64-bit mode +.*:9: Error: `cmplxadd' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.s b/gas/testsuite/gas/i386/cmpccxadd-inval.s new file mode 100644 index 0000000000..a349628863 --- /dev/null +++ b/gas/testsuite/gas/i386/cmpccxadd-inval.s @@ -0,0 +1,9 @@ +# Check Illegal CMPccXADD instructions + + .allow_index_reg + .text +_start: + cmpbexadd %eax, %eax, 0x10000000(%esp, %esi, 8) + cmpbxadd %ebx, %ebx, (%ecx) + cmplexadd %eax, %eax, 508(%ecx) + cmplxadd %ebx, %ebx, -512(%edx) diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index b75fe85cb3..e9785e64fd 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -479,6 +479,7 @@ if [gas_32_check] then { run_list_test "avx-ifma-inval" run_dump_test "avx-vnni-int8" run_dump_test "avx-vnni-int8-intel" + run_list_test "cmpccxadd-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1152,6 +1153,8 @@ if [gas_64_check] then { run_list_test "x86-64-avx-ifma-inval" run_dump_test "x86-64-avx-vnni-int8" run_dump_test "x86-64-avx-vnni-int8-intel" + run_dump_test "x86-64-cmpccxadd" + run_dump_test "x86-64-cmpccxadd-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d new file mode 100644 index 0000000000..0b906330b7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d @@ -0,0 +1,266 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 CMPCCXADD insns (Intel disassembly) +#source: x86-64-cmpccxadd.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d new file mode 100644 index 0000000000..b24af38d1c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d @@ -0,0 +1,266 @@ +#as: +#objdump: -dw +#name: x86_64 CMPCCXADD insns +#source: x86-64-cmpccxadd.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\) +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\) +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\) +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\) diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.s b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s new file mode 100644 index 0000000000..f2eb84a1a3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s @@ -0,0 +1,263 @@ +# Check 64bit CMPccXADD instructions + + .allow_index_reg + .text +_start: + cmpbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpbexadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpbexadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpbxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpbxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmplexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmplexadd %ebx, %ecx, (%r9) #CMPCCXADD + cmplexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmplexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmplexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmplexadd %rbx, %rcx, (%r9) #CMPCCXADD + cmplexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmplexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmplxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmplxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmplxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmplxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmplxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmplxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmplxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmplxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnbexadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnbexadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnbxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnbxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnlexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnlexadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnlexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnlexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnlexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnlexadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnlexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnlexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnlxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnlxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnlxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnlxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnlxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnlxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnlxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnlxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnoxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnoxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnpxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnpxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnpxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnpxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnpxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnpxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnpxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnpxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnsxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnsxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpnzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnzxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpnzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpnzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpnzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpnzxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpnzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpnzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpoxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpoxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmppxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmppxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmppxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmppxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmppxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmppxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmppxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmppxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpsxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpsxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + cmpzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpzxadd %ebx, %ecx, (%r9) #CMPCCXADD + cmpzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) + cmpzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) + cmpzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD + cmpzxadd %rbx, %rcx, (%r9) #CMPCCXADD + cmpzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) + cmpzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) + +.intel_syntax noprefix + cmpbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmplexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmplexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmplexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmplexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmplexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmplexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmplexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmplexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmplxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmplxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmplxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmplxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmplxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmplxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmplxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmplxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnlexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnlexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnlexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnlexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnlexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnlexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnlexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnlexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnlxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnlxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnlxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnlxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnlxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnlxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnlxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnlxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnpxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnpxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnpxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnpxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnpxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnpxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnpxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnpxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpnzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpnzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpnzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpnzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpnzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpnzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpnzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpnzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmppxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmppxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmppxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmppxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmppxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmppxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmppxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmppxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) + cmpzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD + cmpzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD + cmpzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) + cmpzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) + cmpzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD + cmpzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD + cmpzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) + cmpzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 436d2e7a08..116450c871 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -367,6 +367,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Ma { OP_M, a_mode } #define Mb { OP_M, b_mode } #define Md { OP_M, d_mode } +#define Mdq { OP_M, dq_mode } #define Mo { OP_M, o_mode } #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mq { OP_M, q_mode } @@ -1282,7 +1283,23 @@ enum X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, - X86_64_VEX_0F385E + X86_64_VEX_0F385E, + X86_64_VEX_0F38E0, + X86_64_VEX_0F38E1, + X86_64_VEX_0F38E2, + X86_64_VEX_0F38E3, + X86_64_VEX_0F38E4, + X86_64_VEX_0F38E5, + X86_64_VEX_0F38E6, + X86_64_VEX_0F38E7, + X86_64_VEX_0F38E8, + X86_64_VEX_0F38E9, + X86_64_VEX_0F38EA, + X86_64_VEX_0F38EB, + X86_64_VEX_0F38EC, + X86_64_VEX_0F38ED, + X86_64_VEX_0F38EE, + X86_64_VEX_0F38EF, }; enum @@ -4374,6 +4391,102 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, }, + + /* X86_64_VEX_0F38E0 */ + { + { Bad_Opcode }, + { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E1 */ + { + { Bad_Opcode }, + { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E2 */ + { + { Bad_Opcode }, + { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E3 */ + { + { Bad_Opcode }, + { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E4 */ + { + { Bad_Opcode }, + { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E5 */ + { + { Bad_Opcode }, + { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E6 */ + { + { Bad_Opcode }, + { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E7 */ + { + { Bad_Opcode }, + { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E8 */ + { + { Bad_Opcode }, + { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38E9 */ + { + { Bad_Opcode }, + { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EA */ + { + { Bad_Opcode }, + { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EB */ + { + { Bad_Opcode }, + { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EC */ + { + { Bad_Opcode }, + { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38ED */ + { + { Bad_Opcode }, + { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EE */ + { + { Bad_Opcode }, + { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + + /* X86_64_VEX_0F38EF */ + { + { Bad_Opcode }, + { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, }; static const struct dis386 three_byte_table[][256] = { @@ -6385,23 +6498,23 @@ static const struct dis386 vex_table[][256] = { { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, /* e0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_TABLE (X86_64_VEX_0F38E0) }, + { X86_64_TABLE (X86_64_VEX_0F38E1) }, + { X86_64_TABLE (X86_64_VEX_0F38E2) }, + { X86_64_TABLE (X86_64_VEX_0F38E3) }, + { X86_64_TABLE (X86_64_VEX_0F38E4) }, + { X86_64_TABLE (X86_64_VEX_0F38E5) }, + { X86_64_TABLE (X86_64_VEX_0F38E6) }, + { X86_64_TABLE (X86_64_VEX_0F38E7) }, /* e8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_TABLE (X86_64_VEX_0F38E8) }, + { X86_64_TABLE (X86_64_VEX_0F38E9) }, + { X86_64_TABLE (X86_64_VEX_0F38EA) }, + { X86_64_TABLE (X86_64_VEX_0F38EB) }, + { X86_64_TABLE (X86_64_VEX_0F38EC) }, + { X86_64_TABLE (X86_64_VEX_0F38ED) }, + { X86_64_TABLE (X86_64_VEX_0F38EE) }, + { X86_64_TABLE (X86_64_VEX_0F38EF) }, /* f0 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 21986220d6..55ed659d3d 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -251,6 +251,8 @@ static initializer cpu_flag_init[] = "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, { "CPU_AVX_VNNI_INT8_FLAGS", "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, + { "CPU_CMPCCXADD_FLAGS", + "CpuCMPCCXADD" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -453,6 +455,8 @@ static initializer cpu_flag_init[] = "CpuAVX_IFMA" }, { "CPU_ANY_AVX_VNNI_INT8_FLAGS", "CpuAVX_VNNI_INT8" }, + { "CPU_ANY_CMPCCXADD_FLAGS", + "CpuCMPCCXADD" }, }; static initializer operand_type_init[] = @@ -657,6 +661,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuPREFETCHI), BITFIELD (CpuAVX_IFMA), BITFIELD (CpuAVX_VNNI_INT8), + BITFIELD (CpuCMPCCXADD), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 905908749b..3b9572e2af 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -215,6 +215,8 @@ enum CpuAVX_IFMA, /* Intel AVX VNNI-INT8 Instructions support required. */ CpuAVX_VNNI_INT8, + /* Intel CMPccXADD instructions support required. */ + CpuCMPCCXADD, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -298,7 +300,7 @@ enum /* If you get a compiler error for zero width of the unused field, comment it out. */ -// #define CpuUnused (CpuMax + 1) +#define CpuUnused (CpuMax + 1) /* We can check if an instruction is available with array instead of bitfield. */ @@ -399,6 +401,7 @@ typedef union i386_cpu_flags unsigned int cpuprefetchi:1; unsigned int cpuavx_ifma:1; unsigned int cpuavx_vnni_int8:1; + unsigned int cpucmpccxadd:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 77a5787c4b..5fe9cb053f 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3289,3 +3289,9 @@ prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } // PREFETCHI instructions end. + +// CMPCCXADD instructions. + +cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } + +// CMPCCXADD instructions end. -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] Support Intel CMPccXADD 2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang @ 2022-10-31 16:54 ` H.J. Lu 2022-11-02 10:52 ` Jan Beulich 1 sibling, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:54 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > gas/ChangeLog: > > * NEWS: Support Intel CMPccXADD. > * config/tc-i386.c: Add cmpccxadd. > (build_modrm_byte): Add operations for Vex.VVVV reg > on operand 0 while have memory operand. > * doc/c-i386.texi: Document .cmpccxadd. > * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. > * testsuite/gas/i386/cmpccxadd-inval.s: New test. > * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. > * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. > * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. > * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (Mdq): New. > (X86_64_VEX_0F38E0): Ditto. > (X86_64_VEX_0F38E1): Ditto. > (X86_64_VEX_0F38E2): Ditto. > (X86_64_VEX_0F38E3): Ditto. > (X86_64_VEX_0F38E4): Ditto. > (X86_64_VEX_0F38E5): Ditto. > (X86_64_VEX_0F38E6): Ditto. > (X86_64_VEX_0F38E7): Ditto. > (X86_64_VEX_0F38E8): Ditto. > (X86_64_VEX_0F38E9): Ditto. > (X86_64_VEX_0F38EA): Ditto. > (X86_64_VEX_0F38EB): Ditto. > (X86_64_VEX_0F38EC): Ditto. > (X86_64_VEX_0F38ED): Ditto. > (X86_64_VEX_0F38EE): Ditto. > (X86_64_VEX_0F38EF): Ditto. > (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, > X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, > X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, > X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, > X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, > X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. > * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and > CPU_ANY_CMPCCXADD_FLAGS. > (cpu_flags): Add CpuCMPCCXADD. > * i386-init.h: Regenerated. > * i386-opc.h (CpuCMPCCXADD): New. > (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. > * i386-opc.tbl: Add Intel CMPccXADD instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 3 +- > gas/doc/c-i386.texi | 2 + > gas/testsuite/gas/i386/cmpccxadd-inval.l | 5 + > gas/testsuite/gas/i386/cmpccxadd-inval.s | 9 + > gas/testsuite/gas/i386/i386.exp | 3 + > .../gas/i386/x86-64-cmpccxadd-intel.d | 266 + > gas/testsuite/gas/i386/x86-64-cmpccxadd.d | 266 + > gas/testsuite/gas/i386/x86-64-cmpccxadd.s | 263 + > opcodes/i386-dis.c | 147 +- > opcodes/i386-gen.c | 5 + > opcodes/i386-init.h | 514 +- > opcodes/i386-opc.h | 5 +- > opcodes/i386-opc.tbl | 6 + > opcodes/i386-tbl.h | 8280 +++++++++-------- > 15 files changed, 5624 insertions(+), 4152 deletions(-) > create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.l > create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.s > create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.d > create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.s > > diff --git a/gas/NEWS b/gas/NEWS > index 1547bfd469..7cdd429f0b 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel CMPccXADD instructions. > + > * Add support for Intel AVX-VNNI-INT8 instructions. > > * Add support for Intel AVX-IFMA instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 26d8efb47e..9c0f86ac3d 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > }; > > #undef SUBARCH > @@ -8547,7 +8548,7 @@ build_modrm_byte (void) > source operand is encoded in VEX prefix. */ > gas_assert (mem != (unsigned int) ~0); > > - if (op > mem) > + if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd) > { > vex_reg = op++; > gas_assert (op < i.operands); > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 029f5f2e04..f98b9fbd9f 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -197,6 +197,7 @@ accept various extension mnemonics. For example, > @code{prefetchi}, > @code{avx_ifma}, > @code{avx_vnni_int8}, > +@code{cmpccxadd}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1491,6 +1492,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > +@item @samp{.cmpccxadd} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.l b/gas/testsuite/gas/i386/cmpccxadd-inval.l > new file mode 100644 > index 0000000000..32538867aa > --- /dev/null > +++ b/gas/testsuite/gas/i386/cmpccxadd-inval.l > @@ -0,0 +1,5 @@ > +.* Assembler messages: > +.*:6: Error: `cmpbexadd' is only supported in 64-bit mode > +.*:7: Error: `cmpbxadd' is only supported in 64-bit mode > +.*:8: Error: `cmplexadd' is only supported in 64-bit mode > +.*:9: Error: `cmplxadd' is only supported in 64-bit mode > diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.s b/gas/testsuite/gas/i386/cmpccxadd-inval.s > new file mode 100644 > index 0000000000..a349628863 > --- /dev/null > +++ b/gas/testsuite/gas/i386/cmpccxadd-inval.s > @@ -0,0 +1,9 @@ > +# Check Illegal CMPccXADD instructions > + > + .allow_index_reg > + .text > +_start: > + cmpbexadd %eax, %eax, 0x10000000(%esp, %esi, 8) > + cmpbxadd %ebx, %ebx, (%ecx) > + cmplexadd %eax, %eax, 508(%ecx) > + cmplxadd %ebx, %ebx, -512(%edx) > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index b75fe85cb3..e9785e64fd 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -479,6 +479,7 @@ if [gas_32_check] then { > run_list_test "avx-ifma-inval" > run_dump_test "avx-vnni-int8" > run_dump_test "avx-vnni-int8-intel" > + run_list_test "cmpccxadd-inval" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1152,6 +1153,8 @@ if [gas_64_check] then { > run_list_test "x86-64-avx-ifma-inval" > run_dump_test "x86-64-avx-vnni-int8" > run_dump_test "x86-64-avx-vnni-int8-intel" > + run_dump_test "x86-64-cmpccxadd" > + run_dump_test "x86-64-cmpccxadd-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d > new file mode 100644 > index 0000000000..0b906330b7 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d > @@ -0,0 +1,266 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 CMPCCXADD insns (Intel disassembly) > +#source: x86-64-cmpccxadd.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax > +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax > +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx > +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax > +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx > +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax > +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx > diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d > new file mode 100644 > index 0000000000..b24af38d1c > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d > @@ -0,0 +1,266 @@ > +#as: > +#objdump: -dw > +#name: x86_64 CMPCCXADD insns > +#source: x86-64-cmpccxadd.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\) > +\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\) > +\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\) > +\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\) > +\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\) > diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.s b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s > new file mode 100644 > index 0000000000..f2eb84a1a3 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s > @@ -0,0 +1,263 @@ > +# Check 64bit CMPccXADD instructions > + > + .allow_index_reg > + .text > +_start: > + cmpbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpbexadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpbexadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpbxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpbxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmplexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmplexadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmplexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmplexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmplexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmplexadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmplexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmplexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmplxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmplxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmplxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmplxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmplxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmplxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmplxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmplxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnbexadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnbexadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnbxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnbxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnlexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnlexadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnlexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnlexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnlexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnlexadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnlexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnlexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnlxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnlxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnlxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnlxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnlxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnlxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnlxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnlxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnoxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnoxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnpxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnpxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnpxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnpxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnpxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnpxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnpxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnpxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnsxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnsxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpnzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnzxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpnzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpnzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpnzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpnzxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpnzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpnzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpoxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpoxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmppxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmppxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmppxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmppxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmppxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmppxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmppxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmppxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpsxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpsxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + cmpzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpzxadd %ebx, %ecx, (%r9) #CMPCCXADD > + cmpzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000) > + cmpzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff) > + cmpzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD > + cmpzxadd %rbx, %rcx, (%r9) #CMPCCXADD > + cmpzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000) > + cmpzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff) > + > +.intel_syntax noprefix > + cmpbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmplexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmplexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmplexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmplexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmplexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmplexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmplexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmplexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmplxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmplxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmplxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmplxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmplxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmplxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmplxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmplxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnlexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnlexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnlexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnlexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnlexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnlexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnlexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnlexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnlxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnlxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnlxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnlxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnlxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnlxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnlxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnlxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnpxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnpxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnpxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnpxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnpxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnpxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnpxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnpxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpnzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpnzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpnzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpnzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpnzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpnzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpnzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpnzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmppxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmppxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmppxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmppxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmppxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmppxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmppxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmppxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > + cmpzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD > + cmpzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD > + cmpzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000) > + cmpzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff) > + cmpzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD > + cmpzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD > + cmpzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000) > + cmpzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff) > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index 436d2e7a08..116450c871 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -367,6 +367,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) > #define Ma { OP_M, a_mode } > #define Mb { OP_M, b_mode } > #define Md { OP_M, d_mode } > +#define Mdq { OP_M, dq_mode } > #define Mo { OP_M, o_mode } > #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ > #define Mq { OP_M, q_mode } > @@ -1282,7 +1283,23 @@ enum > X86_64_VEX_0F3849, > X86_64_VEX_0F384B, > X86_64_VEX_0F385C, > - X86_64_VEX_0F385E > + X86_64_VEX_0F385E, > + X86_64_VEX_0F38E0, > + X86_64_VEX_0F38E1, > + X86_64_VEX_0F38E2, > + X86_64_VEX_0F38E3, > + X86_64_VEX_0F38E4, > + X86_64_VEX_0F38E5, > + X86_64_VEX_0F38E6, > + X86_64_VEX_0F38E7, > + X86_64_VEX_0F38E8, > + X86_64_VEX_0F38E9, > + X86_64_VEX_0F38EA, > + X86_64_VEX_0F38EB, > + X86_64_VEX_0F38EC, > + X86_64_VEX_0F38ED, > + X86_64_VEX_0F38EE, > + X86_64_VEX_0F38EF, > }; > > enum > @@ -4374,6 +4391,102 @@ static const struct dis386 x86_64_table[][2] = { > { Bad_Opcode }, > { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, > }, > + > + /* X86_64_VEX_0F38E0 */ > + { > + { Bad_Opcode }, > + { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E1 */ > + { > + { Bad_Opcode }, > + { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E2 */ > + { > + { Bad_Opcode }, > + { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E3 */ > + { > + { Bad_Opcode }, > + { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E4 */ > + { > + { Bad_Opcode }, > + { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E5 */ > + { > + { Bad_Opcode }, > + { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E6 */ > + { > + { Bad_Opcode }, > + { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E7 */ > + { > + { Bad_Opcode }, > + { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E8 */ > + { > + { Bad_Opcode }, > + { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38E9 */ > + { > + { Bad_Opcode }, > + { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38EA */ > + { > + { Bad_Opcode }, > + { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38EB */ > + { > + { Bad_Opcode }, > + { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38EC */ > + { > + { Bad_Opcode }, > + { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38ED */ > + { > + { Bad_Opcode }, > + { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38EE */ > + { > + { Bad_Opcode }, > + { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > + > + /* X86_64_VEX_0F38EF */ > + { > + { Bad_Opcode }, > + { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, > + }, > }; > > static const struct dis386 three_byte_table[][256] = { > @@ -6385,23 +6498,23 @@ static const struct dis386 vex_table[][256] = { > { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, > { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, > /* e0 */ > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > + { X86_64_TABLE (X86_64_VEX_0F38E0) }, > + { X86_64_TABLE (X86_64_VEX_0F38E1) }, > + { X86_64_TABLE (X86_64_VEX_0F38E2) }, > + { X86_64_TABLE (X86_64_VEX_0F38E3) }, > + { X86_64_TABLE (X86_64_VEX_0F38E4) }, > + { X86_64_TABLE (X86_64_VEX_0F38E5) }, > + { X86_64_TABLE (X86_64_VEX_0F38E6) }, > + { X86_64_TABLE (X86_64_VEX_0F38E7) }, > /* e8 */ > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > - { Bad_Opcode }, > + { X86_64_TABLE (X86_64_VEX_0F38E8) }, > + { X86_64_TABLE (X86_64_VEX_0F38E9) }, > + { X86_64_TABLE (X86_64_VEX_0F38EA) }, > + { X86_64_TABLE (X86_64_VEX_0F38EB) }, > + { X86_64_TABLE (X86_64_VEX_0F38EC) }, > + { X86_64_TABLE (X86_64_VEX_0F38ED) }, > + { X86_64_TABLE (X86_64_VEX_0F38EE) }, > + { X86_64_TABLE (X86_64_VEX_0F38EF) }, > /* f0 */ > { Bad_Opcode }, > { Bad_Opcode }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 21986220d6..55ed659d3d 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -251,6 +251,8 @@ static initializer cpu_flag_init[] = > "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, > { "CPU_AVX_VNNI_INT8_FLAGS", > "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, > + { "CPU_CMPCCXADD_FLAGS", > + "CpuCMPCCXADD" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -453,6 +455,8 @@ static initializer cpu_flag_init[] = > "CpuAVX_IFMA" }, > { "CPU_ANY_AVX_VNNI_INT8_FLAGS", > "CpuAVX_VNNI_INT8" }, > + { "CPU_ANY_CMPCCXADD_FLAGS", > + "CpuCMPCCXADD" }, > }; > > static initializer operand_type_init[] = > @@ -657,6 +661,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuPREFETCHI), > BITFIELD (CpuAVX_IFMA), > BITFIELD (CpuAVX_VNNI_INT8), > + BITFIELD (CpuCMPCCXADD), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 905908749b..3b9572e2af 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -215,6 +215,8 @@ enum > CpuAVX_IFMA, > /* Intel AVX VNNI-INT8 Instructions support required. */ > CpuAVX_VNNI_INT8, > + /* Intel CMPccXADD instructions support required. */ > + CpuCMPCCXADD, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -298,7 +300,7 @@ enum > > /* If you get a compiler error for zero width of the unused field, > comment it out. */ > -// #define CpuUnused (CpuMax + 1) > +#define CpuUnused (CpuMax + 1) > > /* We can check if an instruction is available with array instead > of bitfield. */ > @@ -399,6 +401,7 @@ typedef union i386_cpu_flags > unsigned int cpuprefetchi:1; > unsigned int cpuavx_ifma:1; > unsigned int cpuavx_vnni_int8:1; > + unsigned int cpucmpccxadd:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 77a5787c4b..5fe9cb053f 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3289,3 +3289,9 @@ prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No > prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex } > > // PREFETCHI instructions end. > + > +// CMPCCXADD instructions. > + > +cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } > + > +// CMPCCXADD instructions end. > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] Support Intel CMPccXADD 2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang 2022-10-31 16:54 ` H.J. Lu @ 2022-11-02 10:52 ` Jan Beulich 2022-11-02 16:25 ` H.J. Lu 1 sibling, 1 reply; 18+ messages in thread From: Jan Beulich @ 2022-11-02 10:52 UTC (permalink / raw) To: Haochen Jiang; +Cc: hjl.tools, binutils On 31.10.2022 04:05, Haochen Jiang wrote: > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), ANY_CMPCCXADD shouldn't have been re-introduced here. It now being there only means more code churn in my patch to sanitize all of this dependencies handling. (Unless, as I'll mention there as an option, we want to uniformly use ANY_... in [almost] all table entries). > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -215,6 +215,8 @@ enum > CpuAVX_IFMA, > /* Intel AVX VNNI-INT8 Instructions support required. */ > CpuAVX_VNNI_INT8, > + /* Intel CMPccXADD instructions support required. */ > + CpuCMPCCXADD, Just as a remark: Personally I would have considered it more readable overall if this had the "CC" infix in lower case (like in the comment). Jan ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] Support Intel CMPccXADD 2022-11-02 10:52 ` Jan Beulich @ 2022-11-02 16:25 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-11-02 16:25 UTC (permalink / raw) To: Jan Beulich; +Cc: Haochen Jiang, binutils On Wed, Nov 2, 2022 at 3:52 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 31.10.2022 04:05, Haochen Jiang wrote: > > --- a/gas/config/tc-i386.c > > +++ b/gas/config/tc-i386.c > > @@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] = > > SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false), > > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > > ANY_CMPCCXADD shouldn't have been re-introduced here. It now being > there only means more code churn in my patch to sanitize all of this > dependencies handling. (Unless, as I'll mention there as an option, > we want to uniformly use ANY_... in [almost] all table entries). We discussed it. ANY_ doesn't hurt and it can be useful when there is a dependency in the future. > > --- a/opcodes/i386-opc.h > > +++ b/opcodes/i386-opc.h > > @@ -215,6 +215,8 @@ enum > > CpuAVX_IFMA, > > /* Intel AVX VNNI-INT8 Instructions support required. */ > > CpuAVX_VNNI_INT8, > > + /* Intel CMPccXADD instructions support required. */ > > + CpuCMPCCXADD, > > Just as a remark: Personally I would have considered it more readable > overall if this had the "CC" infix in lower case (like in the comment). > > Jan -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/6] Add handler for more i386_cpu_flags 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang ` (2 preceding siblings ...) 2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:54 ` H.J. Lu 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang 2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang 5 siblings, 1 reply; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools, Kong Lingling From: Kong Lingling <lingling.kong@intel.com> gas/ChangeLog: * config/tc-i386.c (cpu_flags_all_zero): Add new ARRAY_SIZE handle. (cpu_flags_equal): Ditto. (cpu_flags_and): Ditto. (cpu_flags_or): Ditto. (cpu_flags_and_not): Ditto. --- gas/config/tc-i386.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 9c0f86ac3d..99d1a4cfec 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1619,6 +1619,10 @@ cpu_flags_all_zero (const union i386_cpu_flags *x) { switch (ARRAY_SIZE(x->array)) { + case 5: + if (x->array[4]) + return 0; + /* Fall through. */ case 4: if (x->array[3]) return 0; @@ -1644,6 +1648,10 @@ cpu_flags_equal (const union i386_cpu_flags *x, { switch (ARRAY_SIZE(x->array)) { + case 5: + if (x->array[4] != y->array[4]) + return 0; + /* Fall through. */ case 4: if (x->array[3] != y->array[3]) return 0; @@ -1676,6 +1684,9 @@ cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 5: + x.array [4] &= y.array [4]; + /* Fall through. */ case 4: x.array [3] &= y.array [3]; /* Fall through. */ @@ -1699,6 +1710,9 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 5: + x.array [4] |= y.array [4]; + /* Fall through. */ case 4: x.array [3] |= y.array [3]; /* Fall through. */ @@ -1722,6 +1736,9 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 5: + x.array [4] &= ~y.array [4]; + /* Fall through. */ case 4: x.array [3] &= ~y.array [3]; /* Fall through. */ -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/6] Add handler for more i386_cpu_flags 2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang @ 2022-10-31 16:54 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:54 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich, Kong Lingling On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > From: Kong Lingling <lingling.kong@intel.com> > > gas/ChangeLog: > > * config/tc-i386.c (cpu_flags_all_zero): Add new ARRAY_SIZE handle. > (cpu_flags_equal): Ditto. > (cpu_flags_and): Ditto. > (cpu_flags_or): Ditto. > (cpu_flags_and_not): Ditto. > --- > gas/config/tc-i386.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 9c0f86ac3d..99d1a4cfec 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1619,6 +1619,10 @@ cpu_flags_all_zero (const union i386_cpu_flags *x) > { > switch (ARRAY_SIZE(x->array)) > { > + case 5: > + if (x->array[4]) > + return 0; > + /* Fall through. */ > case 4: > if (x->array[3]) > return 0; > @@ -1644,6 +1648,10 @@ cpu_flags_equal (const union i386_cpu_flags *x, > { > switch (ARRAY_SIZE(x->array)) > { > + case 5: > + if (x->array[4] != y->array[4]) > + return 0; > + /* Fall through. */ > case 4: > if (x->array[3] != y->array[3]) > return 0; > @@ -1676,6 +1684,9 @@ cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) > { > switch (ARRAY_SIZE (x.array)) > { > + case 5: > + x.array [4] &= y.array [4]; > + /* Fall through. */ > case 4: > x.array [3] &= y.array [3]; > /* Fall through. */ > @@ -1699,6 +1710,9 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) > { > switch (ARRAY_SIZE (x.array)) > { > + case 5: > + x.array [4] |= y.array [4]; > + /* Fall through. */ > case 4: > x.array [3] |= y.array [3]; > /* Fall through. */ > @@ -1722,6 +1736,9 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) > { > switch (ARRAY_SIZE (x.array)) > { > + case 5: > + x.array [4] &= ~y.array [4]; > + /* Fall through. */ > case 4: > x.array [3] &= ~y.array [3]; > /* Fall through. */ > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/6] Support Intel WRMSRNS 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang ` (3 preceding siblings ...) 2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:56 ` H.J. Lu ` (2 more replies) 2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang 5 siblings, 3 replies; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools, Hu, Lin1 From: "Hu, Lin1" <lin1.hu@intel.com> gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/wrmsrns-intel.d | 5 + gas/testsuite/gas/i386/wrmsrns.d | 12 + gas/testsuite/gas/i386/wrmsrns.s | 8 + gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 5 + gas/testsuite/gas/i386/x86-64-wrmsrns.d | 5 + opcodes/i386-dis.c | 7 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 7839 +++++++++-------- 15 files changed, 4257 insertions(+), 4162 deletions(-) create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.s create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d diff --git a/gas/NEWS b/gas/NEWS index 7cdd429f0b..c448ec7861 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel WRMSRNS instructions. + * Add support for Intel CMPccXADD instructions. * Add support for Intel AVX-VNNI-INT8 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 99d1a4cfec..d387f93ea0 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f98b9fbd9f..47aa02b334 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -198,6 +198,7 @@ accept various extension mnemonics. For example, @code{avx_ifma}, @code{avx_vnni_int8}, @code{cmpccxadd}, +@code{wrmsrns}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} -@item @samp{.cmpccxadd} +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index e9785e64fd..d3797937a7 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -480,6 +480,8 @@ if [gas_32_check] then { run_dump_test "avx-vnni-int8" run_dump_test "avx-vnni-int8-intel" run_list_test "cmpccxadd-inval" + run_dump_test "wrmsrns" + run_dump_test "wrmsrns-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1155,6 +1157,8 @@ if [gas_64_check] then { run_dump_test "x86-64-avx-vnni-int8-intel" run_dump_test "x86-64-cmpccxadd" run_dump_test "x86-64-cmpccxadd-intel" + run_dump_test "x86-64-wrmsrns" + run_dump_test "x86-64-wrmsrns-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d new file mode 100644 index 0000000000..b3be2609d8 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns-intel.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw -Mintel +#name: i386 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d new file mode 100644 index 0000000000..e804adc501 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw +#name: i386 WRMSRNS insns +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s new file mode 100644 index 0000000000..a450b0536d --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.s @@ -0,0 +1,8 @@ +# Check WRMSRNS instructions + + .text +_start: + wrmsrns #WRMSRNS + +.intel_syntax noprefix + wrmsrns #WRMSRNS diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d new file mode 100644 index 0000000000..ff80e55b7c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d new file mode 100644 index 0000000000..047f0a1a7d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw +#name: x86_64 WRMSRNS insns +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 116450c871..fb1c14b5b5 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -985,6 +985,7 @@ enum enum { PREFIX_90 = 0, + PREFIX_0F01_REG_0_MOD_3_RM_6, PREFIX_0F01_REG_1_RM_4, PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, @@ -2954,6 +2955,11 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ + { + { "wrmsrns", { Skip_MODRM }, 0 }, + }, + /* PREFIX_0F01_REG_1_RM_4 */ { { Bad_Opcode }, @@ -8634,6 +8640,7 @@ static const struct dis386 rm_table[][8] = { { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, { "pconfig", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, }, { /* RM_0F01_REG_1 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 55ed659d3d..a6dc8b904e 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, { "CPU_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -457,6 +459,8 @@ static initializer cpu_flag_init[] = "CpuAVX_VNNI_INT8" }, { "CPU_ANY_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_ANY_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, }; static initializer operand_type_init[] = @@ -662,6 +666,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_IFMA), BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuCMPCCXADD), + BITFIELD (CpuWRMSRNS), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 3b9572e2af..f00babfce2 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -217,6 +217,8 @@ enum CpuAVX_VNNI_INT8, /* Intel CMPccXADD instructions support required. */ CpuCMPCCXADD, + /* Intel WRMSRNS Instructions support required */ + CpuWRMSRNS, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -402,6 +404,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_ifma:1; unsigned int cpuavx_vnni_int8:1; unsigned int cpucmpccxadd:1; + unsigned int cpuwrmsrns:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5fe9cb053f..3e947cd248 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3295,3 +3295,9 @@ prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. + +// WRMSRNS instruction. + +wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// WRMSRNS instruction end. -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/6] Support Intel WRMSRNS 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang @ 2022-10-31 16:56 ` H.J. Lu 2022-11-02 10:56 ` Jan Beulich 2022-11-02 14:35 ` Jan Beulich 2 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:56 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich, Hu, Lin1 On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > From: "Hu, Lin1" <lin1.hu@intel.com> > > gas/ChangeLog: > > * NEWS: Support Intel WRMSRNS. > * config/tc-i386.c: Add wrmsrns. > * doc/c-i386.texi: Document .wrmsrns. > * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. > * testsuite/gas/i386/wrmsrns-intel.d: New test. > * testsuite/gas/i386/wrmsrns.d: Ditto. > * testsuite/gas/i386/wrmsrns.s: Ditto. > * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. > * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. > (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. > (rm_table): New entry for wrmsrns. > * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS > and CPU_ANY_WRMSRNS_FLAGS. > (cpu_flags): Add CpuWRMSRNS. > * i386-init.h: Regenerated. > * i386-opc.h (CpuWRMSRNS): New. > (i386_cpu_flags): Add cpuwrmsrns. > * i386-opc.tbl: Add WRMSRNS instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/i386.exp | 4 + > gas/testsuite/gas/i386/wrmsrns-intel.d | 5 + > gas/testsuite/gas/i386/wrmsrns.d | 12 + > gas/testsuite/gas/i386/wrmsrns.s | 8 + > gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 5 + > gas/testsuite/gas/i386/x86-64-wrmsrns.d | 5 + > opcodes/i386-dis.c | 7 + > opcodes/i386-gen.c | 5 + > opcodes/i386-init.h | 514 +- > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 6 + > opcodes/i386-tbl.h | 7839 +++++++++-------- > 15 files changed, 4257 insertions(+), 4162 deletions(-) > create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d > create mode 100644 gas/testsuite/gas/i386/wrmsrns.d > create mode 100644 gas/testsuite/gas/i386/wrmsrns.s > create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d > > diff --git a/gas/NEWS b/gas/NEWS > index 7cdd429f0b..c448ec7861 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel WRMSRNS instructions. > + > * Add support for Intel CMPccXADD instructions. > > * Add support for Intel AVX-VNNI-INT8 instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index 99d1a4cfec..d387f93ea0 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index f98b9fbd9f..47aa02b334 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -198,6 +198,7 @@ accept various extension mnemonics. For example, > @code{avx_ifma}, > @code{avx_vnni_int8}, > @code{cmpccxadd}, > +@code{wrmsrns}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > -@item @samp{.cmpccxadd} > +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index e9785e64fd..d3797937a7 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -480,6 +480,8 @@ if [gas_32_check] then { > run_dump_test "avx-vnni-int8" > run_dump_test "avx-vnni-int8-intel" > run_list_test "cmpccxadd-inval" > + run_dump_test "wrmsrns" > + run_dump_test "wrmsrns-intel" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1155,6 +1157,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-avx-vnni-int8-intel" > run_dump_test "x86-64-cmpccxadd" > run_dump_test "x86-64-cmpccxadd-intel" > + run_dump_test "x86-64-wrmsrns" > + run_dump_test "x86-64-wrmsrns-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d > new file mode 100644 > index 0000000000..b3be2609d8 > --- /dev/null > +++ b/gas/testsuite/gas/i386/wrmsrns-intel.d > @@ -0,0 +1,5 @@ > +#as: > +#objdump: -dw -Mintel > +#name: i386 WRMSRNS insns (Intel disassembly) > +#source: wrmsrns.s > +#dump: wrmsrns.d > diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d > new file mode 100644 > index 0000000000..e804adc501 > --- /dev/null > +++ b/gas/testsuite/gas/i386/wrmsrns.d > @@ -0,0 +1,12 @@ > +#as: > +#objdump: -dw > +#name: i386 WRMSRNS insns > +#source: wrmsrns.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns > +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns > diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s > new file mode 100644 > index 0000000000..a450b0536d > --- /dev/null > +++ b/gas/testsuite/gas/i386/wrmsrns.s > @@ -0,0 +1,8 @@ > +# Check WRMSRNS instructions > + > + .text > +_start: > + wrmsrns #WRMSRNS > + > +.intel_syntax noprefix > + wrmsrns #WRMSRNS > diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d > new file mode 100644 > index 0000000000..ff80e55b7c > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d > @@ -0,0 +1,5 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 WRMSRNS insns (Intel disassembly) > +#source: wrmsrns.s > +#dump: wrmsrns.d > diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d > new file mode 100644 > index 0000000000..047f0a1a7d > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d > @@ -0,0 +1,5 @@ > +#as: > +#objdump: -dw > +#name: x86_64 WRMSRNS insns > +#source: wrmsrns.s > +#dump: wrmsrns.d > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index 116450c871..fb1c14b5b5 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -985,6 +985,7 @@ enum > enum > { > PREFIX_90 = 0, > + PREFIX_0F01_REG_0_MOD_3_RM_6, > PREFIX_0F01_REG_1_RM_4, > PREFIX_0F01_REG_1_RM_5, > PREFIX_0F01_REG_1_RM_6, > @@ -2954,6 +2955,11 @@ static const struct dis386 prefix_table[][4] = { > { NULL, { { NULL, 0 } }, PREFIX_IGNORED } > }, > > + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ > + { > + { "wrmsrns", { Skip_MODRM }, 0 }, > + }, > + > /* PREFIX_0F01_REG_1_RM_4 */ > { > { Bad_Opcode }, > @@ -8634,6 +8640,7 @@ static const struct dis386 rm_table[][8] = { > { "vmresume", { Skip_MODRM }, 0 }, > { "vmxoff", { Skip_MODRM }, 0 }, > { "pconfig", { Skip_MODRM }, 0 }, > + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, > }, > { > /* RM_0F01_REG_1 */ > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index 55ed659d3d..a6dc8b904e 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = > "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, > { "CPU_CMPCCXADD_FLAGS", > "CpuCMPCCXADD" }, > + { "CPU_WRMSRNS_FLAGS", > + "CpuWRMSRNS" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -457,6 +459,8 @@ static initializer cpu_flag_init[] = > "CpuAVX_VNNI_INT8" }, > { "CPU_ANY_CMPCCXADD_FLAGS", > "CpuCMPCCXADD" }, > + { "CPU_ANY_WRMSRNS_FLAGS", > + "CpuWRMSRNS" }, > }; > > static initializer operand_type_init[] = > @@ -662,6 +666,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuAVX_IFMA), > BITFIELD (CpuAVX_VNNI_INT8), > BITFIELD (CpuCMPCCXADD), > + BITFIELD (CpuWRMSRNS), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index 3b9572e2af..f00babfce2 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -217,6 +217,8 @@ enum > CpuAVX_VNNI_INT8, > /* Intel CMPccXADD instructions support required. */ > CpuCMPCCXADD, > + /* Intel WRMSRNS Instructions support required */ > + CpuWRMSRNS, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -402,6 +404,7 @@ typedef union i386_cpu_flags > unsigned int cpuavx_ifma:1; > unsigned int cpuavx_vnni_int8:1; > unsigned int cpucmpccxadd:1; > + unsigned int cpuwrmsrns:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 5fe9cb053f..3e947cd248 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3295,3 +3295,9 @@ prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No > cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } > > // CMPCCXADD instructions end. > + > +// WRMSRNS instruction. > + > +wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > + > +// WRMSRNS instruction end. > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/6] Support Intel WRMSRNS 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang 2022-10-31 16:56 ` H.J. Lu @ 2022-11-02 10:56 ` Jan Beulich 2022-11-02 14:35 ` Jan Beulich 2 siblings, 0 replies; 18+ messages in thread From: Jan Beulich @ 2022-11-02 10:56 UTC (permalink / raw) To: Haochen Jiang; +Cc: hjl.tools, Hu, Lin1, binutils On 31.10.2022 04:05, Haochen Jiang wrote: > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), > }; Like for CMPccXADD I don't see why ANY_WRMSRNS was re-introduced here. I guess I'll find the same in patch 6 then yet again. Jan ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/6] Support Intel WRMSRNS 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang 2022-10-31 16:56 ` H.J. Lu 2022-11-02 10:56 ` Jan Beulich @ 2022-11-02 14:35 ` Jan Beulich 2 siblings, 0 replies; 18+ messages in thread From: Jan Beulich @ 2022-11-02 14:35 UTC (permalink / raw) To: Haochen Jiang; +Cc: hjl.tools, Hu, Lin1, binutils On 31.10.2022 04:05, Haochen Jiang wrote: > opcodes/ChangeLog: > > * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. > (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. > (rm_table): New entry for wrmsrns. > * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS > and CPU_ANY_WRMSRNS_FLAGS. > (cpu_flags): Add CpuWRMSRNS. > * i386-init.h: Regenerated. > * i386-opc.h (CpuWRMSRNS): New. > (i386_cpu_flags): Add cpuwrmsrns. Additionally this should have commented out CpuUnused again. Jan ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/6] Support Intel MSRLIST 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang ` (4 preceding siblings ...) 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang @ 2022-10-31 3:05 ` Haochen Jiang 2022-10-31 16:55 ` H.J. Lu 5 siblings, 1 reply; 18+ messages in thread From: Haochen Jiang @ 2022-10-31 3:05 UTC (permalink / raw) To: binutils; +Cc: jbeulich, hjl.tools, Hu, Lin1 From: "Hu, Lin1" <lin1.hu@intel.com> gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/msrlist-inval.l | 3 + gas/testsuite/gas/i386/msrlist-inval.s | 7 + gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 5 + gas/testsuite/gas/i386/x86-64-msrlist.d | 14 + gas/testsuite/gas/i386/x86-64-msrlist.s | 10 + opcodes/i386-dis.c | 17 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 516 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7852 +++++++++-------- 15 files changed, 4285 insertions(+), 4163 deletions(-) create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s diff --git a/gas/NEWS b/gas/NEWS index c448ec7861..c9df5608ec 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel MSRLIST instructions. + * Add support for Intel WRMSRNS instructions. * Add support for Intel CMPccXADD instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index d387f93ea0..e1de7d9c76 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), + SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 47aa02b334..1774979a83 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -199,6 +199,7 @@ accept various extension mnemonics. For example, @code{avx_vnni_int8}, @code{cmpccxadd}, @code{wrmsrns}, +@code{msrlist}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1493,7 +1494,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} -@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index d3797937a7..9eaadd131d 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -482,6 +482,7 @@ if [gas_32_check] then { run_list_test "cmpccxadd-inval" run_dump_test "wrmsrns" run_dump_test "wrmsrns-intel" + run_list_test "msrlist-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1159,6 +1160,8 @@ if [gas_64_check] then { run_dump_test "x86-64-cmpccxadd-intel" run_dump_test "x86-64-wrmsrns" run_dump_test "x86-64-wrmsrns-intel" + run_dump_test "x86-64-msrlist" + run_dump_test "x86-64-msrlist-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l new file mode 100644 index 0000000000..456f41c38f --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `rdmsrlist' is only supported in 64-bit mode +.*:7: Error: `wrmsrlist' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s new file mode 100644 index 0000000000..3c3258a375 --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.s @@ -0,0 +1,7 @@ +# Check Illegal MSRLIST instructions + + .allow_index_reg + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d new file mode 100644 index 0000000000..b37adb573f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 MSRLIST insns (Intel disassembly) +#source: x86-64-msrlist.s +#dump: x86-64-msrlist.d diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d new file mode 100644 index 0000000000..64beed7aa3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw +#name: x86_64 MSRLIST insns +#source: x86-64-msrlist.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s new file mode 100644 index 0000000000..45fb45256a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.s @@ -0,0 +1,10 @@ +# Check 64bit MSRLIST instructions + + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST + +.intel_syntax noprefix + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index fb1c14b5b5..ab43d0cd8e 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1262,6 +1262,8 @@ enum X86_64_E9, X86_64_EA, X86_64_0F01_REG_0, + X86_64_0F01_REG_0_MOD_3_RM_6_P_1, + X86_64_0F01_REG_0_MOD_3_RM_6_P_3, X86_64_0F01_REG_1, X86_64_0F01_REG_1_RM_5_PREFIX_2, X86_64_0F01_REG_1_RM_6_PREFIX_2, @@ -2958,6 +2960,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ { { "wrmsrns", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, }, /* PREFIX_0F01_REG_1_RM_4 */ @@ -4268,6 +4273,18 @@ static const struct dis386 x86_64_table[][2] = { { "sgdt", { M }, 0 }, }, + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ + { + { Bad_Opcode }, + { "wrmsrlist", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ + { + { Bad_Opcode }, + { "rdmsrlist", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_1 */ { { "sidt{Q|Q}", { M }, 0 }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index a6dc8b904e..b820104234 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -255,6 +255,8 @@ static initializer cpu_flag_init[] = "CpuCMPCCXADD" }, { "CPU_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_MSRLIST_FLAGS", + "CpuMSRLIST" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -461,6 +463,8 @@ static initializer cpu_flag_init[] = "CpuCMPCCXADD" }, { "CPU_ANY_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_ANY_MSRLIST_FLAGS", + "CpuMSRLIST" }, }; static initializer operand_type_init[] = @@ -667,6 +671,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuCMPCCXADD), BITFIELD (CpuWRMSRNS), + BITFIELD (CpuMSRLIST), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index f00babfce2..a409b10ca1 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -219,6 +219,8 @@ enum CpuCMPCCXADD, /* Intel WRMSRNS Instructions support required */ CpuWRMSRNS, + /* Intel MSRLIST Instructions support required. */ + CpuMSRLIST, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -405,6 +407,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_vnni_int8:1; unsigned int cpucmpccxadd:1; unsigned int cpuwrmsrns:1; + unsigned int cpumsrlist:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 3e947cd248..f1d17171c3 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3301,3 +3301,10 @@ cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVV wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // WRMSRNS instruction end. + +// MSRLIST instructions. + +rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} +wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// MSRLIST instructions end. -- 2.18.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 6/6] Support Intel MSRLIST 2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang @ 2022-10-31 16:55 ` H.J. Lu 0 siblings, 0 replies; 18+ messages in thread From: H.J. Lu @ 2022-10-31 16:55 UTC (permalink / raw) To: Haochen Jiang; +Cc: binutils, jbeulich, Hu, Lin1 On Sun, Oct 30, 2022 at 8:07 PM Haochen Jiang <haochen.jiang@intel.com> wrote: > > From: "Hu, Lin1" <lin1.hu@intel.com> > > gas/ChangeLog: > > * NEWS: Support Intel MSRLIST. > * config/tc-i386.c: Add msrlist. > * doc/c-i386.texi: Document .msrlist. > * testsuite/gas/i386/i386.exp: Add MSRLIST tests. > * testsuite/gas/i386/msrlist-inval.l: New test. > * testsuite/gas/i386/msrlist-inval.s: Ditto. > * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. > * testsuite/gas/i386/x86-64-msrlist.d: Ditto. > * testsuite/gas/i386/x86-64-msrlist.s: Ditto. > > opcodes/ChangeLog: > > * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. > (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. > (prefix_table): New entry for msrlist. > (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 > and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. > * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS > and CPU_ANY_MSRLIST_FLAGS. > * i386-init.h: Regenerated. > * i386-opc.h (CpuMSRLIST): New. > (i386_cpu_flags): Add cpumsrlist. > * i386-opc.tbl: Add MSRLIST instructions. > * i386-tbl.h: Regenerated. > --- > gas/NEWS | 2 + > gas/config/tc-i386.c | 1 + > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/i386.exp | 3 + > gas/testsuite/gas/i386/msrlist-inval.l | 3 + > gas/testsuite/gas/i386/msrlist-inval.s | 7 + > gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 5 + > gas/testsuite/gas/i386/x86-64-msrlist.d | 14 + > gas/testsuite/gas/i386/x86-64-msrlist.s | 10 + > opcodes/i386-dis.c | 17 + > opcodes/i386-gen.c | 5 + > opcodes/i386-init.h | 516 +- > opcodes/i386-opc.h | 3 + > opcodes/i386-opc.tbl | 7 + > opcodes/i386-tbl.h | 7852 +++++++++-------- > 15 files changed, 4285 insertions(+), 4163 deletions(-) > create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l > create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d > create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s > > diff --git a/gas/NEWS b/gas/NEWS > index c448ec7861..c9df5608ec 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for Intel MSRLIST instructions. > + > * Add support for Intel WRMSRNS instructions. > > * Add support for Intel CMPccXADD instructions. > diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c > index d387f93ea0..e1de7d9c76 100644 > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] = > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), > SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), > SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), > + SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), > }; > > #undef SUBARCH > diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi > index 47aa02b334..1774979a83 100644 > --- a/gas/doc/c-i386.texi > +++ b/gas/doc/c-i386.texi > @@ -199,6 +199,7 @@ accept various extension mnemonics. For example, > @code{avx_vnni_int8}, > @code{cmpccxadd}, > @code{wrmsrns}, > +@code{msrlist}, > @code{amx_int8}, > @code{amx_bf16}, > @code{amx_fp16}, > @@ -1493,7 +1494,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: > @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} > @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} > @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} > -@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} > +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} > @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} > @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} > @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} > diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp > index d3797937a7..9eaadd131d 100644 > --- a/gas/testsuite/gas/i386/i386.exp > +++ b/gas/testsuite/gas/i386/i386.exp > @@ -482,6 +482,7 @@ if [gas_32_check] then { > run_list_test "cmpccxadd-inval" > run_dump_test "wrmsrns" > run_dump_test "wrmsrns-intel" > + run_list_test "msrlist-inval" > run_list_test "sg" > run_dump_test "clzero" > run_dump_test "invlpgb" > @@ -1159,6 +1160,8 @@ if [gas_64_check] then { > run_dump_test "x86-64-cmpccxadd-intel" > run_dump_test "x86-64-wrmsrns" > run_dump_test "x86-64-wrmsrns-intel" > + run_dump_test "x86-64-msrlist" > + run_dump_test "x86-64-msrlist-intel" > run_dump_test "x86-64-clzero" > run_dump_test "x86-64-mwaitx-bdver4" > run_list_test "x86-64-mwaitx-reg" > diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l > new file mode 100644 > index 0000000000..456f41c38f > --- /dev/null > +++ b/gas/testsuite/gas/i386/msrlist-inval.l > @@ -0,0 +1,3 @@ > +.* Assembler messages: > +.*:6: Error: `rdmsrlist' is only supported in 64-bit mode > +.*:7: Error: `wrmsrlist' is only supported in 64-bit mode > diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s > new file mode 100644 > index 0000000000..3c3258a375 > --- /dev/null > +++ b/gas/testsuite/gas/i386/msrlist-inval.s > @@ -0,0 +1,7 @@ > +# Check Illegal MSRLIST instructions > + > + .allow_index_reg > + .text > +_start: > + rdmsrlist #MSRLIST > + wrmsrlist #MSRLIST > diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d > new file mode 100644 > index 0000000000..b37adb573f > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d > @@ -0,0 +1,5 @@ > +#as: > +#objdump: -dw -Mintel > +#name: x86_64 MSRLIST insns (Intel disassembly) > +#source: x86-64-msrlist.s > +#dump: x86-64-msrlist.d > diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d > new file mode 100644 > index 0000000000..64beed7aa3 > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-msrlist.d > @@ -0,0 +1,14 @@ > +#as: > +#objdump: -dw > +#name: x86_64 MSRLIST insns > +#source: x86-64-msrlist.s > + > +.*: +file format .* > + > +Disassembly of section \.text: > + > +0+ <_start>: > +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist > +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist > +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist > +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist > diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s > new file mode 100644 > index 0000000000..45fb45256a > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-msrlist.s > @@ -0,0 +1,10 @@ > +# Check 64bit MSRLIST instructions > + > + .text > +_start: > + rdmsrlist #MSRLIST > + wrmsrlist #MSRLIST > + > +.intel_syntax noprefix > + rdmsrlist #MSRLIST > + wrmsrlist #MSRLIST > diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c > index fb1c14b5b5..ab43d0cd8e 100644 > --- a/opcodes/i386-dis.c > +++ b/opcodes/i386-dis.c > @@ -1262,6 +1262,8 @@ enum > X86_64_E9, > X86_64_EA, > X86_64_0F01_REG_0, > + X86_64_0F01_REG_0_MOD_3_RM_6_P_1, > + X86_64_0F01_REG_0_MOD_3_RM_6_P_3, > X86_64_0F01_REG_1, > X86_64_0F01_REG_1_RM_5_PREFIX_2, > X86_64_0F01_REG_1_RM_6_PREFIX_2, > @@ -2958,6 +2960,9 @@ static const struct dis386 prefix_table[][4] = { > /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ > { > { "wrmsrns", { Skip_MODRM }, 0 }, > + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, > + { Bad_Opcode }, > + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, > }, > > /* PREFIX_0F01_REG_1_RM_4 */ > @@ -4268,6 +4273,18 @@ static const struct dis386 x86_64_table[][2] = { > { "sgdt", { M }, 0 }, > }, > > + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ > + { > + { Bad_Opcode }, > + { "wrmsrlist", { Skip_MODRM }, 0 }, > + }, > + > + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ > + { > + { Bad_Opcode }, > + { "rdmsrlist", { Skip_MODRM }, 0 }, > + }, > + > /* X86_64_0F01_REG_1 */ > { > { "sidt{Q|Q}", { M }, 0 }, > diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c > index a6dc8b904e..b820104234 100644 > --- a/opcodes/i386-gen.c > +++ b/opcodes/i386-gen.c > @@ -255,6 +255,8 @@ static initializer cpu_flag_init[] = > "CpuCMPCCXADD" }, > { "CPU_WRMSRNS_FLAGS", > "CpuWRMSRNS" }, > + { "CPU_MSRLIST_FLAGS", > + "CpuMSRLIST" }, > { "CPU_IAMCU_FLAGS", > "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, > { "CPU_ADX_FLAGS", > @@ -461,6 +463,8 @@ static initializer cpu_flag_init[] = > "CpuCMPCCXADD" }, > { "CPU_ANY_WRMSRNS_FLAGS", > "CpuWRMSRNS" }, > + { "CPU_ANY_MSRLIST_FLAGS", > + "CpuMSRLIST" }, > }; > > static initializer operand_type_init[] = > @@ -667,6 +671,7 @@ static bitfield cpu_flags[] = > BITFIELD (CpuAVX_VNNI_INT8), > BITFIELD (CpuCMPCCXADD), > BITFIELD (CpuWRMSRNS), > + BITFIELD (CpuMSRLIST), > BITFIELD (CpuMWAITX), > BITFIELD (CpuCLZERO), > BITFIELD (CpuOSPKE), > diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h > index f00babfce2..a409b10ca1 100644 > --- a/opcodes/i386-opc.h > +++ b/opcodes/i386-opc.h > @@ -219,6 +219,8 @@ enum > CpuCMPCCXADD, > /* Intel WRMSRNS Instructions support required */ > CpuWRMSRNS, > + /* Intel MSRLIST Instructions support required. */ > + CpuMSRLIST, > /* mwaitx instruction required */ > CpuMWAITX, > /* Clzero instruction required */ > @@ -405,6 +407,7 @@ typedef union i386_cpu_flags > unsigned int cpuavx_vnni_int8:1; > unsigned int cpucmpccxadd:1; > unsigned int cpuwrmsrns:1; > + unsigned int cpumsrlist:1; > unsigned int cpumwaitx:1; > unsigned int cpuclzero:1; > unsigned int cpuospke:1; > diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl > index 3e947cd248..f1d17171c3 100644 > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -3301,3 +3301,10 @@ cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVV > wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > > // WRMSRNS instruction end. > + > +// MSRLIST instructions. > + > +rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > +wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} > + > +// MSRLIST instructions end. > -- > 2.18.1 > OK. Thanks. -- H.J. ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-11-02 16:26 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-10-31 3:05 [PATCH v4 0/6] Support Intel Sierra Forest Instructions Haochen Jiang 2022-10-31 3:05 ` [PATCH 1/6] Support Intel AVX-IFMA Haochen Jiang 2022-10-31 16:52 ` H.J. Lu 2022-10-31 3:05 ` [PATCH 2/6] Support Intel AVX-VNNI-INT8 Haochen Jiang 2022-10-31 16:53 ` H.J. Lu 2022-11-02 10:45 ` Jan Beulich 2022-10-31 3:05 ` [PATCH 3/6] Support Intel CMPccXADD Haochen Jiang 2022-10-31 16:54 ` H.J. Lu 2022-11-02 10:52 ` Jan Beulich 2022-11-02 16:25 ` H.J. Lu 2022-10-31 3:05 ` [PATCH 4/6] Add handler for more i386_cpu_flags Haochen Jiang 2022-10-31 16:54 ` H.J. Lu 2022-10-31 3:05 ` [PATCH 5/6] Support Intel WRMSRNS Haochen Jiang 2022-10-31 16:56 ` H.J. Lu 2022-11-02 10:56 ` Jan Beulich 2022-11-02 14:35 ` Jan Beulich 2022-10-31 3:05 ` [PATCH 6/6] Support Intel MSRLIST Haochen Jiang 2022-10-31 16:55 ` H.J. Lu
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