* [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
@ 2023-09-05 14:52 Mary Bennett
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Mary Bennett @ 2023-09-05 14:52 UTC (permalink / raw)
To: binutils; +Cc: Mary Bennett
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
[2] github.com/openhwgroup/corev-binutils-gdb
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
RISC-V: Add support for XCValu extension in CV32E40P
RISC-V: Add support for XCVmac extension in CV32E40P
bfd/elfxx-riscv.c | 11 ++
gas/config/tc-riscv.c | 60 +++++++
gas/doc/c-riscv.texi | 10 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 +
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 +
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 56 +++++++
include/opcode/riscv.h | 12 ++
opcodes/riscv-dis.c | 20 +++
opcodes/riscv-opc.c | 61 +++++++
44 files changed, 1406 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
@ 2023-09-05 14:52 ` Mary Bennett
2023-09-07 4:35 ` Nelson Chu
2023-09-05 14:53 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Mary Bennett @ 2023-09-05 14:52 UTC (permalink / raw)
To: binutils
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
---
bfd/elfxx-riscv.c | 6 +
gas/config/tc-riscv.c | 45 +++++
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 21 +++
include/opcode/riscv.h | 7 +
opcodes/riscv-dis.c | 16 ++
opcodes/riscv-opc.c | 26 +++
15 files changed, 650 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb65024beaf..a3c32941866 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1347,6 +1347,8 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
+ /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
+ {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2539,6 +2541,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
+ case INSN_CLASS_XCVMAC:
+ return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2779,6 +2783,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
+ case INSN_CLASS_XCVMAC:
+ return "xcvmac";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e49b34fd524..3100a2e135f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1470,6 +1470,25 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
}
}
break;
+ case 'x': /* Vendor-specific operands. */
+ switch (*++oparg)
+ {
+ /* Vendor-specific (CORE-V) operands. */
+ case 'c':
+ switch (*++oparg)
+ {
+ case '3':
+ used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
+ break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
+
default:
unknown_validate_operand:
as_bad (_("internal: bad RISC-V opcode "
@@ -3669,6 +3688,32 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;
+ case 'x': /* Vendor-specific operands. */
+ switch (*++oparg)
+ {
+ /* Vendor-specific (CORE-V) operands. */
+ case 'c':
+ switch (*++oparg)
+ {
+ case '3':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number<0
+ || imm_expr->X_add_number>31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
+ continue;
+ default:
+ goto unknown_riscv_ip_operand;
+ }
+ break;
+ default:
+ goto unknown_riscv_ip_operand;
+ }
+ break;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index b175ba0a729..1dcdeeb7b36 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -745,6 +745,11 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
+@item Xcvmac
+The Xcvmac extension provides instructions for multiply-accumulate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.d b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
new file mode 100644
index 00000000000..eb6352f85f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-mac-fail-march.s
+#error_output: cv-mac-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.l b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
new file mode 100644
index 00000000000..d2bc12c804a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
@@ -0,0 +1,23 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension `xcvmac' required
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.s b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
new file mode 100644
index 00000000000..78b08423a64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
@@ -0,0 +1,24 @@
+# Absence of the xcvmac march option disables all CORE-V MAC extensions.
+target:
+ cv.mac t4, t2, t0
+ cv.msu t4, t2, t0
+ cv.muls t4, t2, t0
+ cv.mulhhs t4, t2, t0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulu t4, t2, t0
+ cv.mulhhu t4, t2, t0
+ cv.mulun t4, t2, t0, 7
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulurn t4, t2, t0, 11
+ cv.mulhhurn t4, t2, t0, 9
+ cv.macsn t4, t2, t0, 24
+ cv.machhsn t4, t2, t0, 11
+ cv.macsrn t4, t2, t0, 9
+ cv.machhsrn t4, t2, t0, 24
+ cv.macun t4, t2, t0, 27
+ cv.machhun t4, t2, t0, 18
+ cv.macurn t4, t2, t0, 25
+ cv.machhurn t4, t2, t0, 5
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
new file mode 100644
index 00000000000..51e1b3052c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmac
+#source: cv-mac-fail-operand.s
+#error_output: cv-mac-fail-operand.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
new file mode 100644
index 00000000000..645949696cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
@@ -0,0 +1,147 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.mac 8,t2,t0'
+.*: Error: illegal operands `cv.msu 23,t2,t0'
+.*: Error: illegal operands `cv.muls 43,t2,t0'
+.*: Error: illegal operands `cv.mulhhs 7,t2,t0'
+.*: Error: illegal operands `cv.mulsn 345,t2,t0,4'
+.*: Error: illegal operands `cv.mulhhsn 356,t2,t0,16'
+.*: Error: illegal operands `cv.mulsrn 867,t2,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn 3454,t2,t0,17'
+.*: Error: illegal operands `cv.mulu 9,t2,t0'
+.*: Error: illegal operands `cv.mulhhu 54,t2,t0'
+.*: Error: illegal operands `cv.mulun 965,t2,t0,7'
+.*: Error: illegal operands `cv.mulhhun 35,t2,t0,16'
+.*: Error: illegal operands `cv.mulurn 87,t2,t0,11'
+.*: Error: illegal operands `cv.mulhhurn 38,t2,t0,9'
+.*: Error: illegal operands `cv.macsn 985,t2,t0,24'
+.*: Error: illegal operands `cv.machhsn 83,t2,t0,11'
+.*: Error: illegal operands `cv.macsrn 960,t2,t0,9'
+.*: Error: illegal operands `cv.machhsrn 385,t2,t0,24'
+.*: Error: illegal operands `cv.macun 58,t2,t0,27'
+.*: Error: illegal operands `cv.machhun 6,t2,t0,18'
+.*: Error: illegal operands `cv.macurn 35,t2,t0,25'
+.*: Error: illegal operands `cv.machhurn 67,t2,t0,5'
+.*: Error: illegal operands `cv.mac t4,43,t0'
+.*: Error: illegal operands `cv.msu t4,3,t0'
+.*: Error: illegal operands `cv.muls t4,345,t0'
+.*: Error: illegal operands `cv.mulhhs t4,54,t0'
+.*: Error: illegal operands `cv.mulsn t4,4,t0,4'
+.*: Error: illegal operands `cv.mulhhsn t4,35,t0,16'
+.*: Error: illegal operands `cv.mulsrn t4,53,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,4456,t0,17'
+.*: Error: illegal operands `cv.mulu t4,868,t0'
+.*: Error: illegal operands `cv.mulhhu t4,95,t0'
+.*: Error: illegal operands `cv.mulun t4,584,t0,7'
+.*: Error: illegal operands `cv.mulhhun t4,37545,t0,16'
+.*: Error: illegal operands `cv.mulurn t4,943,t0,11'
+.*: Error: illegal operands `cv.mulhhurn t4,34,t0,9'
+.*: Error: illegal operands `cv.macsn t4,93,t0,24'
+.*: Error: illegal operands `cv.machhsn t4,584,t0,11'
+.*: Error: illegal operands `cv.macsrn t4,28,t0,9'
+.*: Error: illegal operands `cv.machhsrn t4,9,t0,24'
+.*: Error: illegal operands `cv.macun t4,834,t0,27'
+.*: Error: illegal operands `cv.machhun t4,92,t0,18'
+.*: Error: illegal operands `cv.macurn t4,49,t0,25'
+.*: Error: illegal operands `cv.machhurn t4,6,t0,5'
+.*: Error: illegal operands `cv.mac t4,t2,344'
+.*: Error: illegal operands `cv.msu t4,t2,23'
+.*: Error: illegal operands `cv.muls t4,t2,2'
+.*: Error: illegal operands `cv.mulhhs t4,t2,8'
+.*: Error: illegal operands `cv.mulsn t4,t2,45,4'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,655,16'
+.*: Error: illegal operands `cv.mulsrn t4,t2,465,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,3534,17'
+.*: Error: illegal operands `cv.mulu t4,t2,46'
+.*: Error: illegal operands `cv.mulhhu t4,t2,35'
+.*: Error: illegal operands `cv.mulun t4,t2,67,7'
+.*: Error: illegal operands `cv.mulhhun t4,t2,6,16'
+.*: Error: illegal operands `cv.mulurn t4,t2,787,11'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,3545,9'
+.*: Error: illegal operands `cv.macsn t4,t2,6,24'
+.*: Error: illegal operands `cv.machhsn t4,t2,765,11'
+.*: Error: illegal operands `cv.macsrn t4,t2,45,9'
+.*: Error: illegal operands `cv.machhsrn t4,t2,7,24'
+.*: Error: illegal operands `cv.macun t4,t2,98,27'
+.*: Error: illegal operands `cv.machhun t4,t2,654,18'
+.*: Error: illegal operands `cv.macurn t4,t2,900,25'
+.*: Error: illegal operands `cv.machhurn t4,t2,354,5'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-43'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-23'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-223'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-8'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-2'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-45'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-354'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macun t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,325'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,254'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,76'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,5364'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,34435'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,3423'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,365'
+.*: Error: illegal operands `cv.macun t4,t2,t0,432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,45'
+.*: Error: instruction cv.mulsn requires absolute expression
+.*: Error: instruction cv.mulhhsn requires absolute expression
+.*: Error: instruction cv.mulsrn requires absolute expression
+.*: Error: instruction cv.mulhhsrn requires absolute expression
+.*: Error: instruction cv.mulun requires absolute expression
+.*: Error: instruction cv.mulhhun requires absolute expression
+.*: Error: instruction cv.mulurn requires absolute expression
+.*: Error: instruction cv.mulhhurn requires absolute expression
+.*: Error: instruction cv.macsn requires absolute expression
+.*: Error: instruction cv.machhsn requires absolute expression
+.*: Error: instruction cv.macsrn requires absolute expression
+.*: Error: instruction cv.machhsrn requires absolute expression
+.*: Error: instruction cv.macun requires absolute expression
+.*: Error: instruction cv.machhun requires absolute expression
+.*: Error: instruction cv.macurn requires absolute expression
+.*: Error: instruction cv.machhurn requires absolute expression
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,354'
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
new file mode 100644
index 00000000000..97a29448ebd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
@@ -0,0 +1,156 @@
+# Destination must be of type register
+target:
+ cv.mac 8, t2, t0
+ cv.msu 23, t2, t0
+ cv.muls 43, t2, t0
+ cv.mulhhs 7, t2, t0
+ cv.mulsn 345, t2, t0, 4
+ cv.mulhhsn 356, t2, t0, 16
+ cv.mulsrn 867, t2, t0, 10
+ cv.mulhhsrn 3454, t2, t0, 17
+ cv.mulu 9, t2, t0
+ cv.mulhhu 54, t2, t0
+ cv.mulun 965, t2, t0, 7
+ cv.mulhhun 35, t2, t0, 16
+ cv.mulurn 87, t2, t0, 11
+ cv.mulhhurn 38, t2, t0, 9
+ cv.macsn 985, t2, t0, 24
+ cv.machhsn 83, t2, t0, 11
+ cv.macsrn 960, t2, t0, 9
+ cv.machhsrn 385, t2, t0, 24
+ cv.macun 58, t2, t0, 27
+ cv.machhun 6, t2, t0, 18
+ cv.macurn 35, t2, t0, 25
+ cv.machhurn 67, t2, t0, 5
+
+# Source one must be of type register
+ cv.mac t4, 43, t0
+ cv.msu t4, 3, t0
+ cv.muls t4, 345, t0
+ cv.mulhhs t4, 54, t0
+ cv.mulsn t4, 4, t0, 4
+ cv.mulhhsn t4, 35, t0, 16
+ cv.mulsrn t4, 53, t0, 10
+ cv.mulhhsrn t4, 4456, t0, 17
+ cv.mulu t4, 868, t0
+ cv.mulhhu t4, 95, t0
+ cv.mulun t4, 584, t0, 7
+ cv.mulhhun t4, 37545, t0, 16
+ cv.mulurn t4, 943, t0, 11
+ cv.mulhhurn t4, 34, t0, 9
+ cv.macsn t4, 93, t0, 24
+ cv.machhsn t4, 584, t0, 11
+ cv.macsrn t4, 28, t0, 9
+ cv.machhsrn t4, 9, t0, 24
+ cv.macun t4, 834, t0, 27
+ cv.machhun t4, 92, t0, 18
+ cv.macurn t4, 49, t0, 25
+ cv.machhurn t4, 6, t0, 5
+
+# Source two must be of type register
+ cv.mac t4, t2, 344
+ cv.msu t4, t2, 23
+ cv.muls t4, t2, 2
+ cv.mulhhs t4, t2, 8
+ cv.mulsn t4, t2, 45, 4
+ cv.mulhhsn t4, t2, 655, 16
+ cv.mulsrn t4, t2, 465, 10
+ cv.mulhhsrn t4, t2, 3534, 17
+ cv.mulu t4, t2, 46
+ cv.mulhhu t4, t2, 35
+ cv.mulun t4, t2, 67, 7
+ cv.mulhhun t4, t2, 6, 16
+ cv.mulurn t4, t2, 787, 11
+ cv.mulhhurn t4, t2, 3545, 9
+ cv.macsn t4, t2, 6, 24
+ cv.machhsn t4, t2, 765, 11
+ cv.macsrn t4, t2, 45, 9
+ cv.machhsrn t4, t2, 7, 24
+ cv.macun t4, t2, 98, 27
+ cv.machhun t4, t2, 654, 18
+ cv.macurn t4, t2, 900, 25
+ cv.machhurn t4, t2, 354, 5
+
+# Immediate value must be in range [0, 31]
+ cv.mulsn t4, t2, t0, -1
+ cv.mulhhsn t4, t2, t0, -1
+ cv.mulsrn t4, t2, t0, -1
+ cv.mulhhsrn t4, t2, t0, -1
+ cv.mulun t4, t2, t0, -1
+ cv.mulhhun t4, t2, t0, -1
+ cv.mulurn t4, t2, t0, -1
+ cv.mulhhurn t4, t2, t0, -1
+ cv.macsn t4, t2, t0, -1
+ cv.machhsn t4, t2, t0, -1
+ cv.macsrn t4, t2, t0, -1
+ cv.machhsrn t4, t2, t0, -1
+ cv.macun t4, t2, t0, -1
+ cv.machhun t4, t2, t0, -1
+ cv.macurn t4, t2, t0, -1
+ cv.machhurn t4, t2, t0, -1
+ cv.mulsn t4, t2, t0, -43
+ cv.mulhhsn t4, t2, t0, -531
+ cv.mulsrn t4, t2, t0, -4454
+ cv.mulhhsrn t4, t2, t0, -32
+ cv.mulun t4, t2, t0, -23
+ cv.mulhhun t4, t2, t0, -459
+ cv.mulurn t4, t2, t0, -549
+ cv.mulhhurn t4, t2, t0, -32
+ cv.macsn t4, t2, t0, -223
+ cv.machhsn t4, t2, t0, -56
+ cv.macsrn t4, t2, t0, -8
+ cv.machhsrn t4, t2, t0, -2
+ cv.macun t4, t2, t0, -432
+ cv.machhun t4, t2, t0, -1245
+ cv.macurn t4, t2, t0, -45
+ cv.machhurn t4, t2, t0, -354
+ cv.mulsn t4, t2, t0, 32
+ cv.mulhhsn t4, t2, t0, 32
+ cv.mulsrn t4, t2, t0, 32
+ cv.mulhhsrn t4, t2, t0, 32
+ cv.mulun t4, t2, t0, 32
+ cv.mulhhun t4, t2, t0, 32
+ cv.mulurn t4, t2, t0, 32
+ cv.mulhhurn t4, t2, t0, 32
+ cv.macsn t4, t2, t0, 32
+ cv.machhsn t4, t2, t0, 32
+ cv.macsrn t4, t2, t0, 32
+ cv.machhsrn t4, t2, t0, 32
+ cv.macun t4, t2, t0, 32
+ cv.machhun t4, t2, t0, 32
+ cv.macurn t4, t2, t0, 32
+ cv.machhurn t4, t2, t0, 32
+ cv.mulsn t4, t2, t0, 325
+ cv.mulhhsn t4, t2, t0, 531
+ cv.mulsrn t4, t2, t0, 4454
+ cv.mulhhsrn t4, t2, t0, 254
+ cv.mulun t4, t2, t0, 76
+ cv.mulhhun t4, t2, t0, 459
+ cv.mulurn t4, t2, t0, 549
+ cv.mulhhurn t4, t2, t0, 5364
+ cv.macsn t4, t2, t0, 34435
+ cv.machhsn t4, t2, t0, 56
+ cv.macsrn t4, t2, t0, 3423
+ cv.machhsrn t4, t2, t0, 365
+ cv.macun t4, t2, t0, 432
+ cv.machhun t4, t2, t0, 1245
+ cv.macurn t4, t2, t0, 45
+
+# Immediate value must be an absolute expression
+ cv.mulsn t4, t2, t0, t3
+ cv.mulhhsn t4, t2, t0, t1
+ cv.mulsrn t4, t2, t0, t6
+ cv.mulhhsrn t4, t2, t0, t3
+ cv.mulun t4, t2, t0, t1
+ cv.mulhhun t4, t2, t0, t3
+ cv.mulurn t4, t2, t0, t5
+ cv.mulhhurn t4, t2, t0, t1
+ cv.macsn t4, t2, t0, t3
+ cv.machhsn t4, t2, t0, t5
+ cv.macsrn t4, t2, t0, t1
+ cv.machhsrn t4, t2, t0, t6
+ cv.macun t4, t2, t0, t1
+ cv.machhun t4, t2, t0, t3
+ cv.macurn t4, t2, t0, t6
+ cv.machhurn t4, t2, t0, t5
+ cv.machhurn t4, t2, t0, 354
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.d b/gas/testsuite/gas/riscv/cv-mac-insns.d
new file mode 100644
index 00000000000..9a961051a97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.d
@@ -0,0 +1,87 @@
+#as: -march=rv32i_xcvmac
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
+[ ]+4:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
+[ ]+8:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
+[ ]+c:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
+[ ]+10:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
+[ ]+14:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
+[ ]+18:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
+[ ]+20:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
+[ ]+28:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
+[ ]+2c:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
+[ ]+30:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
+[ ]+34:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
+[ ]+38:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
+[ ]+3c:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
+[ ]+40:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
+[ ]+44:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
+[ ]+48:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
+[ ]+50:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
+[ ]+54:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
+[ ]+58:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
+[ ]+5c:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
+[ ]+60:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
+[ ]+64:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
+[ ]+68:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
+[ ]+6c:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
+[ ]+70:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
+[ ]+74:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
+[ ]+78:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+7c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+80:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+84:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+88:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
+[ ]+8c:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
+[ ]+90:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
+[ ]+94:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
+[ ]+98:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
+[ ]+9c:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+a0:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+a4:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+a8:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+ac:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
+[ ]+b0:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
+[ ]+b4:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
+[ ]+b8:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
+[ ]+bc:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
+[ ]+c0:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+c4:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+c8:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+cc:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+d0:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
+[ ]+d4:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
+[ ]+d8:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
+[ ]+dc:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
+[ ]+e0:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
+[ ]+e4:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+e8:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+ec:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
+[ ]+f0:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+f4:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
+[ ]+f8:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
+[ ]+fc:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
+[ ]+100:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
+[ ]+104:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
+[ ]+108:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+10c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+110:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+114:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+118:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+11c:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+120:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+124:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+128:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+12c:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+130:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+134:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.s b/gas/testsuite/gas/riscv/cv-mac-insns.s
new file mode 100644
index 00000000000..a699a3ba461
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.s
@@ -0,0 +1,81 @@
+target:
+ cv.mac t0, t1, t2
+ cv.mac t4, t2, t0
+ cv.mac t3, t5, t1
+ cv.machhsn t0, t1, t2, 0
+ cv.machhsn t4, t2, t0, 11
+ cv.machhsn t3, t5, t1, 31
+ cv.machhsrn t0, t1, t2, 0
+ cv.machhsrn t4, t2, t0, 24
+ cv.machhsrn t3, t5, t1, 31
+ cv.machhun t0, t1, t2, 0
+ cv.machhun t4, t2, t0, 18
+ cv.machhun t3, t5, t1, 31
+ cv.machhurn t0, t1, t2, 0
+ cv.machhurn t4, t2, t0, 5
+ cv.machhurn t3, t5, t1, 31
+ cv.macsn t0, t1, t2, 0
+ cv.macsn t4, t2, t0, 24
+ cv.macsn t3, t5, t1, 31
+ cv.macsrn t0, t1, t2, 0
+ cv.macsrn t4, t2, t0, 9
+ cv.macsrn t3, t5, t1, 31
+ cv.macun t0, t1, t2, 0
+ cv.macun t4, t2, t0, 27
+ cv.macun t3, t5, t1, 31
+ cv.macurn t0, t1, t2, 0
+ cv.macurn t4, t2, t0, 25
+ cv.macurn t3, t5, t1, 31
+ cv.msu t0, t1, t2
+ cv.msu t4, t2, t0
+ cv.msu t3, t5, t1
+ cv.mulhhs t0, t1, t2
+ cv.mulhhs t4, t2, t0
+ cv.mulhhs t3, t5, t1
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulhhsn t3, t5, t1, 31
+ cv.mulhhsrn t0, t1, t2, 0
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulhhsrn t3, t5, t1, 31
+ cv.mulhhu t0, t1, t2
+ cv.mulhhu t4, t2, t0
+ cv.mulhhu t3, t5, t1
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulhhun t3, t5, t1, 31
+ cv.mulhhurn t0, t1, t2, 0
+ cv.mulhhurn t4, t2, t0, 9
+ cv.mulhhurn t3, t5, t1, 31
+ cv.muls t0, t1, t2
+ cv.muls t4, t2, t0
+ cv.muls t3, t5, t1
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulsn t3, t5, t1, 31
+ cv.mulsrn t0, t1, t2, 0
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulsrn t3, t5, t1, 31
+ cv.mulu t0, t1, t2
+ cv.mulu t4, t2, t0
+ cv.mulu t3, t5, t1
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 7
+ cv.mulun t3, t5, t1, 31
+ cv.mulurn t0, t1, t2, 0
+ cv.mulurn t4, t2, t0, 11
+ cv.mulurn t3, t5, t1, 31
+
+ # Pseudo-instructions
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 0
+ cv.mulhhsn t3, t5, t1, 0
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 0
+ cv.mulhhun t3, t5, t1, 0
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 0
+ cv.mulsn t3, t5, t1, 0
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 0
+ cv.mulun t3, t5, t1, 0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 26d2c04bf24..199ae63585f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2320,6 +2320,27 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+#define MATCH_CV_MAC 0x9000302b
+#define MATCH_CV_MSU 0x9200302b
+#define MASK_CV_MACMSU 0xfe00707f
+#define MATCH_CV_MULSN 0x405b
+#define MATCH_CV_MULHHSN 0x4000405b
+#define MATCH_CV_MULSRN 0x8000405b
+#define MATCH_CV_MULHHSRN 0xc000405b
+#define MATCH_CV_MULUN 0x505b
+#define MATCH_CV_MULHHUN 0x4000505b
+#define MATCH_CV_MULURN 0x8000505b
+#define MATCH_CV_MULHHURN 0xc000505b
+#define MATCH_CV_MACSN 0x605b
+#define MATCH_CV_MACHHSN 0x4000605b
+#define MATCH_CV_MACSRN 0x8000605b
+#define MATCH_CV_MACHHSRN 0xc000605b
+#define MATCH_CV_MACUN 0x705b
+#define MATCH_CV_MACHHUN 0x4000705b
+#define MATCH_CV_MACURN 0x8000705b
+#define MATCH_CV_MACHHURN 0xc000705b
+#define MASK_CV_MULMACN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 38927bd0c74..5097d2cf6c1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -112,6 +112,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
+/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS3_UIMM5(x) \
+ (RV_X(x, 25, 5))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -163,6 +166,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
+/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS3_UIMM5(x) \
+ (RV_X(x, 0, 5) << 25)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -443,6 +449,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
+ INSN_CLASS_XCVMAC,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 90f0fea1692..b16db5113b1 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -429,6 +429,22 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "0");
break;
+ case 'x': /* Vendor-specific operands. */
+ switch (*++oparg)
+ {
+ /* Vendor-specific (CORE-V) operands. */
+ case 'c':
+ switch (*++oparg)
+ {
+ case '3':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS3_UIMM5 (l)));
+ break;
+ }
+ break;
+ }
+ break;
+
case 's':
if ((l & MASK_JALR) == MATCH_JALR)
maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 39da5f84e74..1b2023b96bd 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -154,6 +154,8 @@ const float riscv_fli_numval[32] =
#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+/* Vendor-specific (CORE-V) masks. */
+#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)
static int
match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -2039,6 +2041,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MACMSU, match_opcode, 0},
+{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MACMSU, match_opcode, 0},
+{"cv.mulsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULSN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.muls", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULSN, MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULSRN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulhhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHSN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulhhs", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHSN, MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHSRN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULUN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULUN, MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULURN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulhhun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHUN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.mulhhu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHUN, MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHURN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.macsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACSN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.machhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHSN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.macsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACSRN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHSRN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.macun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACUN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.machhun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHUN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACURN, MASK_CV_MULMACN, match_opcode, 0},
+{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHURN, MASK_CV_MULMACN, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
@ 2023-09-05 14:53 ` Mary Bennett
2023-09-07 4:37 ` Nelson Chu
2023-09-07 4:49 ` [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Nelson Chu
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Mary Bennett @ 2023-09-05 14:53 UTC (permalink / raw)
To: binutils
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
* testsuite/gas/riscv/cv-alu-insns.d: New test.
* testsuite/gas/riscv/cv-alu-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble xcb operand.
* riscv-opc.c: Defined the MASK and added XCValu instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCValu.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for XCValu.
(enum riscv_insn_class): Added the XCValu instruction class.
---
bfd/elfxx-riscv.c | 5 +
gas/config/tc-riscv.c | 17 ++-
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 +++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 ++++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 ++++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 +++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 +++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++++++
include/opcode/riscv-opc.h | 35 +++++
include/opcode/riscv.h | 5 +
opcodes/riscv-dis.c | 24 ++--
opcodes/riscv-opc.c | 35 +++++
36 files changed, 767 insertions(+), 11 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a3c32941866..411f9976ffe 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1349,6 +1349,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
/* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2543,6 +2544,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "h");
case INSN_CLASS_XCVMAC:
return riscv_subset_supports (rps, "xcvmac");
+ case INSN_CLASS_XCVALU:
+ return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2785,6 +2788,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("h");
case INSN_CLASS_XCVMAC:
return "xcvmac";
+ case INSN_CLASS_XCVALU:
+ return "xcvalu";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3100a2e135f..4c201e02b80 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1477,7 +1477,12 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'c':
switch (*++oparg)
{
+ case '2':
+ /* ls2[4:0] */
+ used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
+ break;
case '3':
+ /* ls3[4:0] */
used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
break;
default:
@@ -3695,6 +3700,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'c':
switch (*++oparg)
{
+ case '2':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number<0
+ || imm_expr->X_add_number>31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+ continue;
case '3':
my_getExpression (imm_expr, asarg);
check_absolute_expr (ip, imm_expr, FALSE);
@@ -3712,7 +3727,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
default:
goto unknown_riscv_ip_operand;
}
- break;
+ break;
default:
unknown_riscv_ip_operand:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 1dcdeeb7b36..61e744ae633 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvmac extension provides instructions for multiply-accumulate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+@item Xcvalu
+The Xcvalu extension provides instructions for general ALU operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
new file mode 100644
index 00000000000..907b043aebc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-boundaries.s
+#error_output: cv-alu-boundaries.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
new file mode 100644
index 00000000000..fae4022244c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subnr 10,t3,t6'
+.*: Error: illegal operands `cv.addrnr t4,26,t6'
+.*: Error: illegal operands `cv.subunr t6,t3,15'
+.*: Error: instruction cv.clipu requires absolute expression
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: illegal operands `cv.clipu t0,t3,-10'
+.*: Error: illegal operands `cv.clipu t0,t3,500'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
+.*: Error: illegal operands `cv.addn t0,t3,t6,302'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
+.*: Error: illegal operands `cv.addn t0,t3,t6,32'
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
new file mode 100644
index 00000000000..bb4da949b4a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
@@ -0,0 +1,27 @@
+# Destination must be of type register
+target:
+ cv.subnr 10, t3, t6
+# Source 1 must be of type register
+ cv.addrnr t4, 26, t6
+# Source 2 must be of type register
+ cv.subunr t6, t3, 15
+# Five bit immediate must be an absolute value
+ cv.clipu t0, t3, t6
+# Five bit immediate must be an absolute value
+ cv.addn t0, t3, t6, t2
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -10
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 500
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -60
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 302
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 32
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 32
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
new file mode 100644
index 00000000000..963aa4012da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-alu-fail-march.s
+#error_output: cv-alu-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
new file mode 100644
index 00000000000..11e5a7cd279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' required
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
new file mode 100644
index 00000000000..8dd39b7301f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
@@ -0,0 +1,33 @@
+# Absence of xcv or xcvalu march option disables all CORE-V general ALU ops extensions
+target:
+ cv.abs t4,t2
+ cv.slet t4,t2,t6
+ cv.sletu t4,t2,t6
+ cv.min t4,t2,t6
+ cv.minu t4,t2,t6
+ cv.max t4,t2,t6
+ cv.maxu t4,t2,t6
+ cv.exths t4,t2
+ cv.exthz t4,t2
+ cv.extbs t4,t2
+ cv.extbz t4,t2
+ cv.clip t4,t2,5
+ cv.clipu t4,t2,5
+ cv.clipr t4,t2,t6
+ cv.clipur t4,t2,t6
+ cv.addn t4, t2, t0, 4
+ cv.addun t4, t2, t0, 4
+ cv.addrn t6, t0, t3, 9
+ cv.addurn t6, t0, t3, 14
+ cv.addnr t6, t0, t3
+ cv.addunr t6, t0, t3
+ cv.addrnr t6, t0, t3
+ cv.addurnr t6, t0, t3
+ cv.subn t6, t0, t3, 6
+ cv.subun t6, t0, t3, 24
+ cv.subrn t6, t0, t3, 21
+ cv.suburn t6, t0, t3, 3
+ cv.subnr t6, t0, t3
+ cv.subunr t6, t0, t3
+ cv.subrnr t6, t0, t3
+ cv.suburnr t6, t0, t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
new file mode 100644
index 00000000000..81b17348c32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-01.s
+#error_output: cv-alu-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
new file mode 100644
index 00000000000..f670e4341fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs 5,t2'
+.*: Error: illegal operands `cv.slet 10,t2,t6'
+.*: Error: illegal operands `cv.sletu 11,t2,t6'
+.*: Error: illegal operands `cv.min 15,t2,t6'
+.*: Error: illegal operands `cv.minu 16,t2,t6'
+.*: Error: illegal operands `cv.max 8,t2,t6'
+.*: Error: illegal operands `cv.maxu 3,t2,t6'
+.*: Error: illegal operands `cv.exths 2,t2'
+.*: Error: illegal operands `cv.exthz 6,t2'
+.*: Error: illegal operands `cv.extbs 4,t2'
+.*: Error: illegal operands `cv.extbz 7,t2'
+.*: Error: illegal operands `cv.clip 17,t2,5'
+.*: Error: illegal operands `cv.clipu 11,t2,5'
+.*: Error: illegal operands `cv.clipr 16,t2,t6'
+.*: Error: illegal operands `cv.clipur 15,t2,t6'
+.*: Error: illegal operands `cv.addn 9,t2,t0,4'
+.*: Error: illegal operands `cv.addun 30,t2,t0,4'
+.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
+.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
+.*: Error: illegal operands `cv.addnr 2,t0,t3'
+.*: Error: illegal operands `cv.addunr 26,t0,t3'
+.*: Error: illegal operands `cv.addrnr 3,t0,t3'
+.*: Error: illegal operands `cv.addurnr 14,t0,t3'
+.*: Error: illegal operands `cv.subn 15,t0,t3,6'
+.*: Error: illegal operands `cv.subun 9,t0,t3,24'
+.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
+.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
+.*: Error: illegal operands `cv.subnr 3,t0,t3'
+.*: Error: illegal operands `cv.subunr 12,t0,t3'
+.*: Error: illegal operands `cv.subrnr 13,t0,t3'
+.*: Error: illegal operands `cv.suburnr 8,t0,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
new file mode 100644
index 00000000000..7920ebd53ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
@@ -0,0 +1,33 @@
+# Destination must be of type register
+target:
+ cv.abs 5,t2
+ cv.slet 10,t2,t6
+ cv.sletu 11,t2,t6
+ cv.min 15,t2,t6
+ cv.minu 16,t2,t6
+ cv.max 8,t2,t6
+ cv.maxu 3,t2,t6
+ cv.exths 2,t2
+ cv.exthz 6,t2
+ cv.extbs 4,t2
+ cv.extbz 7,t2
+ cv.clip 17,t2,5
+ cv.clipu 11,t2,5
+ cv.clipr 16,t2,t6
+ cv.clipur 15,t2,t6
+ cv.addn 9,t2,t0,4
+ cv.addun 30,t2,t0,4
+ cv.addrn 21,t0,t3,9
+ cv.addurn 6,t0,t3,14
+ cv.addnr 2,t0,t3
+ cv.addunr 26,t0,t3
+ cv.addrnr 3,t0,t3
+ cv.addurnr 14,t0,t3
+ cv.subn 15,t0,t3,6
+ cv.subun 9,t0,t3,24
+ cv.subrn 24,t0,t3,21
+ cv.suburn 25,t0,t3,3
+ cv.subnr 3,t0,t3
+ cv.subunr 12,t0,t3
+ cv.subrnr 13,t0,t3
+ cv.suburnr 8,t0,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
new file mode 100644
index 00000000000..46645aaf864
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-02.s
+#error_output: cv-alu-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
new file mode 100644
index 00000000000..0a888c7251b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs t4,5'
+.*: Error: illegal operands `cv.slet t4,7,t6'
+.*: Error: illegal operands `cv.sletu t4,3,t6'
+.*: Error: illegal operands `cv.min t4,5,t6'
+.*: Error: illegal operands `cv.minu t4,3,t6'
+.*: Error: illegal operands `cv.max t4,4,t6'
+.*: Error: illegal operands `cv.maxu t4,6,t6'
+.*: Error: illegal operands `cv.exths t4,30'
+.*: Error: illegal operands `cv.exthz t4,23'
+.*: Error: illegal operands `cv.extbs t4,25'
+.*: Error: illegal operands `cv.extbz t4,21'
+.*: Error: illegal operands `cv.clip t4,2,5'
+.*: Error: illegal operands `cv.clipu t4,16,5'
+.*: Error: illegal operands `cv.clipr t4,17,t6'
+.*: Error: illegal operands `cv.clipur t4,14,t6'
+.*: Error: illegal operands `cv.addn t4,5,t0,4'
+.*: Error: illegal operands `cv.addun t4,18,t0,4'
+.*: Error: illegal operands `cv.addrn t6,19,t3,9'
+.*: Error: illegal operands `cv.addurn t6,4,t3,14'
+.*: Error: illegal operands `cv.addnr t6,6,t3'
+.*: Error: illegal operands `cv.addunr t6,7,t3'
+.*: Error: illegal operands `cv.addrnr t6,9,t3'
+.*: Error: illegal operands `cv.addurnr t6,5,t3'
+.*: Error: illegal operands `cv.subn t6,11,t3,6'
+.*: Error: illegal operands `cv.subun t6,14,t3,24'
+.*: Error: illegal operands `cv.subrn t6,15,t3,21'
+.*: Error: illegal operands `cv.suburn t6,24,t3,3'
+.*: Error: illegal operands `cv.subnr t6,4,t3'
+.*: Error: illegal operands `cv.subunr t6,8,t3'
+.*: Error: illegal operands `cv.subrnr t6,7,t3'
+.*: Error: illegal operands `cv.suburnr t6,6,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
new file mode 100644
index 00000000000..6083f1f5044
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
@@ -0,0 +1,33 @@
+# Source 1 must be of type register
+target:
+ cv.abs t4,5
+ cv.slet t4,7,t6
+ cv.sletu t4,3,t6
+ cv.min t4,5,t6
+ cv.minu t4,3,t6
+ cv.max t4,4,t6
+ cv.maxu t4,6,t6
+ cv.exths t4,30
+ cv.exthz t4,23
+ cv.extbs t4,25
+ cv.extbz t4,21
+ cv.clip t4,2,5
+ cv.clipu t4,16,5
+ cv.clipr t4,17,t6
+ cv.clipur t4,14,t6
+ cv.addn t4,5,t0,4
+ cv.addun t4,18,t0,4
+ cv.addrn t6,19,t3,9
+ cv.addurn t6,4,t3,14
+ cv.addnr t6,6,t3
+ cv.addunr t6,7,t3
+ cv.addrnr t6,9,t3
+ cv.addurnr t6,5,t3
+ cv.subn t6,11,t3,6
+ cv.subun t6,14,t3,24
+ cv.subrn t6,15,t3,21
+ cv.suburn t6,24,t3,3
+ cv.subnr t6,4,t3
+ cv.subunr t6,8,t3
+ cv.subrnr t6,7,t3
+ cv.suburnr t6,6,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
new file mode 100644
index 00000000000..6f681289d12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-03.s
+#error_output: cv-alu-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
new file mode 100644
index 00000000000..c7a11184996
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.slet t4,t2,3'
+.*: Error: illegal operands `cv.sletu t4,t2,4'
+.*: Error: illegal operands `cv.min t4,t2,13'
+.*: Error: illegal operands `cv.minu t4,t2,7'
+.*: Error: illegal operands `cv.max t4,t2,17'
+.*: Error: illegal operands `cv.maxu t4,t2,30'
+.*: Error: illegal operands `cv.clipr t4,t2,18'
+.*: Error: illegal operands `cv.clipur t4,t2,29'
+.*: Error: illegal operands `cv.addn t4,t2,24,4'
+.*: Error: illegal operands `cv.addun t4,t2,6,4'
+.*: Error: illegal operands `cv.addrn t6,t0,7,9'
+.*: Error: illegal operands `cv.addurn t6,t0,18,14'
+.*: Error: illegal operands `cv.addnr t6,t0,15'
+.*: Error: illegal operands `cv.addunr t6,t0,24'
+.*: Error: illegal operands `cv.addrnr t6,t0,3'
+.*: Error: illegal operands `cv.addurnr t6,t0,2'
+.*: Error: illegal operands `cv.subn t6,t0,1,6'
+.*: Error: illegal operands `cv.subun t6,t0,8,24'
+.*: Error: illegal operands `cv.subrn t6,t0,18,21'
+.*: Error: illegal operands `cv.suburn t6,t0,25,3'
+.*: Error: illegal operands `cv.subnr t6,t0,14'
+.*: Error: illegal operands `cv.subunr t6,t0,7'
+.*: Error: illegal operands `cv.subrnr t6,t0,18'
+.*: Error: illegal operands `cv.suburnr t6,t0,26'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
new file mode 100644
index 00000000000..64ee8703579
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
@@ -0,0 +1,26 @@
+# Source 2 must be of type register
+target:
+ cv.slet t4,t2,3
+ cv.sletu t4,t2,4
+ cv.min t4,t2,13
+ cv.minu t4,t2,7
+ cv.max t4,t2,17
+ cv.maxu t4,t2,30
+ cv.clipr t4,t2,18
+ cv.clipur t4,t2,29
+ cv.addn t4,t2,24,4
+ cv.addun t4,t2,6,4
+ cv.addrn t6,t0,7,9
+ cv.addurn t6,t0,18,14
+ cv.addnr t6,t0,15
+ cv.addunr t6,t0,24
+ cv.addrnr t6,t0,3
+ cv.addurnr t6,t0,2
+ cv.subn t6,t0,1,6
+ cv.subun t6,t0,8,24
+ cv.subrn t6,t0,18,21
+ cv.suburn t6,t0,25,3
+ cv.subnr t6,t0,14
+ cv.subunr t6,t0,7
+ cv.subrnr t6,t0,18
+ cv.suburnr t6,t0,26
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
new file mode 100644
index 00000000000..634d9bfe091
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-04.s
+#error_output: cv-alu-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
new file mode 100644
index 00000000000..d6fd960f9e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.clip requires absolute expression
+.*: Error: instruction cv.clipu requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
new file mode 100644
index 00000000000..b97d52a77ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
@@ -0,0 +1,4 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.clip t4,t2,t3
+ cv.clipu t4,t2,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
new file mode 100644
index 00000000000..1b90d3e5757
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-05.s
+#error_output: cv-alu-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
new file mode 100644
index 00000000000..05b5289e743
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: instruction cv.addun requires absolute expression
+.*: Error: instruction cv.addrn requires absolute expression
+.*: Error: instruction cv.addurn requires absolute expression
+.*: Error: instruction cv.subn requires absolute expression
+.*: Error: instruction cv.subun requires absolute expression
+.*: Error: instruction cv.subrn requires absolute expression
+.*: Error: instruction cv.suburn requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
new file mode 100644
index 00000000000..1b0ac6f2d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.addn t4,t2,t0,t3
+ cv.addun t4,t2,t0,t3
+ cv.addrn t6,t0,t3,t2
+ cv.addurn t6,t0,t3,t2
+ cv.subn t6,t0,t3,t2
+ cv.subun t6,t0,t3,t2
+ cv.subrn t6,t0,t3,t2
+ cv.suburn t6,t0,t3,t2
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
new file mode 100644
index 00000000000..0a49e682c85
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-06.s
+#error_output: cv-alu-fail-operand-06.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
new file mode 100644
index 00000000000..d8059cb5e3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.clip t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clip t0,t3,-400'
+.*: Error: illegal operands `cv.clipu t0,t3,-985'
+.*: Error: illegal operands `cv.clip t0,t3,32'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.clip t0,t3,859'
+.*: Error: illegal operands `cv.clipu t0,t3,7283'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
new file mode 100644
index 00000000000..1b810bdda55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.clip t0,t3,-1
+ cv.clipu t0,t3,-1
+ cv.clip t0,t3,-400
+ cv.clipu t0,t3,-985
+ cv.clip t0,t3,32
+ cv.clipu t0,t3,32
+ cv.clip t0,t3,859
+ cv.clipu t0,t3,7283
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
new file mode 100644
index 00000000000..06d17fede7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-07.s
+#error_output: cv-alu-fail-operand-07.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
new file mode 100644
index 00000000000..5a34156afc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
+.*: Error: illegal operands `cv.addn t4,t2,t0,32'
+.*: Error: illegal operands `cv.addun t4,t2,t0,32'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subun t6,t0,t3,32'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addn t4,t2,t0,320'
+.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
+.*: Error: illegal operands `cv.subn t6,t0,t3,89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
new file mode 100644
index 00000000000..04788f69ddd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
@@ -0,0 +1,34 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.addn t4,t2,t0,-1
+ cv.addun t4,t2,t0,-1
+ cv.addrn t6,t0,t3,-1
+ cv.addurn t6,t0,t3,-1
+ cv.subn t6,t0,t3,-1
+ cv.subun t6,t0,t3,-1
+ cv.subrn t6,t0,t3,-1
+ cv.suburn t6,t0,t3,-1
+ cv.addn t4,t2,t0,-34
+ cv.addun t4,t2,t0,-3556
+ cv.addrn t6,t0,t3,-212
+ cv.addurn t6,t0,t3,-6584
+ cv.subn t6,t0,t3,-89
+ cv.subun t6,t0,t3,-9034
+ cv.subrn t6,t0,t3,-234
+ cv.suburn t6,t0,t3,-284
+ cv.addn t4,t2,t0,32
+ cv.addun t4,t2,t0,32
+ cv.addrn t6,t0,t3,32
+ cv.addurn t6,t0,t3,32
+ cv.subn t6,t0,t3,32
+ cv.subun t6,t0,t3,32
+ cv.subrn t6,t0,t3,32
+ cv.suburn t6,t0,t3,32
+ cv.addn t4,t2,t0,320
+ cv.addun t4,t2,t0,34534
+ cv.addrn t6,t0,t3,254
+ cv.addurn t6,t0,t3,398
+ cv.subn t6,t0,t3,89
+ cv.subun t6,t0,t3,3489
+ cv.subrn t6,t0,t3,143
+ cv.suburn t6,t0,t3,234
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d b/gas/testsuite/gas/riscv/cv-alu-insns.d
new file mode 100644
index 00000000000..784cf5ca6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.d
@@ -0,0 +1,102 @@
+#as: -march=rv32i_xcvalu
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
+[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
+[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
+[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
+[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
+[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
+[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
+[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
+[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
+[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
+[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
+[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
+[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
+[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
+[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
+[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
+[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
+[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
+[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
+[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
+[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
+[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
+[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
+[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
+[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
+[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
+[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
+[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
+[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
+[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
+[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
+[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
+[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
+[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
+[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
+[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
+[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
+[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
+[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
+[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
+[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
+[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
+[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
+[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
+[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
+[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
+[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
+[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
+[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
+[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
+[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
+[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
+[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
+[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
+[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
+[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
+[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
+[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
+[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
+[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
+[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
+[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
+[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
+[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
+[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
+[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
+[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
+[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
+[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
+[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
+[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
+[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
+[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
+[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
+[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
+[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
+[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
+[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
+[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
+[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
+[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
+[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
+[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
+[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
+[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
+[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
+[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
+[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
+[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
+[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s b/gas/testsuite/gas/riscv/cv-alu-insns.s
new file mode 100644
index 00000000000..82ea0c3b98d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.s
@@ -0,0 +1,124 @@
+target:
+ cv.abs t0,t1
+ cv.abs t4,t2
+ cv.abs t3,t5
+
+ cv.addnr t0, t3, t6
+ cv.addnr t6, t0, t3
+ cv.addnr t3, t6, t0
+
+ cv.addn t0, t1, t2, 0
+ cv.addn t4, t2, t0, 4
+ cv.addn t3, t5, t1, 31
+
+ cv.addrnr t0, t3, t6
+ cv.addrnr t6, t0, t3
+ cv.addrnr t3, t6, t0
+
+ cv.addrn t0, t3, t6, 0
+ cv.addrn t6, t0, t3, 9
+ cv.addrn t3, t6, t0, 31
+
+ cv.addunr t0, t3, t6
+ cv.addunr t6, t0, t3
+ cv.addunr t3, t6, t0
+
+ cv.addun t0, t1, t2, 0
+ cv.addun t4, t2, t0, 4
+ cv.addun t3, t5, t1, 31
+
+ cv.addurnr t0, t3, t6
+ cv.addurnr t6, t0, t3
+ cv.addurnr t3, t6, t0
+
+ cv.addurn t0, t3, t6, 0
+ cv.addurn t6, t0, t3, 14
+ cv.addurn t3, t6, t0, 31
+
+ cv.clipr t0,t1,t2
+ cv.clipr t4,t2,t6
+ cv.clipr t3,t5,t1
+
+ cv.clip t0,t1,0
+ cv.clip t4,t2,5
+ cv.clip t3,t5,31
+
+ cv.clipur t0,t1,t2
+ cv.clipur t4,t2,t6
+ cv.clipur t3,t5,t1
+
+ cv.clipu t0,t1,0
+ cv.clipu t4,t2,5
+ cv.clipu t3,t5,31
+
+ cv.extbs t0,t1
+ cv.extbs t4,t2
+ cv.extbs t3,t5
+
+ cv.extbz t0,t1
+ cv.extbz t4,t2
+ cv.extbz t3,t5
+
+ cv.exths t0,t1
+ cv.exths t4,t2
+ cv.exths t3,t5
+
+ cv.exthz t0,t1
+ cv.exthz t4,t2
+ cv.exthz t3,t5
+
+ cv.max t0,t1,t2
+ cv.max t4,t2,t6
+ cv.max t3,t5,t1
+
+ cv.maxu t0,t1,t2
+ cv.maxu t4,t2,t6
+ cv.maxu t3,t5,t1
+
+ cv.min t0,t1,t2
+ cv.min t4,t2,t6
+ cv.min t3,t5,t1
+
+ cv.minu t0,t1,t2
+ cv.minu t4,t2,t6
+ cv.minu t3,t5,t1
+
+ cv.sle t0,t1,t2
+ cv.sle t4,t2,t6
+ cv.sle t3,t5,t1
+
+ cv.sleu t0,t1,t2
+ cv.sleu t4,t2,t6
+ cv.sleu t3,t5,t1
+
+ cv.subnr t0, t3, t6
+ cv.subnr t6, t0, t3
+ cv.subnr t3, t6, t0
+
+ cv.subn t0, t3, t6, 0
+ cv.subn t6, t0, t3, 6
+ cv.subn t3, t6, t0, 31
+
+ cv.subrnr t0, t3, t6
+ cv.subrnr t6, t0, t3
+ cv.subrnr t3, t6, t0
+
+ cv.subrn t0, t3, t6, 0
+ cv.subrn t6, t0, t3, 21
+ cv.subrn t3, t6, t0, 31
+
+ cv.subunr t0, t3, t6
+ cv.subunr t6, t0, t3
+ cv.subunr t3, t6, t0
+
+ cv.subun t0, t3, t6, 0
+ cv.subun t6, t0, t3, 24
+ cv.subun t3, t6, t0, 31
+
+ cv.suburnr t0, t3, t6
+ cv.suburnr t6, t0, t3
+ cv.suburnr t3, t6, t0
+
+ cv.suburn t0, t3, t6, 0
+ cv.suburn t6, t0, t3, 3
+ cv.suburn t3, t6, t0, 31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 199ae63585f..9e0e090a8a7 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2341,6 +2341,41 @@
#define MATCH_CV_MACURN 0x8000705b
#define MATCH_CV_MACHHURN 0xc000705b
#define MASK_CV_MULMACN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+#define MATCH_CV_ABS 0x5000302b
+#define MASK_CV_ABS 0xfff0707f
+#define MATCH_CV_SLET 0x5200302b
+#define MASK_CV_SLET 0xfe00707f
+#define MATCH_CV_SLETU 0x5400302b
+#define MATCH_CV_MIN 0x5600302b
+#define MATCH_CV_MINU 0x5800302b
+#define MATCH_CV_MAX 0x5a00302b
+#define MATCH_CV_MAXU 0x5c00302b
+#define MATCH_CV_EXTHS 0x6000302b
+#define MATCH_CV_EXTHZ 0x6200302b
+#define MATCH_CV_EXTBS 0x6400302b
+#define MATCH_CV_EXTBZ 0x6600302b
+#define MATCH_CV_CLIP 0x7000302b
+#define MATCH_CV_CLIPU 0x7200302b
+#define MATCH_CV_CLIPR 0x7400302b
+#define MATCH_CV_CLIPUR 0x7600302b
+#define MATCH_CV_ADDNR 0x8000302b
+#define MATCH_CV_ADDUNR 0x8200302b
+#define MATCH_CV_ADDRNR 0x8400302b
+#define MATCH_CV_ADDURNR 0x8600302b
+#define MATCH_CV_SUBNR 0x8800302b
+#define MATCH_CV_SUBUNR 0x8a00302b
+#define MATCH_CV_SUBRNR 0x8c00302b
+#define MATCH_CV_SUBURNR 0x8e00302b
+#define MATCH_CV_ADDN 0x205b
+#define MASK_CV_ADDN 0xc000707f
+#define MATCH_CV_ADDUN 0x4000205b
+#define MATCH_CV_ADDRN 0x8000205b
+#define MATCH_CV_ADDURN 0xc000205b
+#define MATCH_CV_SUBN 0x305b
+#define MATCH_CV_SUBUN 0x4000305b
+#define MATCH_CV_SUBRN 0x8000305b
+#define MATCH_CV_SUBURN 0xc000305b
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5097d2cf6c1..18236a6150c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS2_UIMM5(x) \
+ (RV_X(x, 20, 5))
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
@@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS2_UIMM5(x) \
+ (RV_X(x, 0, 5) << 20)
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
@@ -450,6 +454,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
+ INSN_CLASS_XCVALU,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index b16db5113b1..d10a1e393e7 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -432,16 +432,20 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'x': /* Vendor-specific operands. */
switch (*++oparg)
{
- /* Vendor-specific (CORE-V) operands. */
- case 'c':
- switch (*++oparg)
- {
- case '3':
- print (info->stream, dis_style_immediate, "%d",
- ((int) EXTRACT_CV_IS3_UIMM5 (l)));
- break;
- }
- break;
+ /* Vendor-specific (CORE-V) operands. */
+ case 'c':
+ switch (*++oparg)
+ {
+ case '2':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS2_UIMM5 (l)));
+ break;
+ case '3':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS3_UIMM5 (l)));
+ break;
+ }
+ break;
}
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1b2023b96bd..0b4b4b7dd4d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2065,6 +2065,41 @@ const struct riscv_opcode riscv_opcodes[] =
{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACURN, MASK_CV_MULMACN, match_opcode, 0},
{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHURN, MASK_CV_MULMACN, match_opcode, 0},
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0},
+{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, MASK_CV_ABS, match_opcode, 0},
+{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_ABS, match_opcode, 0},
+{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, MASK_CV_ABS, match_opcode, 0},
+{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_ABS, match_opcode, 0},
+{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, 0},
+{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS},
+{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, 0},
+{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, INSN_ALIAS},
+{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, MASK_CV_SLET, match_opcode, 0},
+{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, MASK_CV_SLET, match_opcode, 0},
+{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, MASK_CV_SLET, match_opcode, 0},
+{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_SLET, match_opcode, 0},
+{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIP, MASK_CV_SLET, match_opcode, 0},
+{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIPU, MASK_CV_SLET, match_opcode, 0},
+{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_SLET, match_opcode, 0},
+{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_SLET, match_opcode, 0},
+{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDUN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDRN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDURN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBUN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBRN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBURN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SLET, match_opcode, 0},
+{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SLET, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
@ 2023-09-07 4:35 ` Nelson Chu
0 siblings, 0 replies; 16+ messages in thread
From: Nelson Chu @ 2023-09-07 4:35 UTC (permalink / raw)
To: Mary Bennett; +Cc: binutils
[-- Attachment #1: Type: text/plain, Size: 43226 bytes --]
Hi,
I just noticed that - it isn't clear from the old code that the operands,
which are named starting with X, are reserved for vendors. Therefore, I
sent the patch to clarify the vendor operands' naming rules,
https://sourceware.org/pipermail/binutils/2023-September/129414.html. So
that everything vendor operands will be named starting with X, and then
follows one letter (or a keyword in the future) to represent which vendors
belonged.
Thanks
Nelson
On Tue, Sep 5, 2023 at 10:54 PM Mary Bennett <mary.bennett@embecosm.com>
wrote:
> Spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
> instruction class.
> (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (validate_riscv_insn): Added the necessary
> operands for the extension.
> (riscv_ip): Likewise.
> * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
> for CORE-V.
> * testsuite/gas/riscv/cv-mac-fail-march.d: New test.
> * testsuite/gas/riscv/cv-mac-fail-march.l: New test.
> * testsuite/gas/riscv/cv-mac-fail-march.s: New test.
> * testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
> * testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
> * testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
> * testsuite/gas/riscv/cv-mac-insns.d: New test.
> * testsuite/gas/riscv/cv-mac-insns.s: New test.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (print_insn_args): Disassemble information with
> the EXTRACT macro implemented.
> * riscv-opc.c: Defined the MASK and added
> XCVmac instructions.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
> for XCVmac.
> * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
> for uimm.
> (enum riscv_insn_class): Added the XCVmac instruction class.
> ---
> bfd/elfxx-riscv.c | 6 +
> gas/config/tc-riscv.c | 45 +++++
> gas/doc/c-riscv.texi | 5 +
> gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
> gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
> include/opcode/riscv-opc.h | 21 +++
> include/opcode/riscv.h | 7 +
> opcodes/riscv-dis.c | 16 ++
> opcodes/riscv-opc.c | 26 +++
> 15 files changed, 650 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cb65024beaf..a3c32941866 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1347,6 +1347,8 @@ static struct riscv_supported_ext
> riscv_supported_std_zxm_ext[] =
>
> static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
> {
> + /* CORE-V ISA extension spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> */
> + {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>
The document link should already be recorded in gas/doc/c-riscv.texi.
> {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2539,6 +2541,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> return riscv_subset_supports (rps, "h");
> + case INSN_CLASS_XCVMAC:
> + return riscv_subset_supports (rps, "xcvmac");
> case INSN_CLASS_XTHEADBA:
> return riscv_subset_supports (rps, "xtheadba");
> case INSN_CLASS_XTHEADBB:
> @@ -2779,6 +2783,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return "svinval";
> case INSN_CLASS_H:
> return _("h");
> + case INSN_CLASS_XCVMAC:
> + return "xcvmac";
> case INSN_CLASS_XTHEADBA:
> return "xtheadba";
> case INSN_CLASS_XTHEADBB:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index e49b34fd524..3100a2e135f 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1470,6 +1470,25 @@ validate_riscv_insn (const struct riscv_opcode
> *opc, int length)
> }
> }
> break;
> + case 'x': /* Vendor-specific operands. */
>
Considering consistency, it's better to use `X'.
> + switch (*++oparg)
> + {
> + /* Vendor-specific (CORE-V) operands. */
> + case 'c':
> + switch (*++oparg)
> + {
> + case '3':
> + used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
> + break;
> + default:
> + goto unknown_validate_operand;
> + }
> + break;
> + default:
> + goto unknown_validate_operand;
> + }
> + break;
> +
> default:
> unknown_validate_operand:
> as_bad (_("internal: bad RISC-V opcode "
> @@ -3669,6 +3688,32 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> }
> break;
>
> + case 'x': /* Vendor-specific operands. */
>
Likewise.
> + switch (*++oparg)
> + {
> + /* Vendor-specific (CORE-V) operands. */
> + case 'c':
>
Use c to represent vendor core-v looks reasonable.
> + switch (*++oparg)
> + {
> + case '3':
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + asarg = expr_parse_end;
> + if (imm_expr->X_add_number<0
> + || imm_expr->X_add_number>31)
> + break;
> + ip->insn_opcode
> + |= ENCODE_CV_IS3_UIMM5
> (imm_expr->X_add_number);
> + continue;
> + default:
> + goto unknown_riscv_ip_operand;
> + }
> + break;
> + default:
> + goto unknown_riscv_ip_operand;
> + }
> + break;
> +
> default:
> unknown_riscv_ip_operand:
> as_fatal (_("internal: unknown argument type `%s'"),
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index b175ba0a729..1dcdeeb7b36 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -745,6 +745,11 @@ extensions supported and provides the location of
> their
> publicly-released documentation:
>
> @table @r
> +@item Xcvmac
> +The Xcvmac extension provides instructions for multiply-accumulate
> operations.
> +
> +It is documented in @url{
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> }
> +
> @item XTheadBa
> The XTheadBa extension provides instructions for address calculations.
>
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.d
> b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
> new file mode 100644
> index 00000000000..eb6352f85f2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: cv-mac-fail-march.s
> +#error_output: cv-mac-fail-march.l
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.l
> b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
> new file mode 100644
> index 00000000000..d2bc12c804a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
> @@ -0,0 +1,23 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac'
> required
> +.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension
> `xcvmac' required
> +.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension
> `xcvmac' required
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.s
> b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
> new file mode 100644
> index 00000000000..78b08423a64
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
> @@ -0,0 +1,24 @@
> +# Absence of the xcvmac march option disables all CORE-V MAC extensions.
> +target:
> + cv.mac t4, t2, t0
> + cv.msu t4, t2, t0
> + cv.muls t4, t2, t0
> + cv.mulhhs t4, t2, t0
> + cv.mulsn t4, t2, t0, 4
> + cv.mulhhsn t4, t2, t0, 16
> + cv.mulsrn t4, t2, t0, 10
> + cv.mulhhsrn t4, t2, t0, 17
> + cv.mulu t4, t2, t0
> + cv.mulhhu t4, t2, t0
> + cv.mulun t4, t2, t0, 7
> + cv.mulhhun t4, t2, t0, 16
> + cv.mulurn t4, t2, t0, 11
> + cv.mulhhurn t4, t2, t0, 9
> + cv.macsn t4, t2, t0, 24
> + cv.machhsn t4, t2, t0, 11
> + cv.macsrn t4, t2, t0, 9
> + cv.machhsrn t4, t2, t0, 24
> + cv.macun t4, t2, t0, 27
> + cv.machhun t4, t2, t0, 18
> + cv.macurn t4, t2, t0, 25
> + cv.machhurn t4, t2, t0, 5
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> new file mode 100644
> index 00000000000..51e1b3052c9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvmac
> +#source: cv-mac-fail-operand.s
> +#error_output: cv-mac-fail-operand.l
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> new file mode 100644
> index 00000000000..645949696cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> @@ -0,0 +1,147 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.mac 8,t2,t0'
> +.*: Error: illegal operands `cv.msu 23,t2,t0'
> +.*: Error: illegal operands `cv.muls 43,t2,t0'
> +.*: Error: illegal operands `cv.mulhhs 7,t2,t0'
> +.*: Error: illegal operands `cv.mulsn 345,t2,t0,4'
> +.*: Error: illegal operands `cv.mulhhsn 356,t2,t0,16'
> +.*: Error: illegal operands `cv.mulsrn 867,t2,t0,10'
> +.*: Error: illegal operands `cv.mulhhsrn 3454,t2,t0,17'
> +.*: Error: illegal operands `cv.mulu 9,t2,t0'
> +.*: Error: illegal operands `cv.mulhhu 54,t2,t0'
> +.*: Error: illegal operands `cv.mulun 965,t2,t0,7'
> +.*: Error: illegal operands `cv.mulhhun 35,t2,t0,16'
> +.*: Error: illegal operands `cv.mulurn 87,t2,t0,11'
> +.*: Error: illegal operands `cv.mulhhurn 38,t2,t0,9'
> +.*: Error: illegal operands `cv.macsn 985,t2,t0,24'
> +.*: Error: illegal operands `cv.machhsn 83,t2,t0,11'
> +.*: Error: illegal operands `cv.macsrn 960,t2,t0,9'
> +.*: Error: illegal operands `cv.machhsrn 385,t2,t0,24'
> +.*: Error: illegal operands `cv.macun 58,t2,t0,27'
> +.*: Error: illegal operands `cv.machhun 6,t2,t0,18'
> +.*: Error: illegal operands `cv.macurn 35,t2,t0,25'
> +.*: Error: illegal operands `cv.machhurn 67,t2,t0,5'
> +.*: Error: illegal operands `cv.mac t4,43,t0'
> +.*: Error: illegal operands `cv.msu t4,3,t0'
> +.*: Error: illegal operands `cv.muls t4,345,t0'
> +.*: Error: illegal operands `cv.mulhhs t4,54,t0'
> +.*: Error: illegal operands `cv.mulsn t4,4,t0,4'
> +.*: Error: illegal operands `cv.mulhhsn t4,35,t0,16'
> +.*: Error: illegal operands `cv.mulsrn t4,53,t0,10'
> +.*: Error: illegal operands `cv.mulhhsrn t4,4456,t0,17'
> +.*: Error: illegal operands `cv.mulu t4,868,t0'
> +.*: Error: illegal operands `cv.mulhhu t4,95,t0'
> +.*: Error: illegal operands `cv.mulun t4,584,t0,7'
> +.*: Error: illegal operands `cv.mulhhun t4,37545,t0,16'
> +.*: Error: illegal operands `cv.mulurn t4,943,t0,11'
> +.*: Error: illegal operands `cv.mulhhurn t4,34,t0,9'
> +.*: Error: illegal operands `cv.macsn t4,93,t0,24'
> +.*: Error: illegal operands `cv.machhsn t4,584,t0,11'
> +.*: Error: illegal operands `cv.macsrn t4,28,t0,9'
> +.*: Error: illegal operands `cv.machhsrn t4,9,t0,24'
> +.*: Error: illegal operands `cv.macun t4,834,t0,27'
> +.*: Error: illegal operands `cv.machhun t4,92,t0,18'
> +.*: Error: illegal operands `cv.macurn t4,49,t0,25'
> +.*: Error: illegal operands `cv.machhurn t4,6,t0,5'
> +.*: Error: illegal operands `cv.mac t4,t2,344'
> +.*: Error: illegal operands `cv.msu t4,t2,23'
> +.*: Error: illegal operands `cv.muls t4,t2,2'
> +.*: Error: illegal operands `cv.mulhhs t4,t2,8'
> +.*: Error: illegal operands `cv.mulsn t4,t2,45,4'
> +.*: Error: illegal operands `cv.mulhhsn t4,t2,655,16'
> +.*: Error: illegal operands `cv.mulsrn t4,t2,465,10'
> +.*: Error: illegal operands `cv.mulhhsrn t4,t2,3534,17'
> +.*: Error: illegal operands `cv.mulu t4,t2,46'
> +.*: Error: illegal operands `cv.mulhhu t4,t2,35'
> +.*: Error: illegal operands `cv.mulun t4,t2,67,7'
> +.*: Error: illegal operands `cv.mulhhun t4,t2,6,16'
> +.*: Error: illegal operands `cv.mulurn t4,t2,787,11'
> +.*: Error: illegal operands `cv.mulhhurn t4,t2,3545,9'
> +.*: Error: illegal operands `cv.macsn t4,t2,6,24'
> +.*: Error: illegal operands `cv.machhsn t4,t2,765,11'
> +.*: Error: illegal operands `cv.macsrn t4,t2,45,9'
> +.*: Error: illegal operands `cv.machhsrn t4,t2,7,24'
> +.*: Error: illegal operands `cv.macun t4,t2,98,27'
> +.*: Error: illegal operands `cv.machhun t4,t2,654,18'
> +.*: Error: illegal operands `cv.macurn t4,t2,900,25'
> +.*: Error: illegal operands `cv.machhurn t4,t2,354,5'
> +.*: Error: illegal operands `cv.mulsn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulun t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulurn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.macsn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.machhsn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.macsrn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.macun t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.machhun t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.macurn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.machhurn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.mulsn t4,t2,t0,-43'
> +.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-531'
> +.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-4454'
> +.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-32'
> +.*: Error: illegal operands `cv.mulun t4,t2,t0,-23'
> +.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-459'
> +.*: Error: illegal operands `cv.mulurn t4,t2,t0,-549'
> +.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-32'
> +.*: Error: illegal operands `cv.macsn t4,t2,t0,-223'
> +.*: Error: illegal operands `cv.machhsn t4,t2,t0,-56'
> +.*: Error: illegal operands `cv.macsrn t4,t2,t0,-8'
> +.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-2'
> +.*: Error: illegal operands `cv.macun t4,t2,t0,-432'
> +.*: Error: illegal operands `cv.machhun t4,t2,t0,-1245'
> +.*: Error: illegal operands `cv.macurn t4,t2,t0,-45'
> +.*: Error: illegal operands `cv.machhurn t4,t2,t0,-354'
> +.*: Error: illegal operands `cv.mulsn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulsrn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulun t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulhhun t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulurn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.macsn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.machhsn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.macsrn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.machhsrn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.macun t4,t2,t0,32'
> +.*: Error: illegal operands `cv.machhun t4,t2,t0,32'
> +.*: Error: illegal operands `cv.macurn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.machhurn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.mulsn t4,t2,t0,325'
> +.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,531'
> +.*: Error: illegal operands `cv.mulsrn t4,t2,t0,4454'
> +.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,254'
> +.*: Error: illegal operands `cv.mulun t4,t2,t0,76'
> +.*: Error: illegal operands `cv.mulhhun t4,t2,t0,459'
> +.*: Error: illegal operands `cv.mulurn t4,t2,t0,549'
> +.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,5364'
> +.*: Error: illegal operands `cv.macsn t4,t2,t0,34435'
> +.*: Error: illegal operands `cv.machhsn t4,t2,t0,56'
> +.*: Error: illegal operands `cv.macsrn t4,t2,t0,3423'
> +.*: Error: illegal operands `cv.machhsrn t4,t2,t0,365'
> +.*: Error: illegal operands `cv.macun t4,t2,t0,432'
> +.*: Error: illegal operands `cv.machhun t4,t2,t0,1245'
> +.*: Error: illegal operands `cv.macurn t4,t2,t0,45'
> +.*: Error: instruction cv.mulsn requires absolute expression
> +.*: Error: instruction cv.mulhhsn requires absolute expression
> +.*: Error: instruction cv.mulsrn requires absolute expression
> +.*: Error: instruction cv.mulhhsrn requires absolute expression
> +.*: Error: instruction cv.mulun requires absolute expression
> +.*: Error: instruction cv.mulhhun requires absolute expression
> +.*: Error: instruction cv.mulurn requires absolute expression
> +.*: Error: instruction cv.mulhhurn requires absolute expression
> +.*: Error: instruction cv.macsn requires absolute expression
> +.*: Error: instruction cv.machhsn requires absolute expression
> +.*: Error: instruction cv.macsrn requires absolute expression
> +.*: Error: instruction cv.machhsrn requires absolute expression
> +.*: Error: instruction cv.macun requires absolute expression
> +.*: Error: instruction cv.machhun requires absolute expression
> +.*: Error: instruction cv.macurn requires absolute expression
> +.*: Error: instruction cv.machhurn requires absolute expression
> +.*: Error: illegal operands `cv.machhurn t4,t2,t0,354'
> diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> new file mode 100644
> index 00000000000..97a29448ebd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> @@ -0,0 +1,156 @@
> +# Destination must be of type register
> +target:
> + cv.mac 8, t2, t0
> + cv.msu 23, t2, t0
> + cv.muls 43, t2, t0
> + cv.mulhhs 7, t2, t0
> + cv.mulsn 345, t2, t0, 4
> + cv.mulhhsn 356, t2, t0, 16
> + cv.mulsrn 867, t2, t0, 10
> + cv.mulhhsrn 3454, t2, t0, 17
> + cv.mulu 9, t2, t0
> + cv.mulhhu 54, t2, t0
> + cv.mulun 965, t2, t0, 7
> + cv.mulhhun 35, t2, t0, 16
> + cv.mulurn 87, t2, t0, 11
> + cv.mulhhurn 38, t2, t0, 9
> + cv.macsn 985, t2, t0, 24
> + cv.machhsn 83, t2, t0, 11
> + cv.macsrn 960, t2, t0, 9
> + cv.machhsrn 385, t2, t0, 24
> + cv.macun 58, t2, t0, 27
> + cv.machhun 6, t2, t0, 18
> + cv.macurn 35, t2, t0, 25
> + cv.machhurn 67, t2, t0, 5
> +
> +# Source one must be of type register
> + cv.mac t4, 43, t0
> + cv.msu t4, 3, t0
> + cv.muls t4, 345, t0
> + cv.mulhhs t4, 54, t0
> + cv.mulsn t4, 4, t0, 4
> + cv.mulhhsn t4, 35, t0, 16
> + cv.mulsrn t4, 53, t0, 10
> + cv.mulhhsrn t4, 4456, t0, 17
> + cv.mulu t4, 868, t0
> + cv.mulhhu t4, 95, t0
> + cv.mulun t4, 584, t0, 7
> + cv.mulhhun t4, 37545, t0, 16
> + cv.mulurn t4, 943, t0, 11
> + cv.mulhhurn t4, 34, t0, 9
> + cv.macsn t4, 93, t0, 24
> + cv.machhsn t4, 584, t0, 11
> + cv.macsrn t4, 28, t0, 9
> + cv.machhsrn t4, 9, t0, 24
> + cv.macun t4, 834, t0, 27
> + cv.machhun t4, 92, t0, 18
> + cv.macurn t4, 49, t0, 25
> + cv.machhurn t4, 6, t0, 5
> +
> +# Source two must be of type register
> + cv.mac t4, t2, 344
> + cv.msu t4, t2, 23
> + cv.muls t4, t2, 2
> + cv.mulhhs t4, t2, 8
> + cv.mulsn t4, t2, 45, 4
> + cv.mulhhsn t4, t2, 655, 16
> + cv.mulsrn t4, t2, 465, 10
> + cv.mulhhsrn t4, t2, 3534, 17
> + cv.mulu t4, t2, 46
> + cv.mulhhu t4, t2, 35
> + cv.mulun t4, t2, 67, 7
> + cv.mulhhun t4, t2, 6, 16
> + cv.mulurn t4, t2, 787, 11
> + cv.mulhhurn t4, t2, 3545, 9
> + cv.macsn t4, t2, 6, 24
> + cv.machhsn t4, t2, 765, 11
> + cv.macsrn t4, t2, 45, 9
> + cv.machhsrn t4, t2, 7, 24
> + cv.macun t4, t2, 98, 27
> + cv.machhun t4, t2, 654, 18
> + cv.macurn t4, t2, 900, 25
> + cv.machhurn t4, t2, 354, 5
> +
> +# Immediate value must be in range [0, 31]
> + cv.mulsn t4, t2, t0, -1
> + cv.mulhhsn t4, t2, t0, -1
> + cv.mulsrn t4, t2, t0, -1
> + cv.mulhhsrn t4, t2, t0, -1
> + cv.mulun t4, t2, t0, -1
> + cv.mulhhun t4, t2, t0, -1
> + cv.mulurn t4, t2, t0, -1
> + cv.mulhhurn t4, t2, t0, -1
> + cv.macsn t4, t2, t0, -1
> + cv.machhsn t4, t2, t0, -1
> + cv.macsrn t4, t2, t0, -1
> + cv.machhsrn t4, t2, t0, -1
> + cv.macun t4, t2, t0, -1
> + cv.machhun t4, t2, t0, -1
> + cv.macurn t4, t2, t0, -1
> + cv.machhurn t4, t2, t0, -1
> + cv.mulsn t4, t2, t0, -43
> + cv.mulhhsn t4, t2, t0, -531
> + cv.mulsrn t4, t2, t0, -4454
> + cv.mulhhsrn t4, t2, t0, -32
> + cv.mulun t4, t2, t0, -23
> + cv.mulhhun t4, t2, t0, -459
> + cv.mulurn t4, t2, t0, -549
> + cv.mulhhurn t4, t2, t0, -32
> + cv.macsn t4, t2, t0, -223
> + cv.machhsn t4, t2, t0, -56
> + cv.macsrn t4, t2, t0, -8
> + cv.machhsrn t4, t2, t0, -2
> + cv.macun t4, t2, t0, -432
> + cv.machhun t4, t2, t0, -1245
> + cv.macurn t4, t2, t0, -45
> + cv.machhurn t4, t2, t0, -354
> + cv.mulsn t4, t2, t0, 32
> + cv.mulhhsn t4, t2, t0, 32
> + cv.mulsrn t4, t2, t0, 32
> + cv.mulhhsrn t4, t2, t0, 32
> + cv.mulun t4, t2, t0, 32
> + cv.mulhhun t4, t2, t0, 32
> + cv.mulurn t4, t2, t0, 32
> + cv.mulhhurn t4, t2, t0, 32
> + cv.macsn t4, t2, t0, 32
> + cv.machhsn t4, t2, t0, 32
> + cv.macsrn t4, t2, t0, 32
> + cv.machhsrn t4, t2, t0, 32
> + cv.macun t4, t2, t0, 32
> + cv.machhun t4, t2, t0, 32
> + cv.macurn t4, t2, t0, 32
> + cv.machhurn t4, t2, t0, 32
> + cv.mulsn t4, t2, t0, 325
> + cv.mulhhsn t4, t2, t0, 531
> + cv.mulsrn t4, t2, t0, 4454
> + cv.mulhhsrn t4, t2, t0, 254
> + cv.mulun t4, t2, t0, 76
> + cv.mulhhun t4, t2, t0, 459
> + cv.mulurn t4, t2, t0, 549
> + cv.mulhhurn t4, t2, t0, 5364
> + cv.macsn t4, t2, t0, 34435
> + cv.machhsn t4, t2, t0, 56
> + cv.macsrn t4, t2, t0, 3423
> + cv.machhsrn t4, t2, t0, 365
> + cv.macun t4, t2, t0, 432
> + cv.machhun t4, t2, t0, 1245
> + cv.macurn t4, t2, t0, 45
> +
> +# Immediate value must be an absolute expression
> + cv.mulsn t4, t2, t0, t3
> + cv.mulhhsn t4, t2, t0, t1
> + cv.mulsrn t4, t2, t0, t6
> + cv.mulhhsrn t4, t2, t0, t3
> + cv.mulun t4, t2, t0, t1
> + cv.mulhhun t4, t2, t0, t3
> + cv.mulurn t4, t2, t0, t5
> + cv.mulhhurn t4, t2, t0, t1
> + cv.macsn t4, t2, t0, t3
> + cv.machhsn t4, t2, t0, t5
> + cv.macsrn t4, t2, t0, t1
> + cv.machhsrn t4, t2, t0, t6
> + cv.macun t4, t2, t0, t1
> + cv.machhun t4, t2, t0, t3
> + cv.macurn t4, t2, t0, t6
> + cv.machhurn t4, t2, t0, t5
> + cv.machhurn t4, t2, t0, 354
> diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.d
> b/gas/testsuite/gas/riscv/cv-mac-insns.d
> new file mode 100644
> index 00000000000..9a961051a97
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-insns.d
> @@ -0,0 +1,87 @@
> +#as: -march=rv32i_xcvmac
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+0:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
> +[ ]+4:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
> +[ ]+8:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
> +[ ]+c:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
> +[ ]+10:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
> +[ ]+14:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
> +[ ]+18:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
> +[ ]+1c:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
> +[ ]+20:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
> +[ ]+24:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
> +[ ]+28:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
> +[ ]+2c:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
> +[ ]+30:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
> +[ ]+34:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
> +[ ]+38:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
> +[ ]+3c:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
> +[ ]+40:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
> +[ ]+44:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
> +[ ]+48:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
> +[ ]+4c:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
> +[ ]+50:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
> +[ ]+54:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
> +[ ]+58:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
> +[ ]+5c:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
> +[ ]+60:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
> +[ ]+64:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
> +[ ]+68:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
> +[ ]+6c:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
> +[ ]+70:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
> +[ ]+74:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
> +[ ]+78:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
> +[ ]+7c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
> +[ ]+80:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
> +[ ]+84:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
> +[ ]+88:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
> +[ ]+8c:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
> +[ ]+90:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
> +[ ]+94:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
> +[ ]+98:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
> +[ ]+9c:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
> +[ ]+a0:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
> +[ ]+a4:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
> +[ ]+a8:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
> +[ ]+ac:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
> +[ ]+b0:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
> +[ ]+b4:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
> +[ ]+b8:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
> +[ ]+bc:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
> +[ ]+c0:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
> +[ ]+c4:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
> +[ ]+c8:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
> +[ ]+cc:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
> +[ ]+d0:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
> +[ ]+d4:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
> +[ ]+d8:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
> +[ ]+dc:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
> +[ ]+e0:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
> +[ ]+e4:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
> +[ ]+e8:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
> +[ ]+ec:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
> +[ ]+f0:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
> +[ ]+f4:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
> +[ ]+f8:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
> +[ ]+fc:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
> +[ ]+100:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
> +[ ]+104:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
> +[ ]+108:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
> +[ ]+10c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
> +[ ]+110:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
> +[ ]+114:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
> +[ ]+118:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
> +[ ]+11c:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
> +[ ]+120:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
> +[ ]+124:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
> +[ ]+128:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
> +[ ]+12c:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
> +[ ]+130:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
> +[ ]+134:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
> diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.s
> b/gas/testsuite/gas/riscv/cv-mac-insns.s
> new file mode 100644
> index 00000000000..a699a3ba461
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-mac-insns.s
> @@ -0,0 +1,81 @@
> +target:
> + cv.mac t0, t1, t2
> + cv.mac t4, t2, t0
> + cv.mac t3, t5, t1
> + cv.machhsn t0, t1, t2, 0
> + cv.machhsn t4, t2, t0, 11
> + cv.machhsn t3, t5, t1, 31
> + cv.machhsrn t0, t1, t2, 0
> + cv.machhsrn t4, t2, t0, 24
> + cv.machhsrn t3, t5, t1, 31
> + cv.machhun t0, t1, t2, 0
> + cv.machhun t4, t2, t0, 18
> + cv.machhun t3, t5, t1, 31
> + cv.machhurn t0, t1, t2, 0
> + cv.machhurn t4, t2, t0, 5
> + cv.machhurn t3, t5, t1, 31
> + cv.macsn t0, t1, t2, 0
> + cv.macsn t4, t2, t0, 24
> + cv.macsn t3, t5, t1, 31
> + cv.macsrn t0, t1, t2, 0
> + cv.macsrn t4, t2, t0, 9
> + cv.macsrn t3, t5, t1, 31
> + cv.macun t0, t1, t2, 0
> + cv.macun t4, t2, t0, 27
> + cv.macun t3, t5, t1, 31
> + cv.macurn t0, t1, t2, 0
> + cv.macurn t4, t2, t0, 25
> + cv.macurn t3, t5, t1, 31
> + cv.msu t0, t1, t2
> + cv.msu t4, t2, t0
> + cv.msu t3, t5, t1
> + cv.mulhhs t0, t1, t2
> + cv.mulhhs t4, t2, t0
> + cv.mulhhs t3, t5, t1
> + cv.mulhhsn t0, t1, t2, 0
> + cv.mulhhsn t4, t2, t0, 16
> + cv.mulhhsn t3, t5, t1, 31
> + cv.mulhhsrn t0, t1, t2, 0
> + cv.mulhhsrn t4, t2, t0, 17
> + cv.mulhhsrn t3, t5, t1, 31
> + cv.mulhhu t0, t1, t2
> + cv.mulhhu t4, t2, t0
> + cv.mulhhu t3, t5, t1
> + cv.mulhhun t0, t1, t2, 0
> + cv.mulhhun t4, t2, t0, 16
> + cv.mulhhun t3, t5, t1, 31
> + cv.mulhhurn t0, t1, t2, 0
> + cv.mulhhurn t4, t2, t0, 9
> + cv.mulhhurn t3, t5, t1, 31
> + cv.muls t0, t1, t2
> + cv.muls t4, t2, t0
> + cv.muls t3, t5, t1
> + cv.mulsn t0, t1, t2, 0
> + cv.mulsn t4, t2, t0, 4
> + cv.mulsn t3, t5, t1, 31
> + cv.mulsrn t0, t1, t2, 0
> + cv.mulsrn t4, t2, t0, 10
> + cv.mulsrn t3, t5, t1, 31
> + cv.mulu t0, t1, t2
> + cv.mulu t4, t2, t0
> + cv.mulu t3, t5, t1
> + cv.mulun t0, t1, t2, 0
> + cv.mulun t4, t2, t0, 7
> + cv.mulun t3, t5, t1, 31
> + cv.mulurn t0, t1, t2, 0
> + cv.mulurn t4, t2, t0, 11
> + cv.mulurn t3, t5, t1, 31
> +
> + # Pseudo-instructions
> + cv.mulhhsn t0, t1, t2, 0
> + cv.mulhhsn t4, t2, t0, 0
> + cv.mulhhsn t3, t5, t1, 0
> + cv.mulhhun t0, t1, t2, 0
> + cv.mulhhun t4, t2, t0, 0
> + cv.mulhhun t3, t5, t1, 0
> + cv.mulsn t0, t1, t2, 0
> + cv.mulsn t4, t2, t0, 0
> + cv.mulsn t3, t5, t1, 0
> + cv.mulun t0, t1, t2, 0
> + cv.mulun t4, t2, t0, 0
> + cv.mulun t3, t5, t1, 0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 26d2c04bf24..199ae63585f 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2320,6 +2320,27 @@
> #define MASK_WRS_NTO 0xffffffff
> #define MATCH_WRS_STO 0x01d00073
> #define MASK_WRS_STO 0xffffffff
> +/* Vendor-specific (CORE-V) Xcvmac instructions. */
> +#define MATCH_CV_MAC 0x9000302b
> +#define MATCH_CV_MSU 0x9200302b
> +#define MASK_CV_MACMSU 0xfe00707f
> +#define MATCH_CV_MULSN 0x405b
> +#define MATCH_CV_MULHHSN 0x4000405b
> +#define MATCH_CV_MULSRN 0x8000405b
> +#define MATCH_CV_MULHHSRN 0xc000405b
> +#define MATCH_CV_MULUN 0x505b
> +#define MATCH_CV_MULHHUN 0x4000505b
> +#define MATCH_CV_MULURN 0x8000505b
> +#define MATCH_CV_MULHHURN 0xc000505b
> +#define MATCH_CV_MACSN 0x605b
> +#define MATCH_CV_MACHHSN 0x4000605b
> +#define MATCH_CV_MACSRN 0x8000605b
> +#define MATCH_CV_MACHHSRN 0xc000605b
> +#define MATCH_CV_MACUN 0x705b
> +#define MATCH_CV_MACHHUN 0x4000705b
> +#define MATCH_CV_MACURN 0x8000705b
> +#define MATCH_CV_MACHHURN 0xc000705b
> +#define MASK_CV_MULMACN 0xc000707f
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> #define MATCH_TH_ADDSL 0x0000100b
> #define MASK_TH_ADDSL 0xf800707f
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 38927bd0c74..5097d2cf6c1 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -112,6 +112,9 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
> #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
> (RV_X(x, 5, 1) << 1)
> +/* Vendor-specific (CORE-V) extract macros. */
> +#define EXTRACT_CV_IS3_UIMM5(x) \
> + (RV_X(x, 25, 5))
>
> #define ENCODE_ITYPE_IMM(x) \
> (RV_X(x, 0, 12) << 20)
> @@ -163,6 +166,9 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
> #define ENCODE_ZCB_HALFWORD_UIMM(x) \
> (RV_X(x, 1, 1) << 5)
> +/* Vendor-specific (CORE-V) encode macros. */
> +#define ENCODE_CV_IS3_UIMM5(x) \
> + (RV_X(x, 0, 5) << 25)
>
> #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
> #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
> @@ -443,6 +449,7 @@ enum riscv_insn_class
> INSN_CLASS_ZICBOP,
> INSN_CLASS_ZICBOZ,
> INSN_CLASS_H,
> + INSN_CLASS_XCVMAC,
> INSN_CLASS_XTHEADBA,
> INSN_CLASS_XTHEADBB,
> INSN_CLASS_XTHEADBS,
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 90f0fea1692..b16db5113b1 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -429,6 +429,22 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma
> pc, disassemble_info *info
> print (info->stream, dis_style_immediate, "0");
> break;
>
> + case 'x': /* Vendor-specific operands. */
>
Likewise, use `X'.
> + switch (*++oparg)
> + {
> + /* Vendor-specific (CORE-V) operands. */
> + case 'c':
> + switch (*++oparg)
> + {
> + case '3':
> + print (info->stream, dis_style_immediate, "%d",
> + ((int) EXTRACT_CV_IS3_UIMM5 (l)));
> + break;
> + }
> + break;
> + }
> + break;
> +
> case 's':
> if ((l & MASK_JALR) == MATCH_JALR)
> maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 39da5f84e74..1b2023b96bd 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -154,6 +154,8 @@ const float riscv_fli_numval[32] =
> #define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
> #define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
> #define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
> +/* Vendor-specific (CORE-V) masks. */
> +#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)
>
> static int
> match_opcode (const struct riscv_opcode *op, insn_t insn)
> @@ -2039,6 +2041,30 @@ const struct riscv_opcode riscv_opcodes[] =
> {"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W,
> match_opcode, INSN_DREF|INSN_4_BYTE },
> {"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D,
> match_opcode, INSN_DREF|INSN_8_BYTE },
>
> +/* Vendor-specific (CORE-V) Xcvmac instructions. */
>
Instructions are named starting with "cv." looks reasonable and good.
> +{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC,
> MASK_CV_MACMSU, match_opcode, 0},
> +{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU,
> MASK_CV_MACMSU, match_opcode, 0},
> +{"cv.mulsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULSN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.muls", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULSN,
> MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
> +{"cv.mulsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULSRN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulhhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHSN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulhhs", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHSN,
> MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
> +{"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHSRN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULUN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULUN,
> MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
> +{"cv.mulurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULURN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulhhun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHUN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.mulhhu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHUN,
> MASK_CV_MULMACN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
> +{"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MULHHURN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.macsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACSN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.machhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHSN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.macsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACSRN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHSRN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.macun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACUN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.machhun", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHUN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACURN,
> MASK_CV_MULMACN, match_opcode, 0},
> +{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHURN,
> MASK_CV_MULMACN, match_opcode, 0},
> +
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25",
> MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P
2023-09-05 14:53 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
@ 2023-09-07 4:37 ` Nelson Chu
0 siblings, 0 replies; 16+ messages in thread
From: Nelson Chu @ 2023-09-07 4:37 UTC (permalink / raw)
To: Mary Bennett; +Cc: binutils
[-- Attachment #1: Type: text/plain, Size: 56020 bytes --]
Okay, except using X to replace x for vendor core-v operands, otherwise
looks good.
Thanks
Nelson
On Tue, Sep 5, 2023 at 10:54 PM Mary Bennett <mary.bennett@embecosm.com>
wrote:
> Spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
> instruction class.
> (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (validate_riscv_insn): Added the necessary
> operands for the extension.
> (riscv_ip): Likewise.
> * doc/c-riscv.texi: Noted XCValu as an additional ISA extension
> for CORE-V.
> * testsuite/gas/riscv/cv-alu-boundaries.d: New test.
> * testsuite/gas/riscv/cv-alu-boundaries.l: New test.
> * testsuite/gas/riscv/cv-alu-boundaries.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-march.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-march.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-march.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
> * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
> * testsuite/gas/riscv/cv-alu-insns.d: New test.
> * testsuite/gas/riscv/cv-alu-insns.s: New test.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (print_insn_args): Disassemble xcb operand.
> * riscv-opc.c: Defined the MASK and added XCValu instructions.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
> for XCValu.
> * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
> for XCValu.
> (enum riscv_insn_class): Added the XCValu instruction class.
> ---
> bfd/elfxx-riscv.c | 5 +
> gas/config/tc-riscv.c | 17 ++-
> gas/doc/c-riscv.texi | 5 +
> gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 ++++
> gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 +++++
> gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 +++++
> .../gas/riscv/cv-alu-fail-operand-01.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-01.l | 32 +++++
> .../gas/riscv/cv-alu-fail-operand-01.s | 33 +++++
> .../gas/riscv/cv-alu-fail-operand-02.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-02.l | 32 +++++
> .../gas/riscv/cv-alu-fail-operand-02.s | 33 +++++
> .../gas/riscv/cv-alu-fail-operand-03.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-03.l | 25 ++++
> .../gas/riscv/cv-alu-fail-operand-03.s | 26 ++++
> .../gas/riscv/cv-alu-fail-operand-04.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.l | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.s | 4 +
> .../gas/riscv/cv-alu-fail-operand-05.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-05.l | 9 ++
> .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-06.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-06.l | 9 ++
> .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-07.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-07.l | 33 +++++
> .../gas/riscv/cv-alu-fail-operand-07.s | 34 +++++
> gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++++
> gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++++++
> include/opcode/riscv-opc.h | 35 +++++
> include/opcode/riscv.h | 5 +
> opcodes/riscv-dis.c | 24 ++--
> opcodes/riscv-opc.c | 35 +++++
> 36 files changed, 767 insertions(+), 11 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index a3c32941866..411f9976ffe 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1349,6 +1349,7 @@ static struct riscv_supported_ext
> riscv_supported_vendor_x_ext[] =
> {
> /* CORE-V ISA extension spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> */
> {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2543,6 +2544,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> return riscv_subset_supports (rps, "h");
> case INSN_CLASS_XCVMAC:
> return riscv_subset_supports (rps, "xcvmac");
> + case INSN_CLASS_XCVALU:
> + return riscv_subset_supports (rps, "xcvalu");
> case INSN_CLASS_XTHEADBA:
> return riscv_subset_supports (rps, "xtheadba");
> case INSN_CLASS_XTHEADBB:
> @@ -2785,6 +2788,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return _("h");
> case INSN_CLASS_XCVMAC:
> return "xcvmac";
> + case INSN_CLASS_XCVALU:
> + return "xcvalu";
> case INSN_CLASS_XTHEADBA:
> return "xtheadba";
> case INSN_CLASS_XTHEADBB:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 3100a2e135f..4c201e02b80 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1477,7 +1477,12 @@ validate_riscv_insn (const struct riscv_opcode
> *opc, int length)
> case 'c':
> switch (*++oparg)
> {
> + case '2':
> + /* ls2[4:0] */
> + used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
> + break;
> case '3':
> + /* ls3[4:0] */
> used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
> break;
> default:
> @@ -3695,6 +3700,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> case 'c':
> switch (*++oparg)
> {
> + case '2':
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + asarg = expr_parse_end;
> + if (imm_expr->X_add_number<0
> + || imm_expr->X_add_number>31)
> + break;
> + ip->insn_opcode
> + |= ENCODE_CV_IS2_UIMM5
> (imm_expr->X_add_number);
> + continue;
> case '3':
> my_getExpression (imm_expr, asarg);
> check_absolute_expr (ip, imm_expr, FALSE);
> @@ -3712,7 +3727,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> default:
> goto unknown_riscv_ip_operand;
> }
> - break;
> + break;
>
> default:
> unknown_riscv_ip_operand:
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 1dcdeeb7b36..61e744ae633 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -750,6 +750,11 @@ The Xcvmac extension provides instructions for
> multiply-accumulate operations.
>
> It is documented in @url{
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> }
>
> +@item Xcvalu
> +The Xcvalu extension provides instructions for general ALU operations.
> +
> +It is documented in @url{
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> }
> +
> @item XTheadBa
> The XTheadBa extension provides instructions for address calculations.
>
> diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d
> b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
> new file mode 100644
> index 00000000000..907b043aebc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-boundaries.s
> +#error_output: cv-alu-boundaries.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l
> b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
> new file mode 100644
> index 00000000000..fae4022244c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
> @@ -0,0 +1,14 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.subnr 10,t3,t6'
> +.*: Error: illegal operands `cv.addrnr t4,26,t6'
> +.*: Error: illegal operands `cv.subunr t6,t3,15'
> +.*: Error: instruction cv.clipu requires absolute expression
> +.*: Error: instruction cv.addn requires absolute expression
> +.*: Error: illegal operands `cv.clipu t0,t3,-10'
> +.*: Error: illegal operands `cv.clipu t0,t3,500'
> +.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
> +.*: Error: illegal operands `cv.addn t0,t3,t6,302'
> +.*: Error: illegal operands `cv.clipu t0,t3,-1'
> +.*: Error: illegal operands `cv.clipu t0,t3,32'
> +.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
> +.*: Error: illegal operands `cv.addn t0,t3,t6,32'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s
> b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
> new file mode 100644
> index 00000000000..bb4da949b4a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
> @@ -0,0 +1,27 @@
> +# Destination must be of type register
> +target:
> + cv.subnr 10, t3, t6
> +# Source 1 must be of type register
> + cv.addrnr t4, 26, t6
> +# Source 2 must be of type register
> + cv.subunr t6, t3, 15
> +# Five bit immediate must be an absolute value
> + cv.clipu t0, t3, t6
> +# Five bit immediate must be an absolute value
> + cv.addn t0, t3, t6, t2
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.clipu t0, t3, -10
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.clipu t0, t3, 500
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.addn t0, t3, t6, -60
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.addn t0, t3, t6, 302
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.clipu t0, t3, -1
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.clipu t0, t3, 32
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.addn t0, t3, t6, -1
> +# Five bit immediate must be an absolute value in range [0, 31]
> + cv.addn t0, t3, t6, 32
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
> new file mode 100644
> index 00000000000..963aa4012da
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: cv-alu-fail-march.s
> +#error_output: cv-alu-fail-march.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
> new file mode 100644
> index 00000000000..11e5a7cd279
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
> @@ -0,0 +1,32 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
> +.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension
> `xcvalu' required
> +.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu'
> required
> +.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu'
> required
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
> new file mode 100644
> index 00000000000..8dd39b7301f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
> @@ -0,0 +1,33 @@
> +# Absence of xcv or xcvalu march option disables all CORE-V general ALU
> ops extensions
> +target:
> + cv.abs t4,t2
> + cv.slet t4,t2,t6
> + cv.sletu t4,t2,t6
> + cv.min t4,t2,t6
> + cv.minu t4,t2,t6
> + cv.max t4,t2,t6
> + cv.maxu t4,t2,t6
> + cv.exths t4,t2
> + cv.exthz t4,t2
> + cv.extbs t4,t2
> + cv.extbz t4,t2
> + cv.clip t4,t2,5
> + cv.clipu t4,t2,5
> + cv.clipr t4,t2,t6
> + cv.clipur t4,t2,t6
> + cv.addn t4, t2, t0, 4
> + cv.addun t4, t2, t0, 4
> + cv.addrn t6, t0, t3, 9
> + cv.addurn t6, t0, t3, 14
> + cv.addnr t6, t0, t3
> + cv.addunr t6, t0, t3
> + cv.addrnr t6, t0, t3
> + cv.addurnr t6, t0, t3
> + cv.subn t6, t0, t3, 6
> + cv.subun t6, t0, t3, 24
> + cv.subrn t6, t0, t3, 21
> + cv.suburn t6, t0, t3, 3
> + cv.subnr t6, t0, t3
> + cv.subunr t6, t0, t3
> + cv.subrnr t6, t0, t3
> + cv.suburnr t6, t0, t3
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> new file mode 100644
> index 00000000000..81b17348c32
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-01.s
> +#error_output: cv-alu-fail-operand-01.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> new file mode 100644
> index 00000000000..f670e4341fa
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> @@ -0,0 +1,32 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.abs 5,t2'
> +.*: Error: illegal operands `cv.slet 10,t2,t6'
> +.*: Error: illegal operands `cv.sletu 11,t2,t6'
> +.*: Error: illegal operands `cv.min 15,t2,t6'
> +.*: Error: illegal operands `cv.minu 16,t2,t6'
> +.*: Error: illegal operands `cv.max 8,t2,t6'
> +.*: Error: illegal operands `cv.maxu 3,t2,t6'
> +.*: Error: illegal operands `cv.exths 2,t2'
> +.*: Error: illegal operands `cv.exthz 6,t2'
> +.*: Error: illegal operands `cv.extbs 4,t2'
> +.*: Error: illegal operands `cv.extbz 7,t2'
> +.*: Error: illegal operands `cv.clip 17,t2,5'
> +.*: Error: illegal operands `cv.clipu 11,t2,5'
> +.*: Error: illegal operands `cv.clipr 16,t2,t6'
> +.*: Error: illegal operands `cv.clipur 15,t2,t6'
> +.*: Error: illegal operands `cv.addn 9,t2,t0,4'
> +.*: Error: illegal operands `cv.addun 30,t2,t0,4'
> +.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
> +.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
> +.*: Error: illegal operands `cv.addnr 2,t0,t3'
> +.*: Error: illegal operands `cv.addunr 26,t0,t3'
> +.*: Error: illegal operands `cv.addrnr 3,t0,t3'
> +.*: Error: illegal operands `cv.addurnr 14,t0,t3'
> +.*: Error: illegal operands `cv.subn 15,t0,t3,6'
> +.*: Error: illegal operands `cv.subun 9,t0,t3,24'
> +.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
> +.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
> +.*: Error: illegal operands `cv.subnr 3,t0,t3'
> +.*: Error: illegal operands `cv.subunr 12,t0,t3'
> +.*: Error: illegal operands `cv.subrnr 13,t0,t3'
> +.*: Error: illegal operands `cv.suburnr 8,t0,t3'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> new file mode 100644
> index 00000000000..7920ebd53ec
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> @@ -0,0 +1,33 @@
> +# Destination must be of type register
> +target:
> + cv.abs 5,t2
> + cv.slet 10,t2,t6
> + cv.sletu 11,t2,t6
> + cv.min 15,t2,t6
> + cv.minu 16,t2,t6
> + cv.max 8,t2,t6
> + cv.maxu 3,t2,t6
> + cv.exths 2,t2
> + cv.exthz 6,t2
> + cv.extbs 4,t2
> + cv.extbz 7,t2
> + cv.clip 17,t2,5
> + cv.clipu 11,t2,5
> + cv.clipr 16,t2,t6
> + cv.clipur 15,t2,t6
> + cv.addn 9,t2,t0,4
> + cv.addun 30,t2,t0,4
> + cv.addrn 21,t0,t3,9
> + cv.addurn 6,t0,t3,14
> + cv.addnr 2,t0,t3
> + cv.addunr 26,t0,t3
> + cv.addrnr 3,t0,t3
> + cv.addurnr 14,t0,t3
> + cv.subn 15,t0,t3,6
> + cv.subun 9,t0,t3,24
> + cv.subrn 24,t0,t3,21
> + cv.suburn 25,t0,t3,3
> + cv.subnr 3,t0,t3
> + cv.subunr 12,t0,t3
> + cv.subrnr 13,t0,t3
> + cv.suburnr 8,t0,t3
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> new file mode 100644
> index 00000000000..46645aaf864
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-02.s
> +#error_output: cv-alu-fail-operand-02.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> new file mode 100644
> index 00000000000..0a888c7251b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> @@ -0,0 +1,32 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.abs t4,5'
> +.*: Error: illegal operands `cv.slet t4,7,t6'
> +.*: Error: illegal operands `cv.sletu t4,3,t6'
> +.*: Error: illegal operands `cv.min t4,5,t6'
> +.*: Error: illegal operands `cv.minu t4,3,t6'
> +.*: Error: illegal operands `cv.max t4,4,t6'
> +.*: Error: illegal operands `cv.maxu t4,6,t6'
> +.*: Error: illegal operands `cv.exths t4,30'
> +.*: Error: illegal operands `cv.exthz t4,23'
> +.*: Error: illegal operands `cv.extbs t4,25'
> +.*: Error: illegal operands `cv.extbz t4,21'
> +.*: Error: illegal operands `cv.clip t4,2,5'
> +.*: Error: illegal operands `cv.clipu t4,16,5'
> +.*: Error: illegal operands `cv.clipr t4,17,t6'
> +.*: Error: illegal operands `cv.clipur t4,14,t6'
> +.*: Error: illegal operands `cv.addn t4,5,t0,4'
> +.*: Error: illegal operands `cv.addun t4,18,t0,4'
> +.*: Error: illegal operands `cv.addrn t6,19,t3,9'
> +.*: Error: illegal operands `cv.addurn t6,4,t3,14'
> +.*: Error: illegal operands `cv.addnr t6,6,t3'
> +.*: Error: illegal operands `cv.addunr t6,7,t3'
> +.*: Error: illegal operands `cv.addrnr t6,9,t3'
> +.*: Error: illegal operands `cv.addurnr t6,5,t3'
> +.*: Error: illegal operands `cv.subn t6,11,t3,6'
> +.*: Error: illegal operands `cv.subun t6,14,t3,24'
> +.*: Error: illegal operands `cv.subrn t6,15,t3,21'
> +.*: Error: illegal operands `cv.suburn t6,24,t3,3'
> +.*: Error: illegal operands `cv.subnr t6,4,t3'
> +.*: Error: illegal operands `cv.subunr t6,8,t3'
> +.*: Error: illegal operands `cv.subrnr t6,7,t3'
> +.*: Error: illegal operands `cv.suburnr t6,6,t3'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> new file mode 100644
> index 00000000000..6083f1f5044
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> @@ -0,0 +1,33 @@
> +# Source 1 must be of type register
> +target:
> + cv.abs t4,5
> + cv.slet t4,7,t6
> + cv.sletu t4,3,t6
> + cv.min t4,5,t6
> + cv.minu t4,3,t6
> + cv.max t4,4,t6
> + cv.maxu t4,6,t6
> + cv.exths t4,30
> + cv.exthz t4,23
> + cv.extbs t4,25
> + cv.extbz t4,21
> + cv.clip t4,2,5
> + cv.clipu t4,16,5
> + cv.clipr t4,17,t6
> + cv.clipur t4,14,t6
> + cv.addn t4,5,t0,4
> + cv.addun t4,18,t0,4
> + cv.addrn t6,19,t3,9
> + cv.addurn t6,4,t3,14
> + cv.addnr t6,6,t3
> + cv.addunr t6,7,t3
> + cv.addrnr t6,9,t3
> + cv.addurnr t6,5,t3
> + cv.subn t6,11,t3,6
> + cv.subun t6,14,t3,24
> + cv.subrn t6,15,t3,21
> + cv.suburn t6,24,t3,3
> + cv.subnr t6,4,t3
> + cv.subunr t6,8,t3
> + cv.subrnr t6,7,t3
> + cv.suburnr t6,6,t3
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> new file mode 100644
> index 00000000000..6f681289d12
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-03.s
> +#error_output: cv-alu-fail-operand-03.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> new file mode 100644
> index 00000000000..c7a11184996
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> @@ -0,0 +1,25 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.slet t4,t2,3'
> +.*: Error: illegal operands `cv.sletu t4,t2,4'
> +.*: Error: illegal operands `cv.min t4,t2,13'
> +.*: Error: illegal operands `cv.minu t4,t2,7'
> +.*: Error: illegal operands `cv.max t4,t2,17'
> +.*: Error: illegal operands `cv.maxu t4,t2,30'
> +.*: Error: illegal operands `cv.clipr t4,t2,18'
> +.*: Error: illegal operands `cv.clipur t4,t2,29'
> +.*: Error: illegal operands `cv.addn t4,t2,24,4'
> +.*: Error: illegal operands `cv.addun t4,t2,6,4'
> +.*: Error: illegal operands `cv.addrn t6,t0,7,9'
> +.*: Error: illegal operands `cv.addurn t6,t0,18,14'
> +.*: Error: illegal operands `cv.addnr t6,t0,15'
> +.*: Error: illegal operands `cv.addunr t6,t0,24'
> +.*: Error: illegal operands `cv.addrnr t6,t0,3'
> +.*: Error: illegal operands `cv.addurnr t6,t0,2'
> +.*: Error: illegal operands `cv.subn t6,t0,1,6'
> +.*: Error: illegal operands `cv.subun t6,t0,8,24'
> +.*: Error: illegal operands `cv.subrn t6,t0,18,21'
> +.*: Error: illegal operands `cv.suburn t6,t0,25,3'
> +.*: Error: illegal operands `cv.subnr t6,t0,14'
> +.*: Error: illegal operands `cv.subunr t6,t0,7'
> +.*: Error: illegal operands `cv.subrnr t6,t0,18'
> +.*: Error: illegal operands `cv.suburnr t6,t0,26'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> new file mode 100644
> index 00000000000..64ee8703579
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> @@ -0,0 +1,26 @@
> +# Source 2 must be of type register
> +target:
> + cv.slet t4,t2,3
> + cv.sletu t4,t2,4
> + cv.min t4,t2,13
> + cv.minu t4,t2,7
> + cv.max t4,t2,17
> + cv.maxu t4,t2,30
> + cv.clipr t4,t2,18
> + cv.clipur t4,t2,29
> + cv.addn t4,t2,24,4
> + cv.addun t4,t2,6,4
> + cv.addrn t6,t0,7,9
> + cv.addurn t6,t0,18,14
> + cv.addnr t6,t0,15
> + cv.addunr t6,t0,24
> + cv.addrnr t6,t0,3
> + cv.addurnr t6,t0,2
> + cv.subn t6,t0,1,6
> + cv.subun t6,t0,8,24
> + cv.subrn t6,t0,18,21
> + cv.suburn t6,t0,25,3
> + cv.subnr t6,t0,14
> + cv.subunr t6,t0,7
> + cv.subrnr t6,t0,18
> + cv.suburnr t6,t0,26
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> new file mode 100644
> index 00000000000..634d9bfe091
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-04.s
> +#error_output: cv-alu-fail-operand-04.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> new file mode 100644
> index 00000000000..d6fd960f9e0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> @@ -0,0 +1,3 @@
> +.*: Assembler messages:
> +.*: Error: instruction cv.clip requires absolute expression
> +.*: Error: instruction cv.clipu requires absolute expression
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> new file mode 100644
> index 00000000000..b97d52a77ab
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> @@ -0,0 +1,4 @@
> +# Five bit immediate must be an absolute value
> +target:
> + cv.clip t4,t2,t3
> + cv.clipu t4,t2,t3
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> new file mode 100644
> index 00000000000..1b90d3e5757
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-05.s
> +#error_output: cv-alu-fail-operand-05.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> new file mode 100644
> index 00000000000..05b5289e743
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> @@ -0,0 +1,9 @@
> +.*: Assembler messages:
> +.*: Error: instruction cv.addn requires absolute expression
> +.*: Error: instruction cv.addun requires absolute expression
> +.*: Error: instruction cv.addrn requires absolute expression
> +.*: Error: instruction cv.addurn requires absolute expression
> +.*: Error: instruction cv.subn requires absolute expression
> +.*: Error: instruction cv.subun requires absolute expression
> +.*: Error: instruction cv.subrn requires absolute expression
> +.*: Error: instruction cv.suburn requires absolute expression
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> new file mode 100644
> index 00000000000..1b0ac6f2d59
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> @@ -0,0 +1,10 @@
> +# Five bit immediate must be an absolute value
> +target:
> + cv.addn t4,t2,t0,t3
> + cv.addun t4,t2,t0,t3
> + cv.addrn t6,t0,t3,t2
> + cv.addurn t6,t0,t3,t2
> + cv.subn t6,t0,t3,t2
> + cv.subun t6,t0,t3,t2
> + cv.subrn t6,t0,t3,t2
> + cv.suburn t6,t0,t3,t2
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> new file mode 100644
> index 00000000000..0a49e682c85
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-06.s
> +#error_output: cv-alu-fail-operand-06.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> new file mode 100644
> index 00000000000..d8059cb5e3a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> @@ -0,0 +1,9 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.clip t0,t3,-1'
> +.*: Error: illegal operands `cv.clipu t0,t3,-1'
> +.*: Error: illegal operands `cv.clip t0,t3,-400'
> +.*: Error: illegal operands `cv.clipu t0,t3,-985'
> +.*: Error: illegal operands `cv.clip t0,t3,32'
> +.*: Error: illegal operands `cv.clipu t0,t3,32'
> +.*: Error: illegal operands `cv.clip t0,t3,859'
> +.*: Error: illegal operands `cv.clipu t0,t3,7283'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> new file mode 100644
> index 00000000000..1b810bdda55
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> @@ -0,0 +1,10 @@
> +# Five bit immediate must be an absolute value in range [0, 31]
> +target:
> + cv.clip t0,t3,-1
> + cv.clipu t0,t3,-1
> + cv.clip t0,t3,-400
> + cv.clipu t0,t3,-985
> + cv.clip t0,t3,32
> + cv.clipu t0,t3,32
> + cv.clip t0,t3,859
> + cv.clipu t0,t3,7283
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> new file mode 100644
> index 00000000000..06d17fede7c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_xcvalu
> +#source: cv-alu-fail-operand-07.s
> +#error_output: cv-alu-fail-operand-07.l
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> new file mode 100644
> index 00000000000..5a34156afc3
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> @@ -0,0 +1,33 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
> +.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
> +.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
> +.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
> +.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
> +.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
> +.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
> +.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
> +.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
> +.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
> +.*: Error: illegal operands `cv.addn t4,t2,t0,32'
> +.*: Error: illegal operands `cv.addun t4,t2,t0,32'
> +.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
> +.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
> +.*: Error: illegal operands `cv.subn t6,t0,t3,32'
> +.*: Error: illegal operands `cv.subun t6,t0,t3,32'
> +.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
> +.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
> +.*: Error: illegal operands `cv.addn t4,t2,t0,320'
> +.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
> +.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
> +.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
> +.*: Error: illegal operands `cv.subn t6,t0,t3,89'
> +.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
> +.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
> +.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
> diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> new file mode 100644
> index 00000000000..04788f69ddd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> @@ -0,0 +1,34 @@
> +# Five bit immediate must be an absolute value in range [0, 31]
> +target:
> + cv.addn t4,t2,t0,-1
> + cv.addun t4,t2,t0,-1
> + cv.addrn t6,t0,t3,-1
> + cv.addurn t6,t0,t3,-1
> + cv.subn t6,t0,t3,-1
> + cv.subun t6,t0,t3,-1
> + cv.subrn t6,t0,t3,-1
> + cv.suburn t6,t0,t3,-1
> + cv.addn t4,t2,t0,-34
> + cv.addun t4,t2,t0,-3556
> + cv.addrn t6,t0,t3,-212
> + cv.addurn t6,t0,t3,-6584
> + cv.subn t6,t0,t3,-89
> + cv.subun t6,t0,t3,-9034
> + cv.subrn t6,t0,t3,-234
> + cv.suburn t6,t0,t3,-284
> + cv.addn t4,t2,t0,32
> + cv.addun t4,t2,t0,32
> + cv.addrn t6,t0,t3,32
> + cv.addurn t6,t0,t3,32
> + cv.subn t6,t0,t3,32
> + cv.subun t6,t0,t3,32
> + cv.subrn t6,t0,t3,32
> + cv.suburn t6,t0,t3,32
> + cv.addn t4,t2,t0,320
> + cv.addun t4,t2,t0,34534
> + cv.addrn t6,t0,t3,254
> + cv.addurn t6,t0,t3,398
> + cv.subn t6,t0,t3,89
> + cv.subun t6,t0,t3,3489
> + cv.subrn t6,t0,t3,143
> + cv.suburn t6,t0,t3,234
> diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d
> b/gas/testsuite/gas/riscv/cv-alu-insns.d
> new file mode 100644
> index 00000000000..784cf5ca6cb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-insns.d
> @@ -0,0 +1,102 @@
> +#as: -march=rv32i_xcvalu
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
> +[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
> +[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
> +[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
> +[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
> +[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
> +[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
> +[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
> +[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
> +[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
> +[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
> +[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
> +[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
> +[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
> +[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
> +[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
> +[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
> +[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
> +[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
> +[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
> +[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
> +[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
> +[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
> +[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
> +[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
> +[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
> +[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
> +[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
> +[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
> +[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
> +[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
> +[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
> +[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
> +[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
> +[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
> +[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
> +[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
> +[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
> +[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
> +[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
> +[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
> +[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
> +[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
> +[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
> +[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
> +[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
> +[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
> +[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
> +[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
> +[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
> +[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
> +[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
> +[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
> +[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
> +[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
> +[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
> +[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
> +[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
> +[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
> +[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
> +[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
> +[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
> +[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
> +[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
> +[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
> +[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
> +[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
> +[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
> +[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
> +[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
> +[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
> +[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
> +[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
> +[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
> +[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
> +[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
> +[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
> +[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
> +[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
> +[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
> +[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
> +[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
> +[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
> +[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
> +[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
> +[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
> +[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
> +[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
> +[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
> +[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
> +[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
> +[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
> +[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
> diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s
> b/gas/testsuite/gas/riscv/cv-alu-insns.s
> new file mode 100644
> index 00000000000..82ea0c3b98d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/cv-alu-insns.s
> @@ -0,0 +1,124 @@
> +target:
> + cv.abs t0,t1
> + cv.abs t4,t2
> + cv.abs t3,t5
> +
> + cv.addnr t0, t3, t6
> + cv.addnr t6, t0, t3
> + cv.addnr t3, t6, t0
> +
> + cv.addn t0, t1, t2, 0
> + cv.addn t4, t2, t0, 4
> + cv.addn t3, t5, t1, 31
> +
> + cv.addrnr t0, t3, t6
> + cv.addrnr t6, t0, t3
> + cv.addrnr t3, t6, t0
> +
> + cv.addrn t0, t3, t6, 0
> + cv.addrn t6, t0, t3, 9
> + cv.addrn t3, t6, t0, 31
> +
> + cv.addunr t0, t3, t6
> + cv.addunr t6, t0, t3
> + cv.addunr t3, t6, t0
> +
> + cv.addun t0, t1, t2, 0
> + cv.addun t4, t2, t0, 4
> + cv.addun t3, t5, t1, 31
> +
> + cv.addurnr t0, t3, t6
> + cv.addurnr t6, t0, t3
> + cv.addurnr t3, t6, t0
> +
> + cv.addurn t0, t3, t6, 0
> + cv.addurn t6, t0, t3, 14
> + cv.addurn t3, t6, t0, 31
> +
> + cv.clipr t0,t1,t2
> + cv.clipr t4,t2,t6
> + cv.clipr t3,t5,t1
> +
> + cv.clip t0,t1,0
> + cv.clip t4,t2,5
> + cv.clip t3,t5,31
> +
> + cv.clipur t0,t1,t2
> + cv.clipur t4,t2,t6
> + cv.clipur t3,t5,t1
> +
> + cv.clipu t0,t1,0
> + cv.clipu t4,t2,5
> + cv.clipu t3,t5,31
> +
> + cv.extbs t0,t1
> + cv.extbs t4,t2
> + cv.extbs t3,t5
> +
> + cv.extbz t0,t1
> + cv.extbz t4,t2
> + cv.extbz t3,t5
> +
> + cv.exths t0,t1
> + cv.exths t4,t2
> + cv.exths t3,t5
> +
> + cv.exthz t0,t1
> + cv.exthz t4,t2
> + cv.exthz t3,t5
> +
> + cv.max t0,t1,t2
> + cv.max t4,t2,t6
> + cv.max t3,t5,t1
> +
> + cv.maxu t0,t1,t2
> + cv.maxu t4,t2,t6
> + cv.maxu t3,t5,t1
> +
> + cv.min t0,t1,t2
> + cv.min t4,t2,t6
> + cv.min t3,t5,t1
> +
> + cv.minu t0,t1,t2
> + cv.minu t4,t2,t6
> + cv.minu t3,t5,t1
> +
> + cv.sle t0,t1,t2
> + cv.sle t4,t2,t6
> + cv.sle t3,t5,t1
> +
> + cv.sleu t0,t1,t2
> + cv.sleu t4,t2,t6
> + cv.sleu t3,t5,t1
> +
> + cv.subnr t0, t3, t6
> + cv.subnr t6, t0, t3
> + cv.subnr t3, t6, t0
> +
> + cv.subn t0, t3, t6, 0
> + cv.subn t6, t0, t3, 6
> + cv.subn t3, t6, t0, 31
> +
> + cv.subrnr t0, t3, t6
> + cv.subrnr t6, t0, t3
> + cv.subrnr t3, t6, t0
> +
> + cv.subrn t0, t3, t6, 0
> + cv.subrn t6, t0, t3, 21
> + cv.subrn t3, t6, t0, 31
> +
> + cv.subunr t0, t3, t6
> + cv.subunr t6, t0, t3
> + cv.subunr t3, t6, t0
> +
> + cv.subun t0, t3, t6, 0
> + cv.subun t6, t0, t3, 24
> + cv.subun t3, t6, t0, 31
> +
> + cv.suburnr t0, t3, t6
> + cv.suburnr t6, t0, t3
> + cv.suburnr t3, t6, t0
> +
> + cv.suburn t0, t3, t6, 0
> + cv.suburn t6, t0, t3, 3
> + cv.suburn t3, t6, t0, 31
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 199ae63585f..9e0e090a8a7 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2341,6 +2341,41 @@
> #define MATCH_CV_MACURN 0x8000705b
> #define MATCH_CV_MACHHURN 0xc000705b
> #define MASK_CV_MULMACN 0xc000707f
> +/* Vendor-specific (CORE-V) Xcvalu instructions. */
> +#define MATCH_CV_ABS 0x5000302b
> +#define MASK_CV_ABS 0xfff0707f
> +#define MATCH_CV_SLET 0x5200302b
> +#define MASK_CV_SLET 0xfe00707f
> +#define MATCH_CV_SLETU 0x5400302b
> +#define MATCH_CV_MIN 0x5600302b
> +#define MATCH_CV_MINU 0x5800302b
> +#define MATCH_CV_MAX 0x5a00302b
> +#define MATCH_CV_MAXU 0x5c00302b
> +#define MATCH_CV_EXTHS 0x6000302b
> +#define MATCH_CV_EXTHZ 0x6200302b
> +#define MATCH_CV_EXTBS 0x6400302b
> +#define MATCH_CV_EXTBZ 0x6600302b
> +#define MATCH_CV_CLIP 0x7000302b
> +#define MATCH_CV_CLIPU 0x7200302b
> +#define MATCH_CV_CLIPR 0x7400302b
> +#define MATCH_CV_CLIPUR 0x7600302b
> +#define MATCH_CV_ADDNR 0x8000302b
> +#define MATCH_CV_ADDUNR 0x8200302b
> +#define MATCH_CV_ADDRNR 0x8400302b
> +#define MATCH_CV_ADDURNR 0x8600302b
> +#define MATCH_CV_SUBNR 0x8800302b
> +#define MATCH_CV_SUBUNR 0x8a00302b
> +#define MATCH_CV_SUBRNR 0x8c00302b
> +#define MATCH_CV_SUBURNR 0x8e00302b
> +#define MATCH_CV_ADDN 0x205b
> +#define MASK_CV_ADDN 0xc000707f
> +#define MATCH_CV_ADDUN 0x4000205b
> +#define MATCH_CV_ADDRN 0x8000205b
> +#define MATCH_CV_ADDURN 0xc000205b
> +#define MATCH_CV_SUBN 0x305b
> +#define MATCH_CV_SUBUN 0x4000305b
> +#define MATCH_CV_SUBRN 0x8000305b
> +#define MATCH_CV_SUBURN 0xc000305b
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> #define MATCH_TH_ADDSL 0x0000100b
> #define MASK_TH_ADDSL 0xf800707f
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 5097d2cf6c1..18236a6150c 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
> (RV_X(x, 5, 1) << 1)
> /* Vendor-specific (CORE-V) extract macros. */
> +#define EXTRACT_CV_IS2_UIMM5(x) \
> + (RV_X(x, 20, 5))
> #define EXTRACT_CV_IS3_UIMM5(x) \
> (RV_X(x, 25, 5))
>
> @@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> #define ENCODE_ZCB_HALFWORD_UIMM(x) \
> (RV_X(x, 1, 1) << 5)
> /* Vendor-specific (CORE-V) encode macros. */
> +#define ENCODE_CV_IS2_UIMM5(x) \
> + (RV_X(x, 0, 5) << 20)
> #define ENCODE_CV_IS3_UIMM5(x) \
> (RV_X(x, 0, 5) << 25)
>
> @@ -450,6 +454,7 @@ enum riscv_insn_class
> INSN_CLASS_ZICBOZ,
> INSN_CLASS_H,
> INSN_CLASS_XCVMAC,
> + INSN_CLASS_XCVALU,
> INSN_CLASS_XTHEADBA,
> INSN_CLASS_XTHEADBB,
> INSN_CLASS_XTHEADBS,
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index b16db5113b1..d10a1e393e7 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -432,16 +432,20 @@ print_insn_args (const char *oparg, insn_t l,
> bfd_vma pc, disassemble_info *info
> case 'x': /* Vendor-specific operands. */
> switch (*++oparg)
> {
> - /* Vendor-specific (CORE-V) operands. */
> - case 'c':
> - switch (*++oparg)
> - {
> - case '3':
> - print (info->stream, dis_style_immediate, "%d",
> - ((int) EXTRACT_CV_IS3_UIMM5 (l)));
> - break;
> - }
> - break;
> + /* Vendor-specific (CORE-V) operands. */
> + case 'c':
> + switch (*++oparg)
> + {
> + case '2':
> + print (info->stream, dis_style_immediate, "%d",
> + ((int) EXTRACT_CV_IS2_UIMM5 (l)));
> + break;
> + case '3':
> + print (info->stream, dis_style_immediate, "%d",
> + ((int) EXTRACT_CV_IS3_UIMM5 (l)));
> + break;
> + }
> + break;
> }
> break;
>
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 1b2023b96bd..0b4b4b7dd4d 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2065,6 +2065,41 @@ const struct riscv_opcode riscv_opcodes[] =
> {"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACURN,
> MASK_CV_MULMACN, match_opcode, 0},
> {"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHURN,
> MASK_CV_MULMACN, match_opcode, 0},
>
> +/* Vendor-specific (CORE-V) Xcvalu instructions. */
> +{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS,
> MASK_CV_ABS, match_opcode, 0},
> +{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS,
> MASK_CV_ABS, match_opcode, 0},
> +{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ,
> MASK_CV_ABS, match_opcode, 0},
> +{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS,
> MASK_CV_ABS, match_opcode, 0},
> +{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ,
> MASK_CV_ABS, match_opcode, 0},
> +{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET,
> MASK_CV_SLET, match_opcode, INSN_ALIAS},
> +{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU,
> MASK_CV_SLET, match_opcode, INSN_ALIAS},
> +{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIP,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIPU,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDUN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDRN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDURN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBUN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBRN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBURN,
> MASK_CV_ADDN, match_opcode, 0},
> +{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR,
> MASK_CV_SLET, match_opcode, 0},
> +{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR,
> MASK_CV_SLET, match_opcode, 0},
> +
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25",
> MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-05 14:53 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
@ 2023-09-07 4:49 ` Nelson Chu
2023-09-07 6:57 ` Kito Cheng
2023-09-07 10:11 ` Tsukasa OI
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
4 siblings, 1 reply; 16+ messages in thread
From: Nelson Chu @ 2023-09-07 4:49 UTC (permalink / raw)
To: Mary Bennett
Cc: binutils, Jim Wilson, Jeff Law, Kito Cheng, Palmer Dabbelt,
Andrew Waterman
[-- Attachment #1: Type: text/plain, Size: 7049 bytes --]
Hi Mary,
Thanks for the contribution, the vendor core-v extensions in binutils look
good to me :-)
Hi Jeff, Kito, Palmer and Andrew,
I am not sure if we are likely to accept the vendor core-v extension only
in binutils first? Or if we prefer to accept it with the whole toolchain
support, including gcc and qemu. Need your help, thanks!
If I forgot to cc anyone who may be related, please feel free to add them
in the discussion!
Nelson
On Tue, Sep 5, 2023 at 10:53 PM Mary Bennett <mary.bennett@embecosm.com>
wrote:
> This patch series presents the comprehensive implementation of the MAC and
> ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V instructions are described in the specification [1] and work
> can be
> found in the OpenHW group's Github repository [2].
>
> [1]
> docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> [2] github.com/openhwgroup/corev-binutils-gdb
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
>
> RISC-V: Add support for XCValu extension in CV32E40P
> RISC-V: Add support for XCVmac extension in CV32E40P
>
> bfd/elfxx-riscv.c | 11 ++
> gas/config/tc-riscv.c | 60 +++++++
> gas/doc/c-riscv.texi | 10 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
> gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
> gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-01.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-02.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-03.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
> .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
> .../gas/riscv/cv-alu-fail-operand-04.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.l | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.s | 4 +
> .../gas/riscv/cv-alu-fail-operand-05.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-05.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-06.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-06.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-07.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
> gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
> gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
> gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
> include/opcode/riscv-opc.h | 56 +++++++
> include/opcode/riscv.h | 12 ++
> opcodes/riscv-dis.c | 20 +++
> opcodes/riscv-opc.c | 61 +++++++
> 44 files changed, 1406 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-09-07 4:49 ` [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Nelson Chu
@ 2023-09-07 6:57 ` Kito Cheng
0 siblings, 0 replies; 16+ messages in thread
From: Kito Cheng @ 2023-09-07 6:57 UTC (permalink / raw)
To: Nelson Chu
Cc: Mary Bennett, binutils, Jim Wilson, Jeff Law, Kito Cheng,
Palmer Dabbelt, Andrew Waterman
I am open mind to accept Core-v support for GNU toolchain, and I think
binutils should support first :P
On Thu, Sep 7, 2023 at 12:50 PM Nelson Chu <nelson@rivosinc.com> wrote:
>
> Hi Mary,
>
> Thanks for the contribution, the vendor core-v extensions in binutils look
> good to me :-)
>
> Hi Jeff, Kito, Palmer and Andrew,
>
> I am not sure if we are likely to accept the vendor core-v extension only
> in binutils first? Or if we prefer to accept it with the whole toolchain
> support, including gcc and qemu. Need your help, thanks!
>
> If I forgot to cc anyone who may be related, please feel free to add them
> in the discussion!
>
> Nelson
>
> On Tue, Sep 5, 2023 at 10:53 PM Mary Bennett <mary.bennett@embecosm.com>
> wrote:
>
> > This patch series presents the comprehensive implementation of the MAC and
> > ALU
> > extension for CORE-V.
> >
> > Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> > ensure its correctness and compatibility with the existing codebase.
> > However, your input, reviews, and suggestions are invaluable in making this
> > extension even more robust.
> >
> > The CORE-V instructions are described in the specification [1] and work
> > can be
> > found in the OpenHW group's Github repository [2].
> >
> > [1]
> > docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
> >
> > [2] github.com/openhwgroup/corev-binutils-gdb
> >
> > Contributors:
> > Mary Bennett <mary.bennett@embecosm.com>
> > Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> > Pietra Ferreira <pietra.ferreira@embecosm.com>
> > Charlie Keaney
> > Jessica Mills
> > Craig Blackmore <craig.blackmore@embecosm.com>
> > Simon Cook <simon.cook@embecosm.com>
> > Jeremy Bennett <jeremy.bennett@embecosm.com>
> >
> > RISC-V: Add support for XCValu extension in CV32E40P
> > RISC-V: Add support for XCVmac extension in CV32E40P
> >
> > bfd/elfxx-riscv.c | 11 ++
> > gas/config/tc-riscv.c | 60 +++++++
> > gas/doc/c-riscv.texi | 10 ++
> > gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
> > gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
> > gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
> > gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
> > gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
> > gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
> > .../gas/riscv/cv-alu-fail-operand-01.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
> > .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
> > .../gas/riscv/cv-alu-fail-operand-02.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
> > .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
> > .../gas/riscv/cv-alu-fail-operand-03.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
> > .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
> > .../gas/riscv/cv-alu-fail-operand-04.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-04.l | 3 +
> > .../gas/riscv/cv-alu-fail-operand-04.s | 4 +
> > .../gas/riscv/cv-alu-fail-operand-05.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-05.l | 9 +
> > .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
> > .../gas/riscv/cv-alu-fail-operand-06.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-06.l | 9 +
> > .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
> > .../gas/riscv/cv-alu-fail-operand-07.d | 3 +
> > .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
> > .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
> > gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
> > gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
> > gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
> > gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
> > gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
> > gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
> > gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
> > gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
> > gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
> > gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
> > include/opcode/riscv-opc.h | 56 +++++++
> > include/opcode/riscv.h | 12 ++
> > opcodes/riscv-dis.c | 20 +++
> > opcodes/riscv-opc.c | 61 +++++++
> > 44 files changed, 1406 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
> > create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
> >
> > --
> > 2.34.1
> >
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
` (2 preceding siblings ...)
2023-09-07 4:49 ` [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Nelson Chu
@ 2023-09-07 10:11 ` Tsukasa OI
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
4 siblings, 0 replies; 16+ messages in thread
From: Tsukasa OI @ 2023-09-07 10:11 UTC (permalink / raw)
To: Mary Bennett; +Cc: Binutils
Hi,
In general, I request one large change to your patch set.
> +{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MACMSU, match_opcode, 0},
> +{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MACMSU, match_opcode, 0},
MASK values should be per (non-alias) instruction. Yes, that would make
many MASK macros with different names but per-instruction MASK value is
riscv-opcodes friendly and makes inspecting the opcodes easier.
So, please make MASK values per-instruction as well as MATCH values and
order like:
- MATCH_CV_MAC
- MASK_CV_MAC
- MATCH_CV_MSU
- MASK_CV_MSU
- MATCH_CV_MULSN
- MASK_CV_MULSN
- MATCH_CV_MULSRN
- MASK_CV_MULSRN...
in PATCH 1/2 and likewise in PATCH 2/2.
Otherwise it looks good (I haven't closely inspected yet though).
Thanks,
Tsukasa
On 2023/09/05 23:52, Mary Bennett wrote:
> This patch series presents the comprehensive implementation of the MAC and ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V instructions are described in the specification [1] and work can be
> found in the OpenHW group's Github repository [2].
>
> [1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> [2] github.com/openhwgroup/corev-binutils-gdb
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
>
> RISC-V: Add support for XCValu extension in CV32E40P
> RISC-V: Add support for XCVmac extension in CV32E40P
>
> bfd/elfxx-riscv.c | 11 ++
> gas/config/tc-riscv.c | 60 +++++++
> gas/doc/c-riscv.texi | 10 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
> gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
> gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-01.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-02.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-03.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
> .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
> .../gas/riscv/cv-alu-fail-operand-04.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.l | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.s | 4 +
> .../gas/riscv/cv-alu-fail-operand-05.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-05.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-06.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-06.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-07.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
> gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
> gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
> gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
> include/opcode/riscv-opc.h | 56 +++++++
> include/opcode/riscv.h | 12 ++
> opcodes/riscv-dis.c | 20 +++
> opcodes/riscv-opc.c | 61 +++++++
> 44 files changed, 1406 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
` (3 preceding siblings ...)
2023-09-07 10:11 ` Tsukasa OI
@ 2023-09-12 14:24 ` Mary Bennett
2023-09-12 14:24 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
` (2 more replies)
4 siblings, 3 replies; 16+ messages in thread
From: Mary Bennett @ 2023-09-12 14:24 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, nelson, research_trasio
Changes: v1 -> v2
- Added MASK_<INSN> for each instruction, as suggested
- Changed operand 'x' to operand 'X', as suggested
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
[2] github.com/openhwgroup/corev-binutils-gdb
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Add support for XCValu extension in CV32E40P
RISC-V: Add support for XCVmac extension in CV32E40P
bfd/elfxx-riscv.c | 11 ++
gas/config/tc-riscv.c | 42 +++++
gas/doc/c-riscv.texi | 10 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 +
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 +
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 104 ++++++++++++
include/opcode/riscv.h | 12 ++
opcodes/riscv-dis.c | 13 ++
opcodes/riscv-opc.c | 61 +++++++
44 files changed, 1429 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
@ 2023-09-12 14:24 ` Mary Bennett
2023-09-12 14:24 ` [PATCH v2 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2 siblings, 0 replies; 16+ messages in thread
From: Mary Bennett @ 2023-09-12 14:24 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, nelson, research_trasio
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
---
bfd/elfxx-riscv.c | 6 +
gas/config/tc-riscv.c | 28 ++++
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 37 +++++
include/opcode/riscv.h | 7 +
opcodes/riscv-dis.c | 9 +
opcodes/riscv-opc.c | 26 +++
15 files changed, 642 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb65024beaf..a3c32941866 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1347,6 +1347,8 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
+ /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
+ {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2539,6 +2541,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
+ case INSN_CLASS_XCVMAC:
+ return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2779,6 +2783,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
+ case INSN_CLASS_XCVMAC:
+ return "xcvmac";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e49b34fd524..3dd6123c79b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1452,6 +1452,16 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'l': /* Literal. */
oparg += strcspn(oparg, ",") - 1;
break;
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
+ break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
goto use_imm;
case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
@@ -1470,6 +1480,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
}
}
break;
+
default:
unknown_validate_operand:
as_bad (_("internal: bad RISC-V opcode "
@@ -3632,6 +3643,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
oparg += n - 1;
asarg += n;
continue;
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number<0
+ || imm_expr->X_add_number>31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
+ continue;
+ default:
+ goto unknown_riscv_ip_operand;
+ }
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
sign = true;
goto parse_imm;
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index b175ba0a729..1dcdeeb7b36 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -745,6 +745,11 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
+@item Xcvmac
+The Xcvmac extension provides instructions for multiply-accumulate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.d b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
new file mode 100644
index 00000000000..eb6352f85f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-mac-fail-march.s
+#error_output: cv-mac-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.l b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
new file mode 100644
index 00000000000..d2bc12c804a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
@@ -0,0 +1,23 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension `xcvmac' required
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.s b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
new file mode 100644
index 00000000000..78b08423a64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
@@ -0,0 +1,24 @@
+# Absence of the xcvmac march option disables all CORE-V MAC extensions.
+target:
+ cv.mac t4, t2, t0
+ cv.msu t4, t2, t0
+ cv.muls t4, t2, t0
+ cv.mulhhs t4, t2, t0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulu t4, t2, t0
+ cv.mulhhu t4, t2, t0
+ cv.mulun t4, t2, t0, 7
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulurn t4, t2, t0, 11
+ cv.mulhhurn t4, t2, t0, 9
+ cv.macsn t4, t2, t0, 24
+ cv.machhsn t4, t2, t0, 11
+ cv.macsrn t4, t2, t0, 9
+ cv.machhsrn t4, t2, t0, 24
+ cv.macun t4, t2, t0, 27
+ cv.machhun t4, t2, t0, 18
+ cv.macurn t4, t2, t0, 25
+ cv.machhurn t4, t2, t0, 5
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
new file mode 100644
index 00000000000..51e1b3052c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmac
+#source: cv-mac-fail-operand.s
+#error_output: cv-mac-fail-operand.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
new file mode 100644
index 00000000000..645949696cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
@@ -0,0 +1,147 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.mac 8,t2,t0'
+.*: Error: illegal operands `cv.msu 23,t2,t0'
+.*: Error: illegal operands `cv.muls 43,t2,t0'
+.*: Error: illegal operands `cv.mulhhs 7,t2,t0'
+.*: Error: illegal operands `cv.mulsn 345,t2,t0,4'
+.*: Error: illegal operands `cv.mulhhsn 356,t2,t0,16'
+.*: Error: illegal operands `cv.mulsrn 867,t2,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn 3454,t2,t0,17'
+.*: Error: illegal operands `cv.mulu 9,t2,t0'
+.*: Error: illegal operands `cv.mulhhu 54,t2,t0'
+.*: Error: illegal operands `cv.mulun 965,t2,t0,7'
+.*: Error: illegal operands `cv.mulhhun 35,t2,t0,16'
+.*: Error: illegal operands `cv.mulurn 87,t2,t0,11'
+.*: Error: illegal operands `cv.mulhhurn 38,t2,t0,9'
+.*: Error: illegal operands `cv.macsn 985,t2,t0,24'
+.*: Error: illegal operands `cv.machhsn 83,t2,t0,11'
+.*: Error: illegal operands `cv.macsrn 960,t2,t0,9'
+.*: Error: illegal operands `cv.machhsrn 385,t2,t0,24'
+.*: Error: illegal operands `cv.macun 58,t2,t0,27'
+.*: Error: illegal operands `cv.machhun 6,t2,t0,18'
+.*: Error: illegal operands `cv.macurn 35,t2,t0,25'
+.*: Error: illegal operands `cv.machhurn 67,t2,t0,5'
+.*: Error: illegal operands `cv.mac t4,43,t0'
+.*: Error: illegal operands `cv.msu t4,3,t0'
+.*: Error: illegal operands `cv.muls t4,345,t0'
+.*: Error: illegal operands `cv.mulhhs t4,54,t0'
+.*: Error: illegal operands `cv.mulsn t4,4,t0,4'
+.*: Error: illegal operands `cv.mulhhsn t4,35,t0,16'
+.*: Error: illegal operands `cv.mulsrn t4,53,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,4456,t0,17'
+.*: Error: illegal operands `cv.mulu t4,868,t0'
+.*: Error: illegal operands `cv.mulhhu t4,95,t0'
+.*: Error: illegal operands `cv.mulun t4,584,t0,7'
+.*: Error: illegal operands `cv.mulhhun t4,37545,t0,16'
+.*: Error: illegal operands `cv.mulurn t4,943,t0,11'
+.*: Error: illegal operands `cv.mulhhurn t4,34,t0,9'
+.*: Error: illegal operands `cv.macsn t4,93,t0,24'
+.*: Error: illegal operands `cv.machhsn t4,584,t0,11'
+.*: Error: illegal operands `cv.macsrn t4,28,t0,9'
+.*: Error: illegal operands `cv.machhsrn t4,9,t0,24'
+.*: Error: illegal operands `cv.macun t4,834,t0,27'
+.*: Error: illegal operands `cv.machhun t4,92,t0,18'
+.*: Error: illegal operands `cv.macurn t4,49,t0,25'
+.*: Error: illegal operands `cv.machhurn t4,6,t0,5'
+.*: Error: illegal operands `cv.mac t4,t2,344'
+.*: Error: illegal operands `cv.msu t4,t2,23'
+.*: Error: illegal operands `cv.muls t4,t2,2'
+.*: Error: illegal operands `cv.mulhhs t4,t2,8'
+.*: Error: illegal operands `cv.mulsn t4,t2,45,4'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,655,16'
+.*: Error: illegal operands `cv.mulsrn t4,t2,465,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,3534,17'
+.*: Error: illegal operands `cv.mulu t4,t2,46'
+.*: Error: illegal operands `cv.mulhhu t4,t2,35'
+.*: Error: illegal operands `cv.mulun t4,t2,67,7'
+.*: Error: illegal operands `cv.mulhhun t4,t2,6,16'
+.*: Error: illegal operands `cv.mulurn t4,t2,787,11'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,3545,9'
+.*: Error: illegal operands `cv.macsn t4,t2,6,24'
+.*: Error: illegal operands `cv.machhsn t4,t2,765,11'
+.*: Error: illegal operands `cv.macsrn t4,t2,45,9'
+.*: Error: illegal operands `cv.machhsrn t4,t2,7,24'
+.*: Error: illegal operands `cv.macun t4,t2,98,27'
+.*: Error: illegal operands `cv.machhun t4,t2,654,18'
+.*: Error: illegal operands `cv.macurn t4,t2,900,25'
+.*: Error: illegal operands `cv.machhurn t4,t2,354,5'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-43'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-23'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-223'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-8'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-2'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-45'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-354'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macun t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,325'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,254'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,76'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,5364'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,34435'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,3423'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,365'
+.*: Error: illegal operands `cv.macun t4,t2,t0,432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,45'
+.*: Error: instruction cv.mulsn requires absolute expression
+.*: Error: instruction cv.mulhhsn requires absolute expression
+.*: Error: instruction cv.mulsrn requires absolute expression
+.*: Error: instruction cv.mulhhsrn requires absolute expression
+.*: Error: instruction cv.mulun requires absolute expression
+.*: Error: instruction cv.mulhhun requires absolute expression
+.*: Error: instruction cv.mulurn requires absolute expression
+.*: Error: instruction cv.mulhhurn requires absolute expression
+.*: Error: instruction cv.macsn requires absolute expression
+.*: Error: instruction cv.machhsn requires absolute expression
+.*: Error: instruction cv.macsrn requires absolute expression
+.*: Error: instruction cv.machhsrn requires absolute expression
+.*: Error: instruction cv.macun requires absolute expression
+.*: Error: instruction cv.machhun requires absolute expression
+.*: Error: instruction cv.macurn requires absolute expression
+.*: Error: instruction cv.machhurn requires absolute expression
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,354'
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
new file mode 100644
index 00000000000..97a29448ebd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
@@ -0,0 +1,156 @@
+# Destination must be of type register
+target:
+ cv.mac 8, t2, t0
+ cv.msu 23, t2, t0
+ cv.muls 43, t2, t0
+ cv.mulhhs 7, t2, t0
+ cv.mulsn 345, t2, t0, 4
+ cv.mulhhsn 356, t2, t0, 16
+ cv.mulsrn 867, t2, t0, 10
+ cv.mulhhsrn 3454, t2, t0, 17
+ cv.mulu 9, t2, t0
+ cv.mulhhu 54, t2, t0
+ cv.mulun 965, t2, t0, 7
+ cv.mulhhun 35, t2, t0, 16
+ cv.mulurn 87, t2, t0, 11
+ cv.mulhhurn 38, t2, t0, 9
+ cv.macsn 985, t2, t0, 24
+ cv.machhsn 83, t2, t0, 11
+ cv.macsrn 960, t2, t0, 9
+ cv.machhsrn 385, t2, t0, 24
+ cv.macun 58, t2, t0, 27
+ cv.machhun 6, t2, t0, 18
+ cv.macurn 35, t2, t0, 25
+ cv.machhurn 67, t2, t0, 5
+
+# Source one must be of type register
+ cv.mac t4, 43, t0
+ cv.msu t4, 3, t0
+ cv.muls t4, 345, t0
+ cv.mulhhs t4, 54, t0
+ cv.mulsn t4, 4, t0, 4
+ cv.mulhhsn t4, 35, t0, 16
+ cv.mulsrn t4, 53, t0, 10
+ cv.mulhhsrn t4, 4456, t0, 17
+ cv.mulu t4, 868, t0
+ cv.mulhhu t4, 95, t0
+ cv.mulun t4, 584, t0, 7
+ cv.mulhhun t4, 37545, t0, 16
+ cv.mulurn t4, 943, t0, 11
+ cv.mulhhurn t4, 34, t0, 9
+ cv.macsn t4, 93, t0, 24
+ cv.machhsn t4, 584, t0, 11
+ cv.macsrn t4, 28, t0, 9
+ cv.machhsrn t4, 9, t0, 24
+ cv.macun t4, 834, t0, 27
+ cv.machhun t4, 92, t0, 18
+ cv.macurn t4, 49, t0, 25
+ cv.machhurn t4, 6, t0, 5
+
+# Source two must be of type register
+ cv.mac t4, t2, 344
+ cv.msu t4, t2, 23
+ cv.muls t4, t2, 2
+ cv.mulhhs t4, t2, 8
+ cv.mulsn t4, t2, 45, 4
+ cv.mulhhsn t4, t2, 655, 16
+ cv.mulsrn t4, t2, 465, 10
+ cv.mulhhsrn t4, t2, 3534, 17
+ cv.mulu t4, t2, 46
+ cv.mulhhu t4, t2, 35
+ cv.mulun t4, t2, 67, 7
+ cv.mulhhun t4, t2, 6, 16
+ cv.mulurn t4, t2, 787, 11
+ cv.mulhhurn t4, t2, 3545, 9
+ cv.macsn t4, t2, 6, 24
+ cv.machhsn t4, t2, 765, 11
+ cv.macsrn t4, t2, 45, 9
+ cv.machhsrn t4, t2, 7, 24
+ cv.macun t4, t2, 98, 27
+ cv.machhun t4, t2, 654, 18
+ cv.macurn t4, t2, 900, 25
+ cv.machhurn t4, t2, 354, 5
+
+# Immediate value must be in range [0, 31]
+ cv.mulsn t4, t2, t0, -1
+ cv.mulhhsn t4, t2, t0, -1
+ cv.mulsrn t4, t2, t0, -1
+ cv.mulhhsrn t4, t2, t0, -1
+ cv.mulun t4, t2, t0, -1
+ cv.mulhhun t4, t2, t0, -1
+ cv.mulurn t4, t2, t0, -1
+ cv.mulhhurn t4, t2, t0, -1
+ cv.macsn t4, t2, t0, -1
+ cv.machhsn t4, t2, t0, -1
+ cv.macsrn t4, t2, t0, -1
+ cv.machhsrn t4, t2, t0, -1
+ cv.macun t4, t2, t0, -1
+ cv.machhun t4, t2, t0, -1
+ cv.macurn t4, t2, t0, -1
+ cv.machhurn t4, t2, t0, -1
+ cv.mulsn t4, t2, t0, -43
+ cv.mulhhsn t4, t2, t0, -531
+ cv.mulsrn t4, t2, t0, -4454
+ cv.mulhhsrn t4, t2, t0, -32
+ cv.mulun t4, t2, t0, -23
+ cv.mulhhun t4, t2, t0, -459
+ cv.mulurn t4, t2, t0, -549
+ cv.mulhhurn t4, t2, t0, -32
+ cv.macsn t4, t2, t0, -223
+ cv.machhsn t4, t2, t0, -56
+ cv.macsrn t4, t2, t0, -8
+ cv.machhsrn t4, t2, t0, -2
+ cv.macun t4, t2, t0, -432
+ cv.machhun t4, t2, t0, -1245
+ cv.macurn t4, t2, t0, -45
+ cv.machhurn t4, t2, t0, -354
+ cv.mulsn t4, t2, t0, 32
+ cv.mulhhsn t4, t2, t0, 32
+ cv.mulsrn t4, t2, t0, 32
+ cv.mulhhsrn t4, t2, t0, 32
+ cv.mulun t4, t2, t0, 32
+ cv.mulhhun t4, t2, t0, 32
+ cv.mulurn t4, t2, t0, 32
+ cv.mulhhurn t4, t2, t0, 32
+ cv.macsn t4, t2, t0, 32
+ cv.machhsn t4, t2, t0, 32
+ cv.macsrn t4, t2, t0, 32
+ cv.machhsrn t4, t2, t0, 32
+ cv.macun t4, t2, t0, 32
+ cv.machhun t4, t2, t0, 32
+ cv.macurn t4, t2, t0, 32
+ cv.machhurn t4, t2, t0, 32
+ cv.mulsn t4, t2, t0, 325
+ cv.mulhhsn t4, t2, t0, 531
+ cv.mulsrn t4, t2, t0, 4454
+ cv.mulhhsrn t4, t2, t0, 254
+ cv.mulun t4, t2, t0, 76
+ cv.mulhhun t4, t2, t0, 459
+ cv.mulurn t4, t2, t0, 549
+ cv.mulhhurn t4, t2, t0, 5364
+ cv.macsn t4, t2, t0, 34435
+ cv.machhsn t4, t2, t0, 56
+ cv.macsrn t4, t2, t0, 3423
+ cv.machhsrn t4, t2, t0, 365
+ cv.macun t4, t2, t0, 432
+ cv.machhun t4, t2, t0, 1245
+ cv.macurn t4, t2, t0, 45
+
+# Immediate value must be an absolute expression
+ cv.mulsn t4, t2, t0, t3
+ cv.mulhhsn t4, t2, t0, t1
+ cv.mulsrn t4, t2, t0, t6
+ cv.mulhhsrn t4, t2, t0, t3
+ cv.mulun t4, t2, t0, t1
+ cv.mulhhun t4, t2, t0, t3
+ cv.mulurn t4, t2, t0, t5
+ cv.mulhhurn t4, t2, t0, t1
+ cv.macsn t4, t2, t0, t3
+ cv.machhsn t4, t2, t0, t5
+ cv.macsrn t4, t2, t0, t1
+ cv.machhsrn t4, t2, t0, t6
+ cv.macun t4, t2, t0, t1
+ cv.machhun t4, t2, t0, t3
+ cv.macurn t4, t2, t0, t6
+ cv.machhurn t4, t2, t0, t5
+ cv.machhurn t4, t2, t0, 354
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.d b/gas/testsuite/gas/riscv/cv-mac-insns.d
new file mode 100644
index 00000000000..9a961051a97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.d
@@ -0,0 +1,87 @@
+#as: -march=rv32i_xcvmac
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
+[ ]+4:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
+[ ]+8:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
+[ ]+c:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
+[ ]+10:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
+[ ]+14:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
+[ ]+18:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
+[ ]+20:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
+[ ]+28:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
+[ ]+2c:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
+[ ]+30:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
+[ ]+34:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
+[ ]+38:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
+[ ]+3c:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
+[ ]+40:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
+[ ]+44:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
+[ ]+48:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
+[ ]+50:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
+[ ]+54:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
+[ ]+58:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
+[ ]+5c:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
+[ ]+60:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
+[ ]+64:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
+[ ]+68:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
+[ ]+6c:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
+[ ]+70:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
+[ ]+74:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
+[ ]+78:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+7c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+80:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+84:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+88:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
+[ ]+8c:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
+[ ]+90:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
+[ ]+94:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
+[ ]+98:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
+[ ]+9c:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+a0:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+a4:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+a8:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+ac:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
+[ ]+b0:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
+[ ]+b4:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
+[ ]+b8:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
+[ ]+bc:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
+[ ]+c0:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+c4:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+c8:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+cc:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+d0:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
+[ ]+d4:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
+[ ]+d8:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
+[ ]+dc:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
+[ ]+e0:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
+[ ]+e4:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+e8:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+ec:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
+[ ]+f0:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+f4:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
+[ ]+f8:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
+[ ]+fc:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
+[ ]+100:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
+[ ]+104:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
+[ ]+108:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+10c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+110:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+114:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+118:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+11c:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+120:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+124:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+128:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+12c:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+130:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+134:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.s b/gas/testsuite/gas/riscv/cv-mac-insns.s
new file mode 100644
index 00000000000..a699a3ba461
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.s
@@ -0,0 +1,81 @@
+target:
+ cv.mac t0, t1, t2
+ cv.mac t4, t2, t0
+ cv.mac t3, t5, t1
+ cv.machhsn t0, t1, t2, 0
+ cv.machhsn t4, t2, t0, 11
+ cv.machhsn t3, t5, t1, 31
+ cv.machhsrn t0, t1, t2, 0
+ cv.machhsrn t4, t2, t0, 24
+ cv.machhsrn t3, t5, t1, 31
+ cv.machhun t0, t1, t2, 0
+ cv.machhun t4, t2, t0, 18
+ cv.machhun t3, t5, t1, 31
+ cv.machhurn t0, t1, t2, 0
+ cv.machhurn t4, t2, t0, 5
+ cv.machhurn t3, t5, t1, 31
+ cv.macsn t0, t1, t2, 0
+ cv.macsn t4, t2, t0, 24
+ cv.macsn t3, t5, t1, 31
+ cv.macsrn t0, t1, t2, 0
+ cv.macsrn t4, t2, t0, 9
+ cv.macsrn t3, t5, t1, 31
+ cv.macun t0, t1, t2, 0
+ cv.macun t4, t2, t0, 27
+ cv.macun t3, t5, t1, 31
+ cv.macurn t0, t1, t2, 0
+ cv.macurn t4, t2, t0, 25
+ cv.macurn t3, t5, t1, 31
+ cv.msu t0, t1, t2
+ cv.msu t4, t2, t0
+ cv.msu t3, t5, t1
+ cv.mulhhs t0, t1, t2
+ cv.mulhhs t4, t2, t0
+ cv.mulhhs t3, t5, t1
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulhhsn t3, t5, t1, 31
+ cv.mulhhsrn t0, t1, t2, 0
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulhhsrn t3, t5, t1, 31
+ cv.mulhhu t0, t1, t2
+ cv.mulhhu t4, t2, t0
+ cv.mulhhu t3, t5, t1
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulhhun t3, t5, t1, 31
+ cv.mulhhurn t0, t1, t2, 0
+ cv.mulhhurn t4, t2, t0, 9
+ cv.mulhhurn t3, t5, t1, 31
+ cv.muls t0, t1, t2
+ cv.muls t4, t2, t0
+ cv.muls t3, t5, t1
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulsn t3, t5, t1, 31
+ cv.mulsrn t0, t1, t2, 0
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulsrn t3, t5, t1, 31
+ cv.mulu t0, t1, t2
+ cv.mulu t4, t2, t0
+ cv.mulu t3, t5, t1
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 7
+ cv.mulun t3, t5, t1, 31
+ cv.mulurn t0, t1, t2, 0
+ cv.mulurn t4, t2, t0, 11
+ cv.mulurn t3, t5, t1, 31
+
+ # Pseudo-instructions
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 0
+ cv.mulhhsn t3, t5, t1, 0
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 0
+ cv.mulhhun t3, t5, t1, 0
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 0
+ cv.mulsn t3, t5, t1, 0
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 0
+ cv.mulun t3, t5, t1, 0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 26d2c04bf24..ce935336588 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2320,6 +2320,43 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+#define MATCH_CV_MAC 0x9000302b
+#define MASK_CV_MAC 0xfe00707f
+#define MATCH_CV_MSU 0x9200302b
+#define MASK_CV_MSU 0xfe00707f
+#define MATCH_CV_MULSN 0x405b
+#define MASK_CV_MULSN 0xc000707f
+#define MATCH_CV_MULHHSN 0x4000405b
+#define MASK_CV_MULHHSN 0xc000707f
+#define MATCH_CV_MULSRN 0x8000405b
+#define MASK_CV_MULSRN 0xc000707f
+#define MATCH_CV_MULHHSRN 0xc000405b
+#define MASK_CV_MULHHSRN 0xc000707f
+#define MATCH_CV_MULUN 0x505b
+#define MASK_CV_MULUN 0xc000707f
+#define MATCH_CV_MULHHUN 0x4000505b
+#define MASK_CV_MULHHUN 0xc000707f
+#define MATCH_CV_MULURN 0x8000505b
+#define MASK_CV_MULURN 0xc000707f
+#define MATCH_CV_MULHHURN 0xc000505b
+#define MASK_CV_MULHHURN 0xc000707f
+#define MATCH_CV_MACSN 0x605b
+#define MASK_CV_MACSN 0xc000707f
+#define MATCH_CV_MACHHSN 0x4000605b
+#define MASK_CV_MACHHSN 0xc000707f
+#define MATCH_CV_MACSRN 0x8000605b
+#define MASK_CV_MACSRN 0xc000707f
+#define MATCH_CV_MACHHSRN 0xc000605b
+#define MASK_CV_MACHHSRN 0xc000707f
+#define MATCH_CV_MACUN 0x705b
+#define MASK_CV_MACUN 0xc000707f
+#define MATCH_CV_MACHHUN 0x4000705b
+#define MASK_CV_MACHHUN 0xc000707f
+#define MATCH_CV_MACURN 0x8000705b
+#define MASK_CV_MACURN 0xc000707f
+#define MATCH_CV_MACHHURN 0xc000705b
+#define MASK_CV_MACHHURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 38927bd0c74..5097d2cf6c1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -112,6 +112,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
+/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS3_UIMM5(x) \
+ (RV_X(x, 25, 5))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -163,6 +166,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
+/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS3_UIMM5(x) \
+ (RV_X(x, 0, 5) << 25)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -443,6 +449,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
+ INSN_CLASS_XCVMAC,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 90f0fea1692..2b328f138e9 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -651,6 +651,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
}
oparg--;
break;
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS3_UIMM5 (l)));
+ break;
+ }
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
sign = true;
goto print_imm;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 39da5f84e74..2386b47f16a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -154,6 +154,8 @@ const float riscv_fli_numval[32] =
#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+/* Vendor-specific (CORE-V) masks. */
+#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)
static int
match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -2039,6 +2041,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
+{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
+{"cv.mulsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSN, MASK_CV_MULSN, match_opcode, 0},
+{"cv.muls", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULSN, MASK_CV_MULSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSRN, MASK_CV_MULSRN, match_opcode, 0},
+{"cv.mulhhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSN, MASK_CV_MULHHSN, match_opcode, 0},
+{"cv.mulhhs", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHSN, MASK_CV_MULHHSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSRN, MASK_CV_MULHHSRN, match_opcode, 0},
+{"cv.mulun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULUN, MASK_CV_MULUN, match_opcode, 0},
+{"cv.mulu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULUN, MASK_CV_MULUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULURN, MASK_CV_MULURN, match_opcode, 0},
+{"cv.mulhhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHUN, MASK_CV_MULHHUN, match_opcode, 0},
+{"cv.mulhhu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHUN, MASK_CV_MULHHUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHURN, MASK_CV_MULHHURN, match_opcode, 0},
+{"cv.macsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSN, MASK_CV_MACSN, match_opcode, 0},
+{"cv.machhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSN, MASK_CV_MACHHSN, match_opcode, 0},
+{"cv.macsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSRN, MASK_CV_MACSRN, match_opcode, 0},
+{"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSRN, MASK_CV_MACHHSRN, match_opcode, 0},
+{"cv.macun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACUN, MASK_CV_MACUN, match_opcode, 0},
+{"cv.machhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHUN, MASK_CV_MACHHUN, match_opcode, 0},
+{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN, MASK_CV_MACURN, match_opcode, 0},
+{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/2] RISC-V: Add support for XCValu extension in CV32E40P
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
2023-09-12 14:24 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
@ 2023-09-12 14:24 ` Mary Bennett
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2 siblings, 0 replies; 16+ messages in thread
From: Mary Bennett @ 2023-09-12 14:24 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, nelson, research_trasio
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
* testsuite/gas/riscv/cv-alu-insns.d: New test.
* testsuite/gas/riscv/cv-alu-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble xcb operand.
* riscv-opc.c: Defined the MASK and added XCValu instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCValu.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for XCValu.
(enum riscv_insn_class): Added the XCValu instruction class.
---
bfd/elfxx-riscv.c | 5 +
gas/config/tc-riscv.c | 14 ++
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 +++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 ++++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 ++++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 +++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 +++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++++++
include/opcode/riscv-opc.h | 67 ++++++++++
include/opcode/riscv.h | 5 +
opcodes/riscv-dis.c | 4 +
opcodes/riscv-opc.c | 35 +++++
36 files changed, 787 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a3c32941866..45bd914d0c1 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1349,6 +1349,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
/* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2543,6 +2544,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "h");
case INSN_CLASS_XCVMAC:
return riscv_subset_supports (rps, "xcvmac");
+ case INSN_CLASS_XCVALU:
+ return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2785,6 +2788,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("h");
case INSN_CLASS_XCVMAC:
return "xcvmac";
+ case INSN_CLASS_XCVALU:
+ return "xcvalu";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3dd6123c79b..fdc613e0350 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1455,6 +1455,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ /* ls2[4:0] */
+ used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
+ break;
case '3':
used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
break;
@@ -3646,6 +3650,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number<0
+ || imm_expr->X_add_number>31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+ continue;
case '3':
my_getExpression (imm_expr, asarg);
check_absolute_expr (ip, imm_expr, FALSE);
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 1dcdeeb7b36..61e744ae633 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvmac extension provides instructions for multiply-accumulate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+@item Xcvalu
+The Xcvalu extension provides instructions for general ALU operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
new file mode 100644
index 00000000000..907b043aebc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-boundaries.s
+#error_output: cv-alu-boundaries.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
new file mode 100644
index 00000000000..fae4022244c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subnr 10,t3,t6'
+.*: Error: illegal operands `cv.addrnr t4,26,t6'
+.*: Error: illegal operands `cv.subunr t6,t3,15'
+.*: Error: instruction cv.clipu requires absolute expression
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: illegal operands `cv.clipu t0,t3,-10'
+.*: Error: illegal operands `cv.clipu t0,t3,500'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
+.*: Error: illegal operands `cv.addn t0,t3,t6,302'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
+.*: Error: illegal operands `cv.addn t0,t3,t6,32'
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
new file mode 100644
index 00000000000..bb4da949b4a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
@@ -0,0 +1,27 @@
+# Destination must be of type register
+target:
+ cv.subnr 10, t3, t6
+# Source 1 must be of type register
+ cv.addrnr t4, 26, t6
+# Source 2 must be of type register
+ cv.subunr t6, t3, 15
+# Five bit immediate must be an absolute value
+ cv.clipu t0, t3, t6
+# Five bit immediate must be an absolute value
+ cv.addn t0, t3, t6, t2
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -10
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 500
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -60
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 302
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 32
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 32
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
new file mode 100644
index 00000000000..963aa4012da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-alu-fail-march.s
+#error_output: cv-alu-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
new file mode 100644
index 00000000000..11e5a7cd279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' required
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
new file mode 100644
index 00000000000..8dd39b7301f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
@@ -0,0 +1,33 @@
+# Absence of xcv or xcvalu march option disables all CORE-V general ALU ops extensions
+target:
+ cv.abs t4,t2
+ cv.slet t4,t2,t6
+ cv.sletu t4,t2,t6
+ cv.min t4,t2,t6
+ cv.minu t4,t2,t6
+ cv.max t4,t2,t6
+ cv.maxu t4,t2,t6
+ cv.exths t4,t2
+ cv.exthz t4,t2
+ cv.extbs t4,t2
+ cv.extbz t4,t2
+ cv.clip t4,t2,5
+ cv.clipu t4,t2,5
+ cv.clipr t4,t2,t6
+ cv.clipur t4,t2,t6
+ cv.addn t4, t2, t0, 4
+ cv.addun t4, t2, t0, 4
+ cv.addrn t6, t0, t3, 9
+ cv.addurn t6, t0, t3, 14
+ cv.addnr t6, t0, t3
+ cv.addunr t6, t0, t3
+ cv.addrnr t6, t0, t3
+ cv.addurnr t6, t0, t3
+ cv.subn t6, t0, t3, 6
+ cv.subun t6, t0, t3, 24
+ cv.subrn t6, t0, t3, 21
+ cv.suburn t6, t0, t3, 3
+ cv.subnr t6, t0, t3
+ cv.subunr t6, t0, t3
+ cv.subrnr t6, t0, t3
+ cv.suburnr t6, t0, t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
new file mode 100644
index 00000000000..81b17348c32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-01.s
+#error_output: cv-alu-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
new file mode 100644
index 00000000000..f670e4341fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs 5,t2'
+.*: Error: illegal operands `cv.slet 10,t2,t6'
+.*: Error: illegal operands `cv.sletu 11,t2,t6'
+.*: Error: illegal operands `cv.min 15,t2,t6'
+.*: Error: illegal operands `cv.minu 16,t2,t6'
+.*: Error: illegal operands `cv.max 8,t2,t6'
+.*: Error: illegal operands `cv.maxu 3,t2,t6'
+.*: Error: illegal operands `cv.exths 2,t2'
+.*: Error: illegal operands `cv.exthz 6,t2'
+.*: Error: illegal operands `cv.extbs 4,t2'
+.*: Error: illegal operands `cv.extbz 7,t2'
+.*: Error: illegal operands `cv.clip 17,t2,5'
+.*: Error: illegal operands `cv.clipu 11,t2,5'
+.*: Error: illegal operands `cv.clipr 16,t2,t6'
+.*: Error: illegal operands `cv.clipur 15,t2,t6'
+.*: Error: illegal operands `cv.addn 9,t2,t0,4'
+.*: Error: illegal operands `cv.addun 30,t2,t0,4'
+.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
+.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
+.*: Error: illegal operands `cv.addnr 2,t0,t3'
+.*: Error: illegal operands `cv.addunr 26,t0,t3'
+.*: Error: illegal operands `cv.addrnr 3,t0,t3'
+.*: Error: illegal operands `cv.addurnr 14,t0,t3'
+.*: Error: illegal operands `cv.subn 15,t0,t3,6'
+.*: Error: illegal operands `cv.subun 9,t0,t3,24'
+.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
+.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
+.*: Error: illegal operands `cv.subnr 3,t0,t3'
+.*: Error: illegal operands `cv.subunr 12,t0,t3'
+.*: Error: illegal operands `cv.subrnr 13,t0,t3'
+.*: Error: illegal operands `cv.suburnr 8,t0,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
new file mode 100644
index 00000000000..7920ebd53ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
@@ -0,0 +1,33 @@
+# Destination must be of type register
+target:
+ cv.abs 5,t2
+ cv.slet 10,t2,t6
+ cv.sletu 11,t2,t6
+ cv.min 15,t2,t6
+ cv.minu 16,t2,t6
+ cv.max 8,t2,t6
+ cv.maxu 3,t2,t6
+ cv.exths 2,t2
+ cv.exthz 6,t2
+ cv.extbs 4,t2
+ cv.extbz 7,t2
+ cv.clip 17,t2,5
+ cv.clipu 11,t2,5
+ cv.clipr 16,t2,t6
+ cv.clipur 15,t2,t6
+ cv.addn 9,t2,t0,4
+ cv.addun 30,t2,t0,4
+ cv.addrn 21,t0,t3,9
+ cv.addurn 6,t0,t3,14
+ cv.addnr 2,t0,t3
+ cv.addunr 26,t0,t3
+ cv.addrnr 3,t0,t3
+ cv.addurnr 14,t0,t3
+ cv.subn 15,t0,t3,6
+ cv.subun 9,t0,t3,24
+ cv.subrn 24,t0,t3,21
+ cv.suburn 25,t0,t3,3
+ cv.subnr 3,t0,t3
+ cv.subunr 12,t0,t3
+ cv.subrnr 13,t0,t3
+ cv.suburnr 8,t0,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
new file mode 100644
index 00000000000..46645aaf864
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-02.s
+#error_output: cv-alu-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
new file mode 100644
index 00000000000..0a888c7251b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs t4,5'
+.*: Error: illegal operands `cv.slet t4,7,t6'
+.*: Error: illegal operands `cv.sletu t4,3,t6'
+.*: Error: illegal operands `cv.min t4,5,t6'
+.*: Error: illegal operands `cv.minu t4,3,t6'
+.*: Error: illegal operands `cv.max t4,4,t6'
+.*: Error: illegal operands `cv.maxu t4,6,t6'
+.*: Error: illegal operands `cv.exths t4,30'
+.*: Error: illegal operands `cv.exthz t4,23'
+.*: Error: illegal operands `cv.extbs t4,25'
+.*: Error: illegal operands `cv.extbz t4,21'
+.*: Error: illegal operands `cv.clip t4,2,5'
+.*: Error: illegal operands `cv.clipu t4,16,5'
+.*: Error: illegal operands `cv.clipr t4,17,t6'
+.*: Error: illegal operands `cv.clipur t4,14,t6'
+.*: Error: illegal operands `cv.addn t4,5,t0,4'
+.*: Error: illegal operands `cv.addun t4,18,t0,4'
+.*: Error: illegal operands `cv.addrn t6,19,t3,9'
+.*: Error: illegal operands `cv.addurn t6,4,t3,14'
+.*: Error: illegal operands `cv.addnr t6,6,t3'
+.*: Error: illegal operands `cv.addunr t6,7,t3'
+.*: Error: illegal operands `cv.addrnr t6,9,t3'
+.*: Error: illegal operands `cv.addurnr t6,5,t3'
+.*: Error: illegal operands `cv.subn t6,11,t3,6'
+.*: Error: illegal operands `cv.subun t6,14,t3,24'
+.*: Error: illegal operands `cv.subrn t6,15,t3,21'
+.*: Error: illegal operands `cv.suburn t6,24,t3,3'
+.*: Error: illegal operands `cv.subnr t6,4,t3'
+.*: Error: illegal operands `cv.subunr t6,8,t3'
+.*: Error: illegal operands `cv.subrnr t6,7,t3'
+.*: Error: illegal operands `cv.suburnr t6,6,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
new file mode 100644
index 00000000000..6083f1f5044
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
@@ -0,0 +1,33 @@
+# Source 1 must be of type register
+target:
+ cv.abs t4,5
+ cv.slet t4,7,t6
+ cv.sletu t4,3,t6
+ cv.min t4,5,t6
+ cv.minu t4,3,t6
+ cv.max t4,4,t6
+ cv.maxu t4,6,t6
+ cv.exths t4,30
+ cv.exthz t4,23
+ cv.extbs t4,25
+ cv.extbz t4,21
+ cv.clip t4,2,5
+ cv.clipu t4,16,5
+ cv.clipr t4,17,t6
+ cv.clipur t4,14,t6
+ cv.addn t4,5,t0,4
+ cv.addun t4,18,t0,4
+ cv.addrn t6,19,t3,9
+ cv.addurn t6,4,t3,14
+ cv.addnr t6,6,t3
+ cv.addunr t6,7,t3
+ cv.addrnr t6,9,t3
+ cv.addurnr t6,5,t3
+ cv.subn t6,11,t3,6
+ cv.subun t6,14,t3,24
+ cv.subrn t6,15,t3,21
+ cv.suburn t6,24,t3,3
+ cv.subnr t6,4,t3
+ cv.subunr t6,8,t3
+ cv.subrnr t6,7,t3
+ cv.suburnr t6,6,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
new file mode 100644
index 00000000000..6f681289d12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-03.s
+#error_output: cv-alu-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
new file mode 100644
index 00000000000..c7a11184996
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.slet t4,t2,3'
+.*: Error: illegal operands `cv.sletu t4,t2,4'
+.*: Error: illegal operands `cv.min t4,t2,13'
+.*: Error: illegal operands `cv.minu t4,t2,7'
+.*: Error: illegal operands `cv.max t4,t2,17'
+.*: Error: illegal operands `cv.maxu t4,t2,30'
+.*: Error: illegal operands `cv.clipr t4,t2,18'
+.*: Error: illegal operands `cv.clipur t4,t2,29'
+.*: Error: illegal operands `cv.addn t4,t2,24,4'
+.*: Error: illegal operands `cv.addun t4,t2,6,4'
+.*: Error: illegal operands `cv.addrn t6,t0,7,9'
+.*: Error: illegal operands `cv.addurn t6,t0,18,14'
+.*: Error: illegal operands `cv.addnr t6,t0,15'
+.*: Error: illegal operands `cv.addunr t6,t0,24'
+.*: Error: illegal operands `cv.addrnr t6,t0,3'
+.*: Error: illegal operands `cv.addurnr t6,t0,2'
+.*: Error: illegal operands `cv.subn t6,t0,1,6'
+.*: Error: illegal operands `cv.subun t6,t0,8,24'
+.*: Error: illegal operands `cv.subrn t6,t0,18,21'
+.*: Error: illegal operands `cv.suburn t6,t0,25,3'
+.*: Error: illegal operands `cv.subnr t6,t0,14'
+.*: Error: illegal operands `cv.subunr t6,t0,7'
+.*: Error: illegal operands `cv.subrnr t6,t0,18'
+.*: Error: illegal operands `cv.suburnr t6,t0,26'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
new file mode 100644
index 00000000000..64ee8703579
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
@@ -0,0 +1,26 @@
+# Source 2 must be of type register
+target:
+ cv.slet t4,t2,3
+ cv.sletu t4,t2,4
+ cv.min t4,t2,13
+ cv.minu t4,t2,7
+ cv.max t4,t2,17
+ cv.maxu t4,t2,30
+ cv.clipr t4,t2,18
+ cv.clipur t4,t2,29
+ cv.addn t4,t2,24,4
+ cv.addun t4,t2,6,4
+ cv.addrn t6,t0,7,9
+ cv.addurn t6,t0,18,14
+ cv.addnr t6,t0,15
+ cv.addunr t6,t0,24
+ cv.addrnr t6,t0,3
+ cv.addurnr t6,t0,2
+ cv.subn t6,t0,1,6
+ cv.subun t6,t0,8,24
+ cv.subrn t6,t0,18,21
+ cv.suburn t6,t0,25,3
+ cv.subnr t6,t0,14
+ cv.subunr t6,t0,7
+ cv.subrnr t6,t0,18
+ cv.suburnr t6,t0,26
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
new file mode 100644
index 00000000000..634d9bfe091
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-04.s
+#error_output: cv-alu-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
new file mode 100644
index 00000000000..d6fd960f9e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.clip requires absolute expression
+.*: Error: instruction cv.clipu requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
new file mode 100644
index 00000000000..b97d52a77ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
@@ -0,0 +1,4 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.clip t4,t2,t3
+ cv.clipu t4,t2,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
new file mode 100644
index 00000000000..1b90d3e5757
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-05.s
+#error_output: cv-alu-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
new file mode 100644
index 00000000000..05b5289e743
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: instruction cv.addun requires absolute expression
+.*: Error: instruction cv.addrn requires absolute expression
+.*: Error: instruction cv.addurn requires absolute expression
+.*: Error: instruction cv.subn requires absolute expression
+.*: Error: instruction cv.subun requires absolute expression
+.*: Error: instruction cv.subrn requires absolute expression
+.*: Error: instruction cv.suburn requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
new file mode 100644
index 00000000000..1b0ac6f2d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.addn t4,t2,t0,t3
+ cv.addun t4,t2,t0,t3
+ cv.addrn t6,t0,t3,t2
+ cv.addurn t6,t0,t3,t2
+ cv.subn t6,t0,t3,t2
+ cv.subun t6,t0,t3,t2
+ cv.subrn t6,t0,t3,t2
+ cv.suburn t6,t0,t3,t2
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
new file mode 100644
index 00000000000..0a49e682c85
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-06.s
+#error_output: cv-alu-fail-operand-06.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
new file mode 100644
index 00000000000..d8059cb5e3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.clip t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clip t0,t3,-400'
+.*: Error: illegal operands `cv.clipu t0,t3,-985'
+.*: Error: illegal operands `cv.clip t0,t3,32'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.clip t0,t3,859'
+.*: Error: illegal operands `cv.clipu t0,t3,7283'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
new file mode 100644
index 00000000000..1b810bdda55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.clip t0,t3,-1
+ cv.clipu t0,t3,-1
+ cv.clip t0,t3,-400
+ cv.clipu t0,t3,-985
+ cv.clip t0,t3,32
+ cv.clipu t0,t3,32
+ cv.clip t0,t3,859
+ cv.clipu t0,t3,7283
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
new file mode 100644
index 00000000000..06d17fede7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-07.s
+#error_output: cv-alu-fail-operand-07.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
new file mode 100644
index 00000000000..5a34156afc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
+.*: Error: illegal operands `cv.addn t4,t2,t0,32'
+.*: Error: illegal operands `cv.addun t4,t2,t0,32'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subun t6,t0,t3,32'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addn t4,t2,t0,320'
+.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
+.*: Error: illegal operands `cv.subn t6,t0,t3,89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
new file mode 100644
index 00000000000..04788f69ddd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
@@ -0,0 +1,34 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.addn t4,t2,t0,-1
+ cv.addun t4,t2,t0,-1
+ cv.addrn t6,t0,t3,-1
+ cv.addurn t6,t0,t3,-1
+ cv.subn t6,t0,t3,-1
+ cv.subun t6,t0,t3,-1
+ cv.subrn t6,t0,t3,-1
+ cv.suburn t6,t0,t3,-1
+ cv.addn t4,t2,t0,-34
+ cv.addun t4,t2,t0,-3556
+ cv.addrn t6,t0,t3,-212
+ cv.addurn t6,t0,t3,-6584
+ cv.subn t6,t0,t3,-89
+ cv.subun t6,t0,t3,-9034
+ cv.subrn t6,t0,t3,-234
+ cv.suburn t6,t0,t3,-284
+ cv.addn t4,t2,t0,32
+ cv.addun t4,t2,t0,32
+ cv.addrn t6,t0,t3,32
+ cv.addurn t6,t0,t3,32
+ cv.subn t6,t0,t3,32
+ cv.subun t6,t0,t3,32
+ cv.subrn t6,t0,t3,32
+ cv.suburn t6,t0,t3,32
+ cv.addn t4,t2,t0,320
+ cv.addun t4,t2,t0,34534
+ cv.addrn t6,t0,t3,254
+ cv.addurn t6,t0,t3,398
+ cv.subn t6,t0,t3,89
+ cv.subun t6,t0,t3,3489
+ cv.subrn t6,t0,t3,143
+ cv.suburn t6,t0,t3,234
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d b/gas/testsuite/gas/riscv/cv-alu-insns.d
new file mode 100644
index 00000000000..784cf5ca6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.d
@@ -0,0 +1,102 @@
+#as: -march=rv32i_xcvalu
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
+[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
+[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
+[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
+[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
+[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
+[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
+[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
+[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
+[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
+[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
+[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
+[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
+[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
+[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
+[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
+[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
+[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
+[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
+[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
+[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
+[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
+[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
+[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
+[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
+[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
+[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
+[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
+[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
+[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
+[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
+[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
+[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
+[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
+[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
+[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
+[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
+[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
+[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
+[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
+[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
+[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
+[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
+[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
+[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
+[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
+[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
+[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
+[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
+[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
+[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
+[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
+[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
+[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
+[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
+[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
+[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
+[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
+[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
+[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
+[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
+[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
+[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
+[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
+[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
+[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
+[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
+[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
+[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
+[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
+[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
+[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
+[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
+[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
+[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
+[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
+[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
+[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
+[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
+[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
+[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
+[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
+[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
+[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
+[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
+[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
+[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
+[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
+[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
+[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s b/gas/testsuite/gas/riscv/cv-alu-insns.s
new file mode 100644
index 00000000000..82ea0c3b98d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.s
@@ -0,0 +1,124 @@
+target:
+ cv.abs t0,t1
+ cv.abs t4,t2
+ cv.abs t3,t5
+
+ cv.addnr t0, t3, t6
+ cv.addnr t6, t0, t3
+ cv.addnr t3, t6, t0
+
+ cv.addn t0, t1, t2, 0
+ cv.addn t4, t2, t0, 4
+ cv.addn t3, t5, t1, 31
+
+ cv.addrnr t0, t3, t6
+ cv.addrnr t6, t0, t3
+ cv.addrnr t3, t6, t0
+
+ cv.addrn t0, t3, t6, 0
+ cv.addrn t6, t0, t3, 9
+ cv.addrn t3, t6, t0, 31
+
+ cv.addunr t0, t3, t6
+ cv.addunr t6, t0, t3
+ cv.addunr t3, t6, t0
+
+ cv.addun t0, t1, t2, 0
+ cv.addun t4, t2, t0, 4
+ cv.addun t3, t5, t1, 31
+
+ cv.addurnr t0, t3, t6
+ cv.addurnr t6, t0, t3
+ cv.addurnr t3, t6, t0
+
+ cv.addurn t0, t3, t6, 0
+ cv.addurn t6, t0, t3, 14
+ cv.addurn t3, t6, t0, 31
+
+ cv.clipr t0,t1,t2
+ cv.clipr t4,t2,t6
+ cv.clipr t3,t5,t1
+
+ cv.clip t0,t1,0
+ cv.clip t4,t2,5
+ cv.clip t3,t5,31
+
+ cv.clipur t0,t1,t2
+ cv.clipur t4,t2,t6
+ cv.clipur t3,t5,t1
+
+ cv.clipu t0,t1,0
+ cv.clipu t4,t2,5
+ cv.clipu t3,t5,31
+
+ cv.extbs t0,t1
+ cv.extbs t4,t2
+ cv.extbs t3,t5
+
+ cv.extbz t0,t1
+ cv.extbz t4,t2
+ cv.extbz t3,t5
+
+ cv.exths t0,t1
+ cv.exths t4,t2
+ cv.exths t3,t5
+
+ cv.exthz t0,t1
+ cv.exthz t4,t2
+ cv.exthz t3,t5
+
+ cv.max t0,t1,t2
+ cv.max t4,t2,t6
+ cv.max t3,t5,t1
+
+ cv.maxu t0,t1,t2
+ cv.maxu t4,t2,t6
+ cv.maxu t3,t5,t1
+
+ cv.min t0,t1,t2
+ cv.min t4,t2,t6
+ cv.min t3,t5,t1
+
+ cv.minu t0,t1,t2
+ cv.minu t4,t2,t6
+ cv.minu t3,t5,t1
+
+ cv.sle t0,t1,t2
+ cv.sle t4,t2,t6
+ cv.sle t3,t5,t1
+
+ cv.sleu t0,t1,t2
+ cv.sleu t4,t2,t6
+ cv.sleu t3,t5,t1
+
+ cv.subnr t0, t3, t6
+ cv.subnr t6, t0, t3
+ cv.subnr t3, t6, t0
+
+ cv.subn t0, t3, t6, 0
+ cv.subn t6, t0, t3, 6
+ cv.subn t3, t6, t0, 31
+
+ cv.subrnr t0, t3, t6
+ cv.subrnr t6, t0, t3
+ cv.subrnr t3, t6, t0
+
+ cv.subrn t0, t3, t6, 0
+ cv.subrn t6, t0, t3, 21
+ cv.subrn t3, t6, t0, 31
+
+ cv.subunr t0, t3, t6
+ cv.subunr t6, t0, t3
+ cv.subunr t3, t6, t0
+
+ cv.subun t0, t3, t6, 0
+ cv.subun t6, t0, t3, 24
+ cv.subun t3, t6, t0, 31
+
+ cv.suburnr t0, t3, t6
+ cv.suburnr t6, t0, t3
+ cv.suburnr t3, t6, t0
+
+ cv.suburn t0, t3, t6, 0
+ cv.suburn t6, t0, t3, 3
+ cv.suburn t3, t6, t0, 31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ce935336588..5e29ff90055 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2357,6 +2357,73 @@
#define MASK_CV_MACURN 0xc000707f
#define MATCH_CV_MACHHURN 0xc000705b
#define MASK_CV_MACHHURN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+#define MATCH_CV_ABS 0x5000302b
+#define MASK_CV_ABS 0xfff0707f
+#define MATCH_CV_SLE 0x5200302b
+#define MASK_CV_SLE 0xfe00707f
+#define MATCH_CV_SLET 0x5200302b
+#define MASK_CV_SLET 0xfe00707f
+#define MATCH_CV_SLEU 0x5400302b
+#define MASK_CV_SLEU 0xfe00707f
+#define MATCH_CV_SLETU 0x5400302b
+#define MASK_CV_SLETU 0xfe00707f
+#define MATCH_CV_MIN 0x5600302b
+#define MASK_CV_MIN 0xfe00707f
+#define MATCH_CV_MINU 0x5800302b
+#define MASK_CV_MINU 0xfe00707f
+#define MATCH_CV_MAX 0x5a00302b
+#define MASK_CV_MAX 0xfe00707f
+#define MATCH_CV_MAXU 0x5c00302b
+#define MASK_CV_MAXU 0xfe00707f
+#define MATCH_CV_EXTHS 0x6000302b
+#define MASK_CV_EXTHS 0xfff0707f
+#define MATCH_CV_EXTHZ 0x6200302b
+#define MASK_CV_EXTHZ 0xfff0707f
+#define MATCH_CV_EXTBS 0x6400302b
+#define MASK_CV_EXTBS 0xfff0707f
+#define MATCH_CV_EXTBZ 0x6600302b
+#define MASK_CV_EXTBZ 0xfff0707f
+#define MATCH_CV_CLIP 0x7000302b
+#define MASK_CV_CLIP 0xfe00707f
+#define MATCH_CV_CLIPU 0x7200302b
+#define MASK_CV_CLIPU 0xfe00707f
+#define MATCH_CV_CLIPR 0x7400302b
+#define MASK_CV_CLIPR 0xfe00707f
+#define MATCH_CV_CLIPUR 0x7600302b
+#define MASK_CV_CLIPUR 0xfe00707f
+#define MATCH_CV_ADDNR 0x8000302b
+#define MASK_CV_ADDNR 0xfe00707f
+#define MATCH_CV_ADDUNR 0x8200302b
+#define MASK_CV_ADDUNR 0xfe00707f
+#define MATCH_CV_ADDRNR 0x8400302b
+#define MASK_CV_ADDRNR 0xfe00707f
+#define MATCH_CV_ADDURNR 0x8600302b
+#define MASK_CV_ADDURNR 0xfe00707f
+#define MATCH_CV_SUBNR 0x8800302b
+#define MASK_CV_SUBNR 0xfe00707f
+#define MATCH_CV_SUBUNR 0x8a00302b
+#define MASK_CV_SUBUNR 0xfe00707f
+#define MATCH_CV_SUBRNR 0x8c00302b
+#define MASK_CV_SUBRNR 0xfe00707f
+#define MATCH_CV_SUBURNR 0x8e00302b
+#define MASK_CV_SUBURNR 0xfe00707f
+#define MATCH_CV_ADDN 0x205b
+#define MASK_CV_ADDN 0xc000707f
+#define MATCH_CV_ADDUN 0x4000205b
+#define MASK_CV_ADDUN 0xc000707f
+#define MATCH_CV_ADDRN 0x8000205b
+#define MASK_CV_ADDRN 0xc000707f
+#define MATCH_CV_ADDURN 0xc000205b
+#define MASK_CV_ADDURN 0xc000707f
+#define MATCH_CV_SUBN 0x305b
+#define MASK_CV_SUBN 0xc000707f
+#define MATCH_CV_SUBUN 0x4000305b
+#define MASK_CV_SUBUN 0xc000707f
+#define MATCH_CV_SUBRN 0x8000305b
+#define MASK_CV_SUBRN 0xc000707f
+#define MATCH_CV_SUBURN 0xc000305b
+#define MASK_CV_SUBURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5097d2cf6c1..18236a6150c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS2_UIMM5(x) \
+ (RV_X(x, 20, 5))
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
@@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS2_UIMM5(x) \
+ (RV_X(x, 0, 5) << 20)
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
@@ -450,6 +454,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
+ INSN_CLASS_XCVALU,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2b328f138e9..c2da1d5bb9b 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -654,6 +654,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS2_UIMM5 (l)));
+ break;
case '3':
print (info->stream, dis_style_immediate, "%d",
((int) EXTRACT_CV_IS3_UIMM5 (l)));
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2386b47f16a..5c68353e5a1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2065,6 +2065,41 @@ const struct riscv_opcode riscv_opcodes[] =
{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN, MASK_CV_MACURN, match_opcode, 0},
{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0},
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0},
+{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, MASK_CV_EXTHS, match_opcode, 0},
+{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_EXTHZ, match_opcode, 0},
+{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, MASK_CV_EXTBS, match_opcode, 0},
+{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_EXTBZ, match_opcode, 0},
+{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLE, MASK_CV_SLE, match_opcode, 0},
+{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS},
+{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLEU, MASK_CV_SLEU, match_opcode, 0},
+{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLETU, match_opcode, INSN_ALIAS},
+{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, MASK_CV_MIN, match_opcode, 0},
+{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, MASK_CV_MINU, match_opcode, 0},
+{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, MASK_CV_MAX, match_opcode, 0},
+{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_MAXU, match_opcode, 0},
+{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIP, MASK_CV_CLIP, match_opcode, 0},
+{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIPU, MASK_CV_CLIPU, match_opcode, 0},
+{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_CLIPR, match_opcode, 0},
+{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_CLIPUR, match_opcode, 0},
+{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDUN, MASK_CV_ADDUN, match_opcode, 0},
+{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_ADDUNR, match_opcode, 0},
+{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDRN, MASK_CV_ADDRN, match_opcode, 0},
+{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDURN, MASK_CV_ADDURN, match_opcode, 0},
+{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_ADDNR, match_opcode, 0},
+{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_ADDRNR, match_opcode, 0},
+{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_ADDURNR, match_opcode, 0},
+{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBN, MASK_CV_SUBN, match_opcode, 0},
+{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBUN, MASK_CV_SUBUN, match_opcode, 0},
+{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBRN, MASK_CV_SUBRN, match_opcode, 0},
+{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBURN, MASK_CV_SUBURN, match_opcode, 0},
+{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SUBNR, match_opcode, 0},
+{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SUBUNR, match_opcode, 0},
+{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SUBRNR, match_opcode, 0},
+{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
2023-09-12 14:24 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-12 14:24 ` [PATCH v2 2/2] RISC-V: Add support for XCValu " Mary Bennett
@ 2023-10-02 2:02 ` Mary Bennett
2023-10-02 2:02 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
` (2 more replies)
2 siblings, 3 replies; 16+ messages in thread
From: Mary Bennett @ 2023-10-02 2:02 UTC (permalink / raw)
To: binutils; +Cc: mary.bennett
Changes: v2 -> v3
- Rebase against 7a5fa3dbe555794ce401a7435cb91f8695fc9847.
Changes: v1 -> v2
- Added MASK_<INSN> for each instruction, as suggested.
- Changed operand 'x' to operand 'X', as suggested.
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
[2] github.com/openhwgroup/corev-binutils-gdb
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Add support for XCValu extension in CV32E40P
RISC-V: Add support for XCVmac extension in CV32E40P
bfd/elfxx-riscv.c | 11 ++
gas/config/tc-riscv.c | 42 ++++-
gas/doc/c-riscv.texi | 10 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 +
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 +
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 104 ++++++++++++
include/opcode/riscv.h | 12 ++
opcodes/riscv-dis.c | 14 +-
opcodes/riscv-opc.c | 61 +++++++
44 files changed, 1428 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
@ 2023-10-02 2:02 ` Mary Bennett
2023-10-02 2:02 ` [PATCH v3 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-11-06 17:27 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2 siblings, 0 replies; 16+ messages in thread
From: Mary Bennett @ 2023-10-02 2:02 UTC (permalink / raw)
To: binutils; +Cc: mary.bennett
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
---
bfd/elfxx-riscv.c | 6 +
gas/config/tc-riscv.c | 28 +++-
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 37 +++++
include/opcode/riscv.h | 7 +
opcodes/riscv-dis.c | 10 +-
opcodes/riscv-opc.c | 26 +++
15 files changed, 641 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6ed657171f0..6f1e66a09dc 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1351,6 +1351,8 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
+ /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
+ {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2549,6 +2551,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
+ case INSN_CLASS_XCVMAC:
+ return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2789,6 +2793,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
+ case INSN_CLASS_XCVMAC:
+ return "xcvmac";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 0b8ecf96681..db3dc297302 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1481,6 +1481,16 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
}
}
break;
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
+ break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
default:
goto unknown_validate_operand;
}
@@ -3649,7 +3659,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
}
break;
-
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number > 31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
+ continue;
+ default:
+ goto unknown_riscv_ip_operand;
+ }
+ break;
default:
goto unknown_riscv_ip_operand;
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 7921556a4f7..5aa511de999 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -745,6 +745,11 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
+@item Xcvmac
+The Xcvmac extension provides instructions for multiply-accumulate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.d b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
new file mode 100644
index 00000000000..eb6352f85f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-mac-fail-march.s
+#error_output: cv-mac-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.l b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
new file mode 100644
index 00000000000..d2bc12c804a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.l
@@ -0,0 +1,23 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.mac t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.msu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.muls t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhs t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsn t4,t2,t0,4', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsn t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulsrn t4,t2,t0,10', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhsrn t4,t2,t0,17', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhu t4,t2,t0', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulun t4,t2,t0,7', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhun t4,t2,t0,16', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulurn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.mulhhurn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsn t4,t2,t0,11', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macsrn t4,t2,t0,9', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhsrn t4,t2,t0,24', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macun t4,t2,t0,27', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhun t4,t2,t0,18', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.macurn t4,t2,t0,25', extension `xcvmac' required
+.*: Error: unrecognized opcode `cv.machhurn t4,t2,t0,5', extension `xcvmac' required
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-march.s b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
new file mode 100644
index 00000000000..78b08423a64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-march.s
@@ -0,0 +1,24 @@
+# Absence of the xcvmac march option disables all CORE-V MAC extensions.
+target:
+ cv.mac t4, t2, t0
+ cv.msu t4, t2, t0
+ cv.muls t4, t2, t0
+ cv.mulhhs t4, t2, t0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulu t4, t2, t0
+ cv.mulhhu t4, t2, t0
+ cv.mulun t4, t2, t0, 7
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulurn t4, t2, t0, 11
+ cv.mulhhurn t4, t2, t0, 9
+ cv.macsn t4, t2, t0, 24
+ cv.machhsn t4, t2, t0, 11
+ cv.macsrn t4, t2, t0, 9
+ cv.machhsrn t4, t2, t0, 24
+ cv.macun t4, t2, t0, 27
+ cv.machhun t4, t2, t0, 18
+ cv.macurn t4, t2, t0, 25
+ cv.machhurn t4, t2, t0, 5
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.d b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
new file mode 100644
index 00000000000..51e1b3052c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvmac
+#source: cv-mac-fail-operand.s
+#error_output: cv-mac-fail-operand.l
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.l b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
new file mode 100644
index 00000000000..645949696cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.l
@@ -0,0 +1,147 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.mac 8,t2,t0'
+.*: Error: illegal operands `cv.msu 23,t2,t0'
+.*: Error: illegal operands `cv.muls 43,t2,t0'
+.*: Error: illegal operands `cv.mulhhs 7,t2,t0'
+.*: Error: illegal operands `cv.mulsn 345,t2,t0,4'
+.*: Error: illegal operands `cv.mulhhsn 356,t2,t0,16'
+.*: Error: illegal operands `cv.mulsrn 867,t2,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn 3454,t2,t0,17'
+.*: Error: illegal operands `cv.mulu 9,t2,t0'
+.*: Error: illegal operands `cv.mulhhu 54,t2,t0'
+.*: Error: illegal operands `cv.mulun 965,t2,t0,7'
+.*: Error: illegal operands `cv.mulhhun 35,t2,t0,16'
+.*: Error: illegal operands `cv.mulurn 87,t2,t0,11'
+.*: Error: illegal operands `cv.mulhhurn 38,t2,t0,9'
+.*: Error: illegal operands `cv.macsn 985,t2,t0,24'
+.*: Error: illegal operands `cv.machhsn 83,t2,t0,11'
+.*: Error: illegal operands `cv.macsrn 960,t2,t0,9'
+.*: Error: illegal operands `cv.machhsrn 385,t2,t0,24'
+.*: Error: illegal operands `cv.macun 58,t2,t0,27'
+.*: Error: illegal operands `cv.machhun 6,t2,t0,18'
+.*: Error: illegal operands `cv.macurn 35,t2,t0,25'
+.*: Error: illegal operands `cv.machhurn 67,t2,t0,5'
+.*: Error: illegal operands `cv.mac t4,43,t0'
+.*: Error: illegal operands `cv.msu t4,3,t0'
+.*: Error: illegal operands `cv.muls t4,345,t0'
+.*: Error: illegal operands `cv.mulhhs t4,54,t0'
+.*: Error: illegal operands `cv.mulsn t4,4,t0,4'
+.*: Error: illegal operands `cv.mulhhsn t4,35,t0,16'
+.*: Error: illegal operands `cv.mulsrn t4,53,t0,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,4456,t0,17'
+.*: Error: illegal operands `cv.mulu t4,868,t0'
+.*: Error: illegal operands `cv.mulhhu t4,95,t0'
+.*: Error: illegal operands `cv.mulun t4,584,t0,7'
+.*: Error: illegal operands `cv.mulhhun t4,37545,t0,16'
+.*: Error: illegal operands `cv.mulurn t4,943,t0,11'
+.*: Error: illegal operands `cv.mulhhurn t4,34,t0,9'
+.*: Error: illegal operands `cv.macsn t4,93,t0,24'
+.*: Error: illegal operands `cv.machhsn t4,584,t0,11'
+.*: Error: illegal operands `cv.macsrn t4,28,t0,9'
+.*: Error: illegal operands `cv.machhsrn t4,9,t0,24'
+.*: Error: illegal operands `cv.macun t4,834,t0,27'
+.*: Error: illegal operands `cv.machhun t4,92,t0,18'
+.*: Error: illegal operands `cv.macurn t4,49,t0,25'
+.*: Error: illegal operands `cv.machhurn t4,6,t0,5'
+.*: Error: illegal operands `cv.mac t4,t2,344'
+.*: Error: illegal operands `cv.msu t4,t2,23'
+.*: Error: illegal operands `cv.muls t4,t2,2'
+.*: Error: illegal operands `cv.mulhhs t4,t2,8'
+.*: Error: illegal operands `cv.mulsn t4,t2,45,4'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,655,16'
+.*: Error: illegal operands `cv.mulsrn t4,t2,465,10'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,3534,17'
+.*: Error: illegal operands `cv.mulu t4,t2,46'
+.*: Error: illegal operands `cv.mulhhu t4,t2,35'
+.*: Error: illegal operands `cv.mulun t4,t2,67,7'
+.*: Error: illegal operands `cv.mulhhun t4,t2,6,16'
+.*: Error: illegal operands `cv.mulurn t4,t2,787,11'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,3545,9'
+.*: Error: illegal operands `cv.macsn t4,t2,6,24'
+.*: Error: illegal operands `cv.machhsn t4,t2,765,11'
+.*: Error: illegal operands `cv.macsrn t4,t2,45,9'
+.*: Error: illegal operands `cv.machhsrn t4,t2,7,24'
+.*: Error: illegal operands `cv.macun t4,t2,98,27'
+.*: Error: illegal operands `cv.machhun t4,t2,654,18'
+.*: Error: illegal operands `cv.macurn t4,t2,900,25'
+.*: Error: illegal operands `cv.machhurn t4,t2,354,5'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,-43'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,-531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,-4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,-23'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,-459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,-549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,-32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,-223'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,-56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,-8'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,-2'
+.*: Error: illegal operands `cv.macun t4,t2,t0,-432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,-1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,-45'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,-354'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,32'
+.*: Error: illegal operands `cv.macun t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,32'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,32'
+.*: Error: illegal operands `cv.mulsn t4,t2,t0,325'
+.*: Error: illegal operands `cv.mulhhsn t4,t2,t0,531'
+.*: Error: illegal operands `cv.mulsrn t4,t2,t0,4454'
+.*: Error: illegal operands `cv.mulhhsrn t4,t2,t0,254'
+.*: Error: illegal operands `cv.mulun t4,t2,t0,76'
+.*: Error: illegal operands `cv.mulhhun t4,t2,t0,459'
+.*: Error: illegal operands `cv.mulurn t4,t2,t0,549'
+.*: Error: illegal operands `cv.mulhhurn t4,t2,t0,5364'
+.*: Error: illegal operands `cv.macsn t4,t2,t0,34435'
+.*: Error: illegal operands `cv.machhsn t4,t2,t0,56'
+.*: Error: illegal operands `cv.macsrn t4,t2,t0,3423'
+.*: Error: illegal operands `cv.machhsrn t4,t2,t0,365'
+.*: Error: illegal operands `cv.macun t4,t2,t0,432'
+.*: Error: illegal operands `cv.machhun t4,t2,t0,1245'
+.*: Error: illegal operands `cv.macurn t4,t2,t0,45'
+.*: Error: instruction cv.mulsn requires absolute expression
+.*: Error: instruction cv.mulhhsn requires absolute expression
+.*: Error: instruction cv.mulsrn requires absolute expression
+.*: Error: instruction cv.mulhhsrn requires absolute expression
+.*: Error: instruction cv.mulun requires absolute expression
+.*: Error: instruction cv.mulhhun requires absolute expression
+.*: Error: instruction cv.mulurn requires absolute expression
+.*: Error: instruction cv.mulhhurn requires absolute expression
+.*: Error: instruction cv.macsn requires absolute expression
+.*: Error: instruction cv.machhsn requires absolute expression
+.*: Error: instruction cv.macsrn requires absolute expression
+.*: Error: instruction cv.machhsrn requires absolute expression
+.*: Error: instruction cv.macun requires absolute expression
+.*: Error: instruction cv.machhun requires absolute expression
+.*: Error: instruction cv.macurn requires absolute expression
+.*: Error: instruction cv.machhurn requires absolute expression
+.*: Error: illegal operands `cv.machhurn t4,t2,t0,354'
diff --git a/gas/testsuite/gas/riscv/cv-mac-fail-operand.s b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
new file mode 100644
index 00000000000..97a29448ebd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-fail-operand.s
@@ -0,0 +1,156 @@
+# Destination must be of type register
+target:
+ cv.mac 8, t2, t0
+ cv.msu 23, t2, t0
+ cv.muls 43, t2, t0
+ cv.mulhhs 7, t2, t0
+ cv.mulsn 345, t2, t0, 4
+ cv.mulhhsn 356, t2, t0, 16
+ cv.mulsrn 867, t2, t0, 10
+ cv.mulhhsrn 3454, t2, t0, 17
+ cv.mulu 9, t2, t0
+ cv.mulhhu 54, t2, t0
+ cv.mulun 965, t2, t0, 7
+ cv.mulhhun 35, t2, t0, 16
+ cv.mulurn 87, t2, t0, 11
+ cv.mulhhurn 38, t2, t0, 9
+ cv.macsn 985, t2, t0, 24
+ cv.machhsn 83, t2, t0, 11
+ cv.macsrn 960, t2, t0, 9
+ cv.machhsrn 385, t2, t0, 24
+ cv.macun 58, t2, t0, 27
+ cv.machhun 6, t2, t0, 18
+ cv.macurn 35, t2, t0, 25
+ cv.machhurn 67, t2, t0, 5
+
+# Source one must be of type register
+ cv.mac t4, 43, t0
+ cv.msu t4, 3, t0
+ cv.muls t4, 345, t0
+ cv.mulhhs t4, 54, t0
+ cv.mulsn t4, 4, t0, 4
+ cv.mulhhsn t4, 35, t0, 16
+ cv.mulsrn t4, 53, t0, 10
+ cv.mulhhsrn t4, 4456, t0, 17
+ cv.mulu t4, 868, t0
+ cv.mulhhu t4, 95, t0
+ cv.mulun t4, 584, t0, 7
+ cv.mulhhun t4, 37545, t0, 16
+ cv.mulurn t4, 943, t0, 11
+ cv.mulhhurn t4, 34, t0, 9
+ cv.macsn t4, 93, t0, 24
+ cv.machhsn t4, 584, t0, 11
+ cv.macsrn t4, 28, t0, 9
+ cv.machhsrn t4, 9, t0, 24
+ cv.macun t4, 834, t0, 27
+ cv.machhun t4, 92, t0, 18
+ cv.macurn t4, 49, t0, 25
+ cv.machhurn t4, 6, t0, 5
+
+# Source two must be of type register
+ cv.mac t4, t2, 344
+ cv.msu t4, t2, 23
+ cv.muls t4, t2, 2
+ cv.mulhhs t4, t2, 8
+ cv.mulsn t4, t2, 45, 4
+ cv.mulhhsn t4, t2, 655, 16
+ cv.mulsrn t4, t2, 465, 10
+ cv.mulhhsrn t4, t2, 3534, 17
+ cv.mulu t4, t2, 46
+ cv.mulhhu t4, t2, 35
+ cv.mulun t4, t2, 67, 7
+ cv.mulhhun t4, t2, 6, 16
+ cv.mulurn t4, t2, 787, 11
+ cv.mulhhurn t4, t2, 3545, 9
+ cv.macsn t4, t2, 6, 24
+ cv.machhsn t4, t2, 765, 11
+ cv.macsrn t4, t2, 45, 9
+ cv.machhsrn t4, t2, 7, 24
+ cv.macun t4, t2, 98, 27
+ cv.machhun t4, t2, 654, 18
+ cv.macurn t4, t2, 900, 25
+ cv.machhurn t4, t2, 354, 5
+
+# Immediate value must be in range [0, 31]
+ cv.mulsn t4, t2, t0, -1
+ cv.mulhhsn t4, t2, t0, -1
+ cv.mulsrn t4, t2, t0, -1
+ cv.mulhhsrn t4, t2, t0, -1
+ cv.mulun t4, t2, t0, -1
+ cv.mulhhun t4, t2, t0, -1
+ cv.mulurn t4, t2, t0, -1
+ cv.mulhhurn t4, t2, t0, -1
+ cv.macsn t4, t2, t0, -1
+ cv.machhsn t4, t2, t0, -1
+ cv.macsrn t4, t2, t0, -1
+ cv.machhsrn t4, t2, t0, -1
+ cv.macun t4, t2, t0, -1
+ cv.machhun t4, t2, t0, -1
+ cv.macurn t4, t2, t0, -1
+ cv.machhurn t4, t2, t0, -1
+ cv.mulsn t4, t2, t0, -43
+ cv.mulhhsn t4, t2, t0, -531
+ cv.mulsrn t4, t2, t0, -4454
+ cv.mulhhsrn t4, t2, t0, -32
+ cv.mulun t4, t2, t0, -23
+ cv.mulhhun t4, t2, t0, -459
+ cv.mulurn t4, t2, t0, -549
+ cv.mulhhurn t4, t2, t0, -32
+ cv.macsn t4, t2, t0, -223
+ cv.machhsn t4, t2, t0, -56
+ cv.macsrn t4, t2, t0, -8
+ cv.machhsrn t4, t2, t0, -2
+ cv.macun t4, t2, t0, -432
+ cv.machhun t4, t2, t0, -1245
+ cv.macurn t4, t2, t0, -45
+ cv.machhurn t4, t2, t0, -354
+ cv.mulsn t4, t2, t0, 32
+ cv.mulhhsn t4, t2, t0, 32
+ cv.mulsrn t4, t2, t0, 32
+ cv.mulhhsrn t4, t2, t0, 32
+ cv.mulun t4, t2, t0, 32
+ cv.mulhhun t4, t2, t0, 32
+ cv.mulurn t4, t2, t0, 32
+ cv.mulhhurn t4, t2, t0, 32
+ cv.macsn t4, t2, t0, 32
+ cv.machhsn t4, t2, t0, 32
+ cv.macsrn t4, t2, t0, 32
+ cv.machhsrn t4, t2, t0, 32
+ cv.macun t4, t2, t0, 32
+ cv.machhun t4, t2, t0, 32
+ cv.macurn t4, t2, t0, 32
+ cv.machhurn t4, t2, t0, 32
+ cv.mulsn t4, t2, t0, 325
+ cv.mulhhsn t4, t2, t0, 531
+ cv.mulsrn t4, t2, t0, 4454
+ cv.mulhhsrn t4, t2, t0, 254
+ cv.mulun t4, t2, t0, 76
+ cv.mulhhun t4, t2, t0, 459
+ cv.mulurn t4, t2, t0, 549
+ cv.mulhhurn t4, t2, t0, 5364
+ cv.macsn t4, t2, t0, 34435
+ cv.machhsn t4, t2, t0, 56
+ cv.macsrn t4, t2, t0, 3423
+ cv.machhsrn t4, t2, t0, 365
+ cv.macun t4, t2, t0, 432
+ cv.machhun t4, t2, t0, 1245
+ cv.macurn t4, t2, t0, 45
+
+# Immediate value must be an absolute expression
+ cv.mulsn t4, t2, t0, t3
+ cv.mulhhsn t4, t2, t0, t1
+ cv.mulsrn t4, t2, t0, t6
+ cv.mulhhsrn t4, t2, t0, t3
+ cv.mulun t4, t2, t0, t1
+ cv.mulhhun t4, t2, t0, t3
+ cv.mulurn t4, t2, t0, t5
+ cv.mulhhurn t4, t2, t0, t1
+ cv.macsn t4, t2, t0, t3
+ cv.machhsn t4, t2, t0, t5
+ cv.macsrn t4, t2, t0, t1
+ cv.machhsrn t4, t2, t0, t6
+ cv.macun t4, t2, t0, t1
+ cv.machhun t4, t2, t0, t3
+ cv.macurn t4, t2, t0, t6
+ cv.machhurn t4, t2, t0, t5
+ cv.machhurn t4, t2, t0, 354
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.d b/gas/testsuite/gas/riscv/cv-mac-insns.d
new file mode 100644
index 00000000000..9a961051a97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.d
@@ -0,0 +1,87 @@
+#as: -march=rv32i_xcvmac
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+907332ab[ ]+cv.mac[ ]+t0,t1,t2
+[ ]+4:[ ]+9053beab[ ]+cv.mac[ ]+t4,t2,t0
+[ ]+8:[ ]+906f3e2b[ ]+cv.mac[ ]+t3,t5,t1
+[ ]+c:[ ]+407362db[ ]+cv.machhsn[ ]+t0,t1,t2,0
+[ ]+10:[ ]+5653eedb[ ]+cv.machhsn[ ]+t4,t2,t0,11
+[ ]+14:[ ]+7e6f6e5b[ ]+cv.machhsn[ ]+t3,t5,t1,31
+[ ]+18:[ ]+c07362db[ ]+cv.machhsrn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+f053eedb[ ]+cv.machhsrn[ ]+t4,t2,t0,24
+[ ]+20:[ ]+fe6f6e5b[ ]+cv.machhsrn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+407372db[ ]+cv.machhun[ ]+t0,t1,t2,0
+[ ]+28:[ ]+6453fedb[ ]+cv.machhun[ ]+t4,t2,t0,18
+[ ]+2c:[ ]+7e6f7e5b[ ]+cv.machhun[ ]+t3,t5,t1,31
+[ ]+30:[ ]+c07372db[ ]+cv.machhurn[ ]+t0,t1,t2,0
+[ ]+34:[ ]+ca53fedb[ ]+cv.machhurn[ ]+t4,t2,t0,5
+[ ]+38:[ ]+fe6f7e5b[ ]+cv.machhurn[ ]+t3,t5,t1,31
+[ ]+3c:[ ]+007362db[ ]+cv.macsn[ ]+t0,t1,t2,0
+[ ]+40:[ ]+3053eedb[ ]+cv.macsn[ ]+t4,t2,t0,24
+[ ]+44:[ ]+3e6f6e5b[ ]+cv.macsn[ ]+t3,t5,t1,31
+[ ]+48:[ ]+807362db[ ]+cv.macsrn[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+9253eedb[ ]+cv.macsrn[ ]+t4,t2,t0,9
+[ ]+50:[ ]+be6f6e5b[ ]+cv.macsrn[ ]+t3,t5,t1,31
+[ ]+54:[ ]+007372db[ ]+cv.macun[ ]+t0,t1,t2,0
+[ ]+58:[ ]+3653fedb[ ]+cv.macun[ ]+t4,t2,t0,27
+[ ]+5c:[ ]+3e6f7e5b[ ]+cv.macun[ ]+t3,t5,t1,31
+[ ]+60:[ ]+807372db[ ]+cv.macurn[ ]+t0,t1,t2,0
+[ ]+64:[ ]+b253fedb[ ]+cv.macurn[ ]+t4,t2,t0,25
+[ ]+68:[ ]+be6f7e5b[ ]+cv.macurn[ ]+t3,t5,t1,31
+[ ]+6c:[ ]+927332ab[ ]+cv.msu[ ]+t0,t1,t2
+[ ]+70:[ ]+9253beab[ ]+cv.msu[ ]+t4,t2,t0
+[ ]+74:[ ]+926f3e2b[ ]+cv.msu[ ]+t3,t5,t1
+[ ]+78:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+7c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+80:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+84:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+88:[ ]+6053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,16
+[ ]+8c:[ ]+7e6f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,31
+[ ]+90:[ ]+c07342db[ ]+cv.mulhhsrn[ ]+t0,t1,t2,0
+[ ]+94:[ ]+e253cedb[ ]+cv.mulhhsrn[ ]+t4,t2,t0,17
+[ ]+98:[ ]+fe6f4e5b[ ]+cv.mulhhsrn[ ]+t3,t5,t1,31
+[ ]+9c:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+a0:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+a4:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+a8:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+ac:[ ]+6053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,16
+[ ]+b0:[ ]+7e6f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,31
+[ ]+b4:[ ]+c07352db[ ]+cv.mulhhurn[ ]+t0,t1,t2,0
+[ ]+b8:[ ]+d253dedb[ ]+cv.mulhhurn[ ]+t4,t2,t0,9
+[ ]+bc:[ ]+fe6f5e5b[ ]+cv.mulhhurn[ ]+t3,t5,t1,31
+[ ]+c0:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+c4:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+c8:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+cc:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+d0:[ ]+0853cedb[ ]+cv.mulsn[ ]+t4,t2,t0,4
+[ ]+d4:[ ]+3e6f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,31
+[ ]+d8:[ ]+807342db[ ]+cv.mulsrn[ ]+t0,t1,t2,0
+[ ]+dc:[ ]+9453cedb[ ]+cv.mulsrn[ ]+t4,t2,t0,10
+[ ]+e0:[ ]+be6f4e5b[ ]+cv.mulsrn[ ]+t3,t5,t1,31
+[ ]+e4:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+e8:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+ec:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
+[ ]+f0:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+f4:[ ]+0e53dedb[ ]+cv.mulun[ ]+t4,t2,t0,7
+[ ]+f8:[ ]+3e6f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,31
+[ ]+fc:[ ]+807352db[ ]+cv.mulurn[ ]+t0,t1,t2,0
+[ ]+100:[ ]+9653dedb[ ]+cv.mulurn[ ]+t4,t2,t0,11
+[ ]+104:[ ]+be6f5e5b[ ]+cv.mulurn[ ]+t3,t5,t1,31
+[ ]+108:[ ]+407342db[ ]+cv.mulhhsn[ ]+t0,t1,t2,0
+[ ]+10c:[ ]+4053cedb[ ]+cv.mulhhsn[ ]+t4,t2,t0,0
+[ ]+110:[ ]+406f4e5b[ ]+cv.mulhhsn[ ]+t3,t5,t1,0
+[ ]+114:[ ]+407352db[ ]+cv.mulhhun[ ]+t0,t1,t2,0
+[ ]+118:[ ]+4053dedb[ ]+cv.mulhhun[ ]+t4,t2,t0,0
+[ ]+11c:[ ]+406f5e5b[ ]+cv.mulhhun[ ]+t3,t5,t1,0
+[ ]+120:[ ]+007342db[ ]+cv.mulsn[ ]+t0,t1,t2,0
+[ ]+124:[ ]+0053cedb[ ]+cv.mulsn[ ]+t4,t2,t0,0
+[ ]+128:[ ]+006f4e5b[ ]+cv.mulsn[ ]+t3,t5,t1,0
+[ ]+12c:[ ]+007352db[ ]+cv.mulun[ ]+t0,t1,t2,0
+[ ]+130:[ ]+0053dedb[ ]+cv.mulun[ ]+t4,t2,t0,0
+[ ]+134:[ ]+006f5e5b[ ]+cv.mulun[ ]+t3,t5,t1,0
diff --git a/gas/testsuite/gas/riscv/cv-mac-insns.s b/gas/testsuite/gas/riscv/cv-mac-insns.s
new file mode 100644
index 00000000000..a699a3ba461
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-mac-insns.s
@@ -0,0 +1,81 @@
+target:
+ cv.mac t0, t1, t2
+ cv.mac t4, t2, t0
+ cv.mac t3, t5, t1
+ cv.machhsn t0, t1, t2, 0
+ cv.machhsn t4, t2, t0, 11
+ cv.machhsn t3, t5, t1, 31
+ cv.machhsrn t0, t1, t2, 0
+ cv.machhsrn t4, t2, t0, 24
+ cv.machhsrn t3, t5, t1, 31
+ cv.machhun t0, t1, t2, 0
+ cv.machhun t4, t2, t0, 18
+ cv.machhun t3, t5, t1, 31
+ cv.machhurn t0, t1, t2, 0
+ cv.machhurn t4, t2, t0, 5
+ cv.machhurn t3, t5, t1, 31
+ cv.macsn t0, t1, t2, 0
+ cv.macsn t4, t2, t0, 24
+ cv.macsn t3, t5, t1, 31
+ cv.macsrn t0, t1, t2, 0
+ cv.macsrn t4, t2, t0, 9
+ cv.macsrn t3, t5, t1, 31
+ cv.macun t0, t1, t2, 0
+ cv.macun t4, t2, t0, 27
+ cv.macun t3, t5, t1, 31
+ cv.macurn t0, t1, t2, 0
+ cv.macurn t4, t2, t0, 25
+ cv.macurn t3, t5, t1, 31
+ cv.msu t0, t1, t2
+ cv.msu t4, t2, t0
+ cv.msu t3, t5, t1
+ cv.mulhhs t0, t1, t2
+ cv.mulhhs t4, t2, t0
+ cv.mulhhs t3, t5, t1
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 16
+ cv.mulhhsn t3, t5, t1, 31
+ cv.mulhhsrn t0, t1, t2, 0
+ cv.mulhhsrn t4, t2, t0, 17
+ cv.mulhhsrn t3, t5, t1, 31
+ cv.mulhhu t0, t1, t2
+ cv.mulhhu t4, t2, t0
+ cv.mulhhu t3, t5, t1
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 16
+ cv.mulhhun t3, t5, t1, 31
+ cv.mulhhurn t0, t1, t2, 0
+ cv.mulhhurn t4, t2, t0, 9
+ cv.mulhhurn t3, t5, t1, 31
+ cv.muls t0, t1, t2
+ cv.muls t4, t2, t0
+ cv.muls t3, t5, t1
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 4
+ cv.mulsn t3, t5, t1, 31
+ cv.mulsrn t0, t1, t2, 0
+ cv.mulsrn t4, t2, t0, 10
+ cv.mulsrn t3, t5, t1, 31
+ cv.mulu t0, t1, t2
+ cv.mulu t4, t2, t0
+ cv.mulu t3, t5, t1
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 7
+ cv.mulun t3, t5, t1, 31
+ cv.mulurn t0, t1, t2, 0
+ cv.mulurn t4, t2, t0, 11
+ cv.mulurn t3, t5, t1, 31
+
+ # Pseudo-instructions
+ cv.mulhhsn t0, t1, t2, 0
+ cv.mulhhsn t4, t2, t0, 0
+ cv.mulhhsn t3, t5, t1, 0
+ cv.mulhhun t0, t1, t2, 0
+ cv.mulhhun t4, t2, t0, 0
+ cv.mulhhun t3, t5, t1, 0
+ cv.mulsn t0, t1, t2, 0
+ cv.mulsn t4, t2, t0, 0
+ cv.mulsn t3, t5, t1, 0
+ cv.mulun t0, t1, t2, 0
+ cv.mulun t4, t2, t0, 0
+ cv.mulun t3, t5, t1, 0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2a26c45f0c2..418e77061df 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2320,6 +2320,43 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+#define MATCH_CV_MAC 0x9000302b
+#define MASK_CV_MAC 0xfe00707f
+#define MATCH_CV_MSU 0x9200302b
+#define MASK_CV_MSU 0xfe00707f
+#define MATCH_CV_MULSN 0x405b
+#define MASK_CV_MULSN 0xc000707f
+#define MATCH_CV_MULHHSN 0x4000405b
+#define MASK_CV_MULHHSN 0xc000707f
+#define MATCH_CV_MULSRN 0x8000405b
+#define MASK_CV_MULSRN 0xc000707f
+#define MATCH_CV_MULHHSRN 0xc000405b
+#define MASK_CV_MULHHSRN 0xc000707f
+#define MATCH_CV_MULUN 0x505b
+#define MASK_CV_MULUN 0xc000707f
+#define MATCH_CV_MULHHUN 0x4000505b
+#define MASK_CV_MULHHUN 0xc000707f
+#define MATCH_CV_MULURN 0x8000505b
+#define MASK_CV_MULURN 0xc000707f
+#define MATCH_CV_MULHHURN 0xc000505b
+#define MASK_CV_MULHHURN 0xc000707f
+#define MATCH_CV_MACSN 0x605b
+#define MASK_CV_MACSN 0xc000707f
+#define MATCH_CV_MACHHSN 0x4000605b
+#define MASK_CV_MACHHSN 0xc000707f
+#define MATCH_CV_MACSRN 0x8000605b
+#define MASK_CV_MACSRN 0xc000707f
+#define MATCH_CV_MACHHSRN 0xc000605b
+#define MASK_CV_MACHHSRN 0xc000707f
+#define MATCH_CV_MACUN 0x705b
+#define MASK_CV_MACUN 0xc000707f
+#define MATCH_CV_MACHHUN 0x4000705b
+#define MASK_CV_MACHHUN 0xc000707f
+#define MATCH_CV_MACURN 0x8000705b
+#define MASK_CV_MACURN 0xc000707f
+#define MATCH_CV_MACHHURN 0xc000705b
+#define MASK_CV_MACHHURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 93dd5169ebc..153bff31e2c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -112,6 +112,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
+/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS3_UIMM5(x) \
+ (RV_X(x, 25, 5))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -163,6 +166,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
+/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS3_UIMM5(x) \
+ (RV_X(x, 0, 5) << 25)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -443,6 +449,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
+ INSN_CLASS_XCVMAC,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c0fd0625a2d..b7a3f1ac2ea 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -677,11 +677,19 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
}
}
break;
+ case 'c': /* Vendor-specific (CORE-V) operands. */
+ switch (*++oparg)
+ {
+ case '3':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS3_UIMM5 (l)));
+ break;
+ }
+ break;
default:
goto undefined_modifier;
}
break;
-
default:
undefined_modifier:
/* xgettext:c-format */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8e0ae85eb06..1f8cfe967f2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -154,6 +154,8 @@ const float riscv_fli_numval[32] =
#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+/* Vendor-specific (CORE-V) masks. */
+#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)
static int
match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -2039,6 +2041,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+/* Vendor-specific (CORE-V) Xcvmac instructions. */
+{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
+{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
+{"cv.mulsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSN, MASK_CV_MULSN, match_opcode, 0},
+{"cv.muls", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULSN, MASK_CV_MULSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSRN, MASK_CV_MULSRN, match_opcode, 0},
+{"cv.mulhhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSN, MASK_CV_MULHHSN, match_opcode, 0},
+{"cv.mulhhs", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHSN, MASK_CV_MULHHSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSRN, MASK_CV_MULHHSRN, match_opcode, 0},
+{"cv.mulun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULUN, MASK_CV_MULUN, match_opcode, 0},
+{"cv.mulu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULUN, MASK_CV_MULUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULURN, MASK_CV_MULURN, match_opcode, 0},
+{"cv.mulhhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHUN, MASK_CV_MULHHUN, match_opcode, 0},
+{"cv.mulhhu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHUN, MASK_CV_MULHHUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHURN, MASK_CV_MULHHURN, match_opcode, 0},
+{"cv.macsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSN, MASK_CV_MACSN, match_opcode, 0},
+{"cv.machhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSN, MASK_CV_MACHHSN, match_opcode, 0},
+{"cv.macsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSRN, MASK_CV_MACSRN, match_opcode, 0},
+{"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSRN, MASK_CV_MACHHSRN, match_opcode, 0},
+{"cv.macun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACUN, MASK_CV_MACUN, match_opcode, 0},
+{"cv.machhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHUN, MASK_CV_MACHHUN, match_opcode, 0},
+{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN, MASK_CV_MACURN, match_opcode, 0},
+{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] RISC-V: Add support for XCValu extension in CV32E40P
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-10-02 2:02 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
@ 2023-10-02 2:02 ` Mary Bennett
2023-11-06 17:27 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2 siblings, 0 replies; 16+ messages in thread
From: Mary Bennett @ 2023-10-02 2:02 UTC (permalink / raw)
To: binutils; +Cc: mary.bennett
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
* testsuite/gas/riscv/cv-alu-insns.d: New test.
* testsuite/gas/riscv/cv-alu-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble xcb operand.
* riscv-opc.c: Defined the MASK and added XCValu instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCValu.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for XCValu.
(enum riscv_insn_class): Added the XCValu instruction class.
---
bfd/elfxx-riscv.c | 5 +
gas/config/tc-riscv.c | 14 ++
gas/doc/c-riscv.texi | 5 +
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 +++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 +++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 +++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 ++++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 ++++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 ++
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 +++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 +++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++++++
include/opcode/riscv-opc.h | 67 ++++++++++
include/opcode/riscv.h | 5 +
opcodes/riscv-dis.c | 4 +
opcodes/riscv-opc.c | 35 +++++
36 files changed, 787 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6f1e66a09dc..5e78bc7873f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1353,6 +1353,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
/* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2553,6 +2554,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "h");
case INSN_CLASS_XCVMAC:
return riscv_subset_supports (rps, "xcvmac");
+ case INSN_CLASS_XCVALU:
+ return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2795,6 +2798,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("h");
case INSN_CLASS_XCVMAC:
return "xcvmac";
+ case INSN_CLASS_XCVALU:
+ return "xcvalu";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index db3dc297302..a58471591fb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1484,6 +1484,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ /* ls2[4:0] */
+ used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
+ break;
case '3':
used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
break;
@@ -3662,6 +3666,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number<0
+ || imm_expr->X_add_number>31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+ continue;
case '3':
my_getExpression (imm_expr, asarg);
check_absolute_expr (ip, imm_expr, FALSE);
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 5aa511de999..6865caa1977 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvmac extension provides instructions for multiply-accumulate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+@item Xcvalu
+The Xcvalu extension provides instructions for general ALU operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
new file mode 100644
index 00000000000..907b043aebc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-boundaries.s
+#error_output: cv-alu-boundaries.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
new file mode 100644
index 00000000000..fae4022244c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subnr 10,t3,t6'
+.*: Error: illegal operands `cv.addrnr t4,26,t6'
+.*: Error: illegal operands `cv.subunr t6,t3,15'
+.*: Error: instruction cv.clipu requires absolute expression
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: illegal operands `cv.clipu t0,t3,-10'
+.*: Error: illegal operands `cv.clipu t0,t3,500'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-60'
+.*: Error: illegal operands `cv.addn t0,t3,t6,302'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.addn t0,t3,t6,-1'
+.*: Error: illegal operands `cv.addn t0,t3,t6,32'
diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
new file mode 100644
index 00000000000..bb4da949b4a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.s
@@ -0,0 +1,27 @@
+# Destination must be of type register
+target:
+ cv.subnr 10, t3, t6
+# Source 1 must be of type register
+ cv.addrnr t4, 26, t6
+# Source 2 must be of type register
+ cv.subunr t6, t3, 15
+# Five bit immediate must be an absolute value
+ cv.clipu t0, t3, t6
+# Five bit immediate must be an absolute value
+ cv.addn t0, t3, t6, t2
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -10
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 500
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -60
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 302
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.clipu t0, t3, 32
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, -1
+# Five bit immediate must be an absolute value in range [0, 31]
+ cv.addn t0, t3, t6, 32
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
new file mode 100644
index 00000000000..963aa4012da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-alu-fail-march.s
+#error_output: cv-alu-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
new file mode 100644
index 00000000000..11e5a7cd279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' required
+.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' required
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
new file mode 100644
index 00000000000..8dd39b7301f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.s
@@ -0,0 +1,33 @@
+# Absence of xcv or xcvalu march option disables all CORE-V general ALU ops extensions
+target:
+ cv.abs t4,t2
+ cv.slet t4,t2,t6
+ cv.sletu t4,t2,t6
+ cv.min t4,t2,t6
+ cv.minu t4,t2,t6
+ cv.max t4,t2,t6
+ cv.maxu t4,t2,t6
+ cv.exths t4,t2
+ cv.exthz t4,t2
+ cv.extbs t4,t2
+ cv.extbz t4,t2
+ cv.clip t4,t2,5
+ cv.clipu t4,t2,5
+ cv.clipr t4,t2,t6
+ cv.clipur t4,t2,t6
+ cv.addn t4, t2, t0, 4
+ cv.addun t4, t2, t0, 4
+ cv.addrn t6, t0, t3, 9
+ cv.addurn t6, t0, t3, 14
+ cv.addnr t6, t0, t3
+ cv.addunr t6, t0, t3
+ cv.addrnr t6, t0, t3
+ cv.addurnr t6, t0, t3
+ cv.subn t6, t0, t3, 6
+ cv.subun t6, t0, t3, 24
+ cv.subrn t6, t0, t3, 21
+ cv.suburn t6, t0, t3, 3
+ cv.subnr t6, t0, t3
+ cv.subunr t6, t0, t3
+ cv.subrnr t6, t0, t3
+ cv.suburnr t6, t0, t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
new file mode 100644
index 00000000000..81b17348c32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-01.s
+#error_output: cv-alu-fail-operand-01.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
new file mode 100644
index 00000000000..f670e4341fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs 5,t2'
+.*: Error: illegal operands `cv.slet 10,t2,t6'
+.*: Error: illegal operands `cv.sletu 11,t2,t6'
+.*: Error: illegal operands `cv.min 15,t2,t6'
+.*: Error: illegal operands `cv.minu 16,t2,t6'
+.*: Error: illegal operands `cv.max 8,t2,t6'
+.*: Error: illegal operands `cv.maxu 3,t2,t6'
+.*: Error: illegal operands `cv.exths 2,t2'
+.*: Error: illegal operands `cv.exthz 6,t2'
+.*: Error: illegal operands `cv.extbs 4,t2'
+.*: Error: illegal operands `cv.extbz 7,t2'
+.*: Error: illegal operands `cv.clip 17,t2,5'
+.*: Error: illegal operands `cv.clipu 11,t2,5'
+.*: Error: illegal operands `cv.clipr 16,t2,t6'
+.*: Error: illegal operands `cv.clipur 15,t2,t6'
+.*: Error: illegal operands `cv.addn 9,t2,t0,4'
+.*: Error: illegal operands `cv.addun 30,t2,t0,4'
+.*: Error: illegal operands `cv.addrn 21,t0,t3,9'
+.*: Error: illegal operands `cv.addurn 6,t0,t3,14'
+.*: Error: illegal operands `cv.addnr 2,t0,t3'
+.*: Error: illegal operands `cv.addunr 26,t0,t3'
+.*: Error: illegal operands `cv.addrnr 3,t0,t3'
+.*: Error: illegal operands `cv.addurnr 14,t0,t3'
+.*: Error: illegal operands `cv.subn 15,t0,t3,6'
+.*: Error: illegal operands `cv.subun 9,t0,t3,24'
+.*: Error: illegal operands `cv.subrn 24,t0,t3,21'
+.*: Error: illegal operands `cv.suburn 25,t0,t3,3'
+.*: Error: illegal operands `cv.subnr 3,t0,t3'
+.*: Error: illegal operands `cv.subunr 12,t0,t3'
+.*: Error: illegal operands `cv.subrnr 13,t0,t3'
+.*: Error: illegal operands `cv.suburnr 8,t0,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
new file mode 100644
index 00000000000..7920ebd53ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
@@ -0,0 +1,33 @@
+# Destination must be of type register
+target:
+ cv.abs 5,t2
+ cv.slet 10,t2,t6
+ cv.sletu 11,t2,t6
+ cv.min 15,t2,t6
+ cv.minu 16,t2,t6
+ cv.max 8,t2,t6
+ cv.maxu 3,t2,t6
+ cv.exths 2,t2
+ cv.exthz 6,t2
+ cv.extbs 4,t2
+ cv.extbz 7,t2
+ cv.clip 17,t2,5
+ cv.clipu 11,t2,5
+ cv.clipr 16,t2,t6
+ cv.clipur 15,t2,t6
+ cv.addn 9,t2,t0,4
+ cv.addun 30,t2,t0,4
+ cv.addrn 21,t0,t3,9
+ cv.addurn 6,t0,t3,14
+ cv.addnr 2,t0,t3
+ cv.addunr 26,t0,t3
+ cv.addrnr 3,t0,t3
+ cv.addurnr 14,t0,t3
+ cv.subn 15,t0,t3,6
+ cv.subun 9,t0,t3,24
+ cv.subrn 24,t0,t3,21
+ cv.suburn 25,t0,t3,3
+ cv.subnr 3,t0,t3
+ cv.subunr 12,t0,t3
+ cv.subrnr 13,t0,t3
+ cv.suburnr 8,t0,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
new file mode 100644
index 00000000000..46645aaf864
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-02.s
+#error_output: cv-alu-fail-operand-02.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
new file mode 100644
index 00000000000..0a888c7251b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
@@ -0,0 +1,32 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs t4,5'
+.*: Error: illegal operands `cv.slet t4,7,t6'
+.*: Error: illegal operands `cv.sletu t4,3,t6'
+.*: Error: illegal operands `cv.min t4,5,t6'
+.*: Error: illegal operands `cv.minu t4,3,t6'
+.*: Error: illegal operands `cv.max t4,4,t6'
+.*: Error: illegal operands `cv.maxu t4,6,t6'
+.*: Error: illegal operands `cv.exths t4,30'
+.*: Error: illegal operands `cv.exthz t4,23'
+.*: Error: illegal operands `cv.extbs t4,25'
+.*: Error: illegal operands `cv.extbz t4,21'
+.*: Error: illegal operands `cv.clip t4,2,5'
+.*: Error: illegal operands `cv.clipu t4,16,5'
+.*: Error: illegal operands `cv.clipr t4,17,t6'
+.*: Error: illegal operands `cv.clipur t4,14,t6'
+.*: Error: illegal operands `cv.addn t4,5,t0,4'
+.*: Error: illegal operands `cv.addun t4,18,t0,4'
+.*: Error: illegal operands `cv.addrn t6,19,t3,9'
+.*: Error: illegal operands `cv.addurn t6,4,t3,14'
+.*: Error: illegal operands `cv.addnr t6,6,t3'
+.*: Error: illegal operands `cv.addunr t6,7,t3'
+.*: Error: illegal operands `cv.addrnr t6,9,t3'
+.*: Error: illegal operands `cv.addurnr t6,5,t3'
+.*: Error: illegal operands `cv.subn t6,11,t3,6'
+.*: Error: illegal operands `cv.subun t6,14,t3,24'
+.*: Error: illegal operands `cv.subrn t6,15,t3,21'
+.*: Error: illegal operands `cv.suburn t6,24,t3,3'
+.*: Error: illegal operands `cv.subnr t6,4,t3'
+.*: Error: illegal operands `cv.subunr t6,8,t3'
+.*: Error: illegal operands `cv.subrnr t6,7,t3'
+.*: Error: illegal operands `cv.suburnr t6,6,t3'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
new file mode 100644
index 00000000000..6083f1f5044
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
@@ -0,0 +1,33 @@
+# Source 1 must be of type register
+target:
+ cv.abs t4,5
+ cv.slet t4,7,t6
+ cv.sletu t4,3,t6
+ cv.min t4,5,t6
+ cv.minu t4,3,t6
+ cv.max t4,4,t6
+ cv.maxu t4,6,t6
+ cv.exths t4,30
+ cv.exthz t4,23
+ cv.extbs t4,25
+ cv.extbz t4,21
+ cv.clip t4,2,5
+ cv.clipu t4,16,5
+ cv.clipr t4,17,t6
+ cv.clipur t4,14,t6
+ cv.addn t4,5,t0,4
+ cv.addun t4,18,t0,4
+ cv.addrn t6,19,t3,9
+ cv.addurn t6,4,t3,14
+ cv.addnr t6,6,t3
+ cv.addunr t6,7,t3
+ cv.addrnr t6,9,t3
+ cv.addurnr t6,5,t3
+ cv.subn t6,11,t3,6
+ cv.subun t6,14,t3,24
+ cv.subrn t6,15,t3,21
+ cv.suburn t6,24,t3,3
+ cv.subnr t6,4,t3
+ cv.subunr t6,8,t3
+ cv.subrnr t6,7,t3
+ cv.suburnr t6,6,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
new file mode 100644
index 00000000000..6f681289d12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-03.s
+#error_output: cv-alu-fail-operand-03.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
new file mode 100644
index 00000000000..c7a11184996
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.slet t4,t2,3'
+.*: Error: illegal operands `cv.sletu t4,t2,4'
+.*: Error: illegal operands `cv.min t4,t2,13'
+.*: Error: illegal operands `cv.minu t4,t2,7'
+.*: Error: illegal operands `cv.max t4,t2,17'
+.*: Error: illegal operands `cv.maxu t4,t2,30'
+.*: Error: illegal operands `cv.clipr t4,t2,18'
+.*: Error: illegal operands `cv.clipur t4,t2,29'
+.*: Error: illegal operands `cv.addn t4,t2,24,4'
+.*: Error: illegal operands `cv.addun t4,t2,6,4'
+.*: Error: illegal operands `cv.addrn t6,t0,7,9'
+.*: Error: illegal operands `cv.addurn t6,t0,18,14'
+.*: Error: illegal operands `cv.addnr t6,t0,15'
+.*: Error: illegal operands `cv.addunr t6,t0,24'
+.*: Error: illegal operands `cv.addrnr t6,t0,3'
+.*: Error: illegal operands `cv.addurnr t6,t0,2'
+.*: Error: illegal operands `cv.subn t6,t0,1,6'
+.*: Error: illegal operands `cv.subun t6,t0,8,24'
+.*: Error: illegal operands `cv.subrn t6,t0,18,21'
+.*: Error: illegal operands `cv.suburn t6,t0,25,3'
+.*: Error: illegal operands `cv.subnr t6,t0,14'
+.*: Error: illegal operands `cv.subunr t6,t0,7'
+.*: Error: illegal operands `cv.subrnr t6,t0,18'
+.*: Error: illegal operands `cv.suburnr t6,t0,26'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
new file mode 100644
index 00000000000..64ee8703579
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
@@ -0,0 +1,26 @@
+# Source 2 must be of type register
+target:
+ cv.slet t4,t2,3
+ cv.sletu t4,t2,4
+ cv.min t4,t2,13
+ cv.minu t4,t2,7
+ cv.max t4,t2,17
+ cv.maxu t4,t2,30
+ cv.clipr t4,t2,18
+ cv.clipur t4,t2,29
+ cv.addn t4,t2,24,4
+ cv.addun t4,t2,6,4
+ cv.addrn t6,t0,7,9
+ cv.addurn t6,t0,18,14
+ cv.addnr t6,t0,15
+ cv.addunr t6,t0,24
+ cv.addrnr t6,t0,3
+ cv.addurnr t6,t0,2
+ cv.subn t6,t0,1,6
+ cv.subun t6,t0,8,24
+ cv.subrn t6,t0,18,21
+ cv.suburn t6,t0,25,3
+ cv.subnr t6,t0,14
+ cv.subunr t6,t0,7
+ cv.subrnr t6,t0,18
+ cv.suburnr t6,t0,26
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
new file mode 100644
index 00000000000..634d9bfe091
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-04.s
+#error_output: cv-alu-fail-operand-04.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
new file mode 100644
index 00000000000..d6fd960f9e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.clip requires absolute expression
+.*: Error: instruction cv.clipu requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
new file mode 100644
index 00000000000..b97d52a77ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
@@ -0,0 +1,4 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.clip t4,t2,t3
+ cv.clipu t4,t2,t3
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
new file mode 100644
index 00000000000..1b90d3e5757
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-05.s
+#error_output: cv-alu-fail-operand-05.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
new file mode 100644
index 00000000000..05b5289e743
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: instruction cv.addn requires absolute expression
+.*: Error: instruction cv.addun requires absolute expression
+.*: Error: instruction cv.addrn requires absolute expression
+.*: Error: instruction cv.addurn requires absolute expression
+.*: Error: instruction cv.subn requires absolute expression
+.*: Error: instruction cv.subun requires absolute expression
+.*: Error: instruction cv.subrn requires absolute expression
+.*: Error: instruction cv.suburn requires absolute expression
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
new file mode 100644
index 00000000000..1b0ac6f2d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value
+target:
+ cv.addn t4,t2,t0,t3
+ cv.addun t4,t2,t0,t3
+ cv.addrn t6,t0,t3,t2
+ cv.addurn t6,t0,t3,t2
+ cv.subn t6,t0,t3,t2
+ cv.subun t6,t0,t3,t2
+ cv.subrn t6,t0,t3,t2
+ cv.suburn t6,t0,t3,t2
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
new file mode 100644
index 00000000000..0a49e682c85
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-06.s
+#error_output: cv-alu-fail-operand-06.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
new file mode 100644
index 00000000000..d8059cb5e3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.clip t0,t3,-1'
+.*: Error: illegal operands `cv.clipu t0,t3,-1'
+.*: Error: illegal operands `cv.clip t0,t3,-400'
+.*: Error: illegal operands `cv.clipu t0,t3,-985'
+.*: Error: illegal operands `cv.clip t0,t3,32'
+.*: Error: illegal operands `cv.clipu t0,t3,32'
+.*: Error: illegal operands `cv.clip t0,t3,859'
+.*: Error: illegal operands `cv.clipu t0,t3,7283'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
new file mode 100644
index 00000000000..1b810bdda55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
@@ -0,0 +1,10 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.clip t0,t3,-1
+ cv.clipu t0,t3,-1
+ cv.clip t0,t3,-400
+ cv.clipu t0,t3,-985
+ cv.clip t0,t3,32
+ cv.clipu t0,t3,32
+ cv.clip t0,t3,859
+ cv.clipu t0,t3,7283
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
new file mode 100644
index 00000000000..06d17fede7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvalu
+#source: cv-alu-fail-operand-07.s
+#error_output: cv-alu-fail-operand-07.l
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
new file mode 100644
index 00000000000..5a34156afc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.addn t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-1'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-1'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-1'
+.*: Error: illegal operands `cv.addn t4,t2,t0,-34'
+.*: Error: illegal operands `cv.addun t4,t2,t0,-3556'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,-212'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584'
+.*: Error: illegal operands `cv.subn t6,t0,t3,-89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,-9034'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,-234'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,-284'
+.*: Error: illegal operands `cv.addn t4,t2,t0,32'
+.*: Error: illegal operands `cv.addun t4,t2,t0,32'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subn t6,t0,t3,32'
+.*: Error: illegal operands `cv.subun t6,t0,t3,32'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,32'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,32'
+.*: Error: illegal operands `cv.addn t4,t2,t0,320'
+.*: Error: illegal operands `cv.addun t4,t2,t0,34534'
+.*: Error: illegal operands `cv.addrn t6,t0,t3,254'
+.*: Error: illegal operands `cv.addurn t6,t0,t3,398'
+.*: Error: illegal operands `cv.subn t6,t0,t3,89'
+.*: Error: illegal operands `cv.subun t6,t0,t3,3489'
+.*: Error: illegal operands `cv.subrn t6,t0,t3,143'
+.*: Error: illegal operands `cv.suburn t6,t0,t3,234'
diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
new file mode 100644
index 00000000000..04788f69ddd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
@@ -0,0 +1,34 @@
+# Five bit immediate must be an absolute value in range [0, 31]
+target:
+ cv.addn t4,t2,t0,-1
+ cv.addun t4,t2,t0,-1
+ cv.addrn t6,t0,t3,-1
+ cv.addurn t6,t0,t3,-1
+ cv.subn t6,t0,t3,-1
+ cv.subun t6,t0,t3,-1
+ cv.subrn t6,t0,t3,-1
+ cv.suburn t6,t0,t3,-1
+ cv.addn t4,t2,t0,-34
+ cv.addun t4,t2,t0,-3556
+ cv.addrn t6,t0,t3,-212
+ cv.addurn t6,t0,t3,-6584
+ cv.subn t6,t0,t3,-89
+ cv.subun t6,t0,t3,-9034
+ cv.subrn t6,t0,t3,-234
+ cv.suburn t6,t0,t3,-284
+ cv.addn t4,t2,t0,32
+ cv.addun t4,t2,t0,32
+ cv.addrn t6,t0,t3,32
+ cv.addurn t6,t0,t3,32
+ cv.subn t6,t0,t3,32
+ cv.subun t6,t0,t3,32
+ cv.subrn t6,t0,t3,32
+ cv.suburn t6,t0,t3,32
+ cv.addn t4,t2,t0,320
+ cv.addun t4,t2,t0,34534
+ cv.addrn t6,t0,t3,254
+ cv.addurn t6,t0,t3,398
+ cv.subn t6,t0,t3,89
+ cv.subun t6,t0,t3,3489
+ cv.subrn t6,t0,t3,143
+ cv.suburn t6,t0,t3,234
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d b/gas/testsuite/gas/riscv/cv-alu-insns.d
new file mode 100644
index 00000000000..784cf5ca6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.d
@@ -0,0 +1,102 @@
+#as: -march=rv32i_xcvalu
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1
+[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2
+[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5
+[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6
+[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3
+[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0
+[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0
+[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4
+[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31
+[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6
+[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3
+[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0
+[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0
+[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9
+[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31
+[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6
+[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3
+[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0
+[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0
+[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4
+[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31
+[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6
+[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3
+[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0
+[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0
+[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14
+[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31
+[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2
+[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6
+[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1
+[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0
+[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5
+[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31
+[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2
+[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6
+[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1
+[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0
+[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5
+[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31
+[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1
+[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2
+[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5
+[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1
+[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2
+[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5
+[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1
+[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2
+[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5
+[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1
+[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2
+[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5
+[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2
+[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6
+[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1
+[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2
+[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6
+[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1
+[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2
+[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6
+[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1
+[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2
+[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6
+[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1
+[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2
+[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6
+[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1
+[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2
+[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6
+[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1
+[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6
+[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3
+[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0
+[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0
+[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6
+[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31
+[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6
+[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3
+[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0
+[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0
+[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21
+[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31
+[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6
+[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3
+[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0
+[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0
+[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24
+[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31
+[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6
+[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3
+[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0
+[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0
+[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3
+[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31
diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s b/gas/testsuite/gas/riscv/cv-alu-insns.s
new file mode 100644
index 00000000000..82ea0c3b98d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-alu-insns.s
@@ -0,0 +1,124 @@
+target:
+ cv.abs t0,t1
+ cv.abs t4,t2
+ cv.abs t3,t5
+
+ cv.addnr t0, t3, t6
+ cv.addnr t6, t0, t3
+ cv.addnr t3, t6, t0
+
+ cv.addn t0, t1, t2, 0
+ cv.addn t4, t2, t0, 4
+ cv.addn t3, t5, t1, 31
+
+ cv.addrnr t0, t3, t6
+ cv.addrnr t6, t0, t3
+ cv.addrnr t3, t6, t0
+
+ cv.addrn t0, t3, t6, 0
+ cv.addrn t6, t0, t3, 9
+ cv.addrn t3, t6, t0, 31
+
+ cv.addunr t0, t3, t6
+ cv.addunr t6, t0, t3
+ cv.addunr t3, t6, t0
+
+ cv.addun t0, t1, t2, 0
+ cv.addun t4, t2, t0, 4
+ cv.addun t3, t5, t1, 31
+
+ cv.addurnr t0, t3, t6
+ cv.addurnr t6, t0, t3
+ cv.addurnr t3, t6, t0
+
+ cv.addurn t0, t3, t6, 0
+ cv.addurn t6, t0, t3, 14
+ cv.addurn t3, t6, t0, 31
+
+ cv.clipr t0,t1,t2
+ cv.clipr t4,t2,t6
+ cv.clipr t3,t5,t1
+
+ cv.clip t0,t1,0
+ cv.clip t4,t2,5
+ cv.clip t3,t5,31
+
+ cv.clipur t0,t1,t2
+ cv.clipur t4,t2,t6
+ cv.clipur t3,t5,t1
+
+ cv.clipu t0,t1,0
+ cv.clipu t4,t2,5
+ cv.clipu t3,t5,31
+
+ cv.extbs t0,t1
+ cv.extbs t4,t2
+ cv.extbs t3,t5
+
+ cv.extbz t0,t1
+ cv.extbz t4,t2
+ cv.extbz t3,t5
+
+ cv.exths t0,t1
+ cv.exths t4,t2
+ cv.exths t3,t5
+
+ cv.exthz t0,t1
+ cv.exthz t4,t2
+ cv.exthz t3,t5
+
+ cv.max t0,t1,t2
+ cv.max t4,t2,t6
+ cv.max t3,t5,t1
+
+ cv.maxu t0,t1,t2
+ cv.maxu t4,t2,t6
+ cv.maxu t3,t5,t1
+
+ cv.min t0,t1,t2
+ cv.min t4,t2,t6
+ cv.min t3,t5,t1
+
+ cv.minu t0,t1,t2
+ cv.minu t4,t2,t6
+ cv.minu t3,t5,t1
+
+ cv.sle t0,t1,t2
+ cv.sle t4,t2,t6
+ cv.sle t3,t5,t1
+
+ cv.sleu t0,t1,t2
+ cv.sleu t4,t2,t6
+ cv.sleu t3,t5,t1
+
+ cv.subnr t0, t3, t6
+ cv.subnr t6, t0, t3
+ cv.subnr t3, t6, t0
+
+ cv.subn t0, t3, t6, 0
+ cv.subn t6, t0, t3, 6
+ cv.subn t3, t6, t0, 31
+
+ cv.subrnr t0, t3, t6
+ cv.subrnr t6, t0, t3
+ cv.subrnr t3, t6, t0
+
+ cv.subrn t0, t3, t6, 0
+ cv.subrn t6, t0, t3, 21
+ cv.subrn t3, t6, t0, 31
+
+ cv.subunr t0, t3, t6
+ cv.subunr t6, t0, t3
+ cv.subunr t3, t6, t0
+
+ cv.subun t0, t3, t6, 0
+ cv.subun t6, t0, t3, 24
+ cv.subun t3, t6, t0, 31
+
+ cv.suburnr t0, t3, t6
+ cv.suburnr t6, t0, t3
+ cv.suburnr t3, t6, t0
+
+ cv.suburn t0, t3, t6, 0
+ cv.suburn t6, t0, t3, 3
+ cv.suburn t3, t6, t0, 31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 418e77061df..7c89a53b591 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2357,6 +2357,73 @@
#define MASK_CV_MACURN 0xc000707f
#define MATCH_CV_MACHHURN 0xc000705b
#define MASK_CV_MACHHURN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+#define MATCH_CV_ABS 0x5000302b
+#define MASK_CV_ABS 0xfff0707f
+#define MATCH_CV_SLE 0x5200302b
+#define MASK_CV_SLE 0xfe00707f
+#define MATCH_CV_SLET 0x5200302b
+#define MASK_CV_SLET 0xfe00707f
+#define MATCH_CV_SLEU 0x5400302b
+#define MASK_CV_SLEU 0xfe00707f
+#define MATCH_CV_SLETU 0x5400302b
+#define MASK_CV_SLETU 0xfe00707f
+#define MATCH_CV_MIN 0x5600302b
+#define MASK_CV_MIN 0xfe00707f
+#define MATCH_CV_MINU 0x5800302b
+#define MASK_CV_MINU 0xfe00707f
+#define MATCH_CV_MAX 0x5a00302b
+#define MASK_CV_MAX 0xfe00707f
+#define MATCH_CV_MAXU 0x5c00302b
+#define MASK_CV_MAXU 0xfe00707f
+#define MATCH_CV_EXTHS 0x6000302b
+#define MASK_CV_EXTHS 0xfff0707f
+#define MATCH_CV_EXTHZ 0x6200302b
+#define MASK_CV_EXTHZ 0xfff0707f
+#define MATCH_CV_EXTBS 0x6400302b
+#define MASK_CV_EXTBS 0xfff0707f
+#define MATCH_CV_EXTBZ 0x6600302b
+#define MASK_CV_EXTBZ 0xfff0707f
+#define MATCH_CV_CLIP 0x7000302b
+#define MASK_CV_CLIP 0xfe00707f
+#define MATCH_CV_CLIPU 0x7200302b
+#define MASK_CV_CLIPU 0xfe00707f
+#define MATCH_CV_CLIPR 0x7400302b
+#define MASK_CV_CLIPR 0xfe00707f
+#define MATCH_CV_CLIPUR 0x7600302b
+#define MASK_CV_CLIPUR 0xfe00707f
+#define MATCH_CV_ADDNR 0x8000302b
+#define MASK_CV_ADDNR 0xfe00707f
+#define MATCH_CV_ADDUNR 0x8200302b
+#define MASK_CV_ADDUNR 0xfe00707f
+#define MATCH_CV_ADDRNR 0x8400302b
+#define MASK_CV_ADDRNR 0xfe00707f
+#define MATCH_CV_ADDURNR 0x8600302b
+#define MASK_CV_ADDURNR 0xfe00707f
+#define MATCH_CV_SUBNR 0x8800302b
+#define MASK_CV_SUBNR 0xfe00707f
+#define MATCH_CV_SUBUNR 0x8a00302b
+#define MASK_CV_SUBUNR 0xfe00707f
+#define MATCH_CV_SUBRNR 0x8c00302b
+#define MASK_CV_SUBRNR 0xfe00707f
+#define MATCH_CV_SUBURNR 0x8e00302b
+#define MASK_CV_SUBURNR 0xfe00707f
+#define MATCH_CV_ADDN 0x205b
+#define MASK_CV_ADDN 0xc000707f
+#define MATCH_CV_ADDUN 0x4000205b
+#define MASK_CV_ADDUN 0xc000707f
+#define MATCH_CV_ADDRN 0x8000205b
+#define MASK_CV_ADDRN 0xc000707f
+#define MATCH_CV_ADDURN 0xc000205b
+#define MASK_CV_ADDURN 0xc000707f
+#define MATCH_CV_SUBN 0x305b
+#define MASK_CV_SUBN 0xc000707f
+#define MATCH_CV_SUBUN 0x4000305b
+#define MASK_CV_SUBUN 0xc000707f
+#define MATCH_CV_SUBRN 0x8000305b
+#define MASK_CV_SUBRN 0xc000707f
+#define MATCH_CV_SUBURN 0xc000305b
+#define MASK_CV_SUBURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 153bff31e2c..88b0556399f 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
/* Vendor-specific (CORE-V) extract macros. */
+#define EXTRACT_CV_IS2_UIMM5(x) \
+ (RV_X(x, 20, 5))
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
@@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
/* Vendor-specific (CORE-V) encode macros. */
+#define ENCODE_CV_IS2_UIMM5(x) \
+ (RV_X(x, 0, 5) << 20)
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
@@ -450,6 +454,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
+ INSN_CLASS_XCVALU,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index b7a3f1ac2ea..83f4e7f5356 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -680,6 +680,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'c': /* Vendor-specific (CORE-V) operands. */
switch (*++oparg)
{
+ case '2':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_IS2_UIMM5 (l)));
+ break;
case '3':
print (info->stream, dis_style_immediate, "%d",
((int) EXTRACT_CV_IS3_UIMM5 (l)));
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1f8cfe967f2..4cee97e43bf 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2065,6 +2065,41 @@ const struct riscv_opcode riscv_opcodes[] =
{"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN, MASK_CV_MACURN, match_opcode, 0},
{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0},
+/* Vendor-specific (CORE-V) Xcvalu instructions. */
+{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0},
+{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, MASK_CV_EXTHS, match_opcode, 0},
+{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_EXTHZ, match_opcode, 0},
+{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, MASK_CV_EXTBS, match_opcode, 0},
+{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_EXTBZ, match_opcode, 0},
+{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLE, MASK_CV_SLE, match_opcode, 0},
+{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS},
+{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLEU, MASK_CV_SLEU, match_opcode, 0},
+{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLETU, match_opcode, INSN_ALIAS},
+{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, MASK_CV_MIN, match_opcode, 0},
+{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, MASK_CV_MINU, match_opcode, 0},
+{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, MASK_CV_MAX, match_opcode, 0},
+{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_MAXU, match_opcode, 0},
+{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIP, MASK_CV_CLIP, match_opcode, 0},
+{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIPU, MASK_CV_CLIPU, match_opcode, 0},
+{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_CLIPR, match_opcode, 0},
+{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_CLIPUR, match_opcode, 0},
+{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0},
+{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDUN, MASK_CV_ADDUN, match_opcode, 0},
+{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_ADDUNR, match_opcode, 0},
+{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDRN, MASK_CV_ADDRN, match_opcode, 0},
+{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDURN, MASK_CV_ADDURN, match_opcode, 0},
+{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_ADDNR, match_opcode, 0},
+{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_ADDRNR, match_opcode, 0},
+{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_ADDURNR, match_opcode, 0},
+{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBN, MASK_CV_SUBN, match_opcode, 0},
+{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBUN, MASK_CV_SUBUN, match_opcode, 0},
+{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBRN, MASK_CV_SUBRN, match_opcode, 0},
+{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBURN, MASK_CV_SUBURN, match_opcode, 0},
+{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SUBNR, match_opcode, 0},
+{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SUBUNR, match_opcode, 0},
+{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SUBRNR, match_opcode, 0},
+{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-10-02 2:02 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-10-02 2:02 ` [PATCH v3 2/2] RISC-V: Add support for XCValu " Mary Bennett
@ 2023-11-06 17:27 ` Mary Bennett
2023-11-07 4:12 ` Nelson Chu
2 siblings, 1 reply; 16+ messages in thread
From: Mary Bennett @ 2023-11-06 17:27 UTC (permalink / raw)
To: Mary Bennett, Binutils
[-- Attachment #1.1.1: Type: text/plain, Size: 7285 bytes --]
Hi
I'm wondering if there are any other changes required for these patches?
If not, are they all good to merge?
Kind regards,
Mary
On 02/10/2023 03:02, Mary Bennett wrote:
> Changes: v2 -> v3
> - Rebase against 7a5fa3dbe555794ce401a7435cb91f8695fc9847.
>
> Changes: v1 -> v2
> - Added MASK_<INSN> for each instruction, as suggested.
> - Changed operand 'x' to operand 'X', as suggested.
>
> This patch series presents the comprehensive implementation of the MAC and ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V instructions are described in the specification [1] and work can be
> found in the OpenHW group's Github repository [2].
>
> [1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> [2] github.com/openhwgroup/corev-binutils-gdb
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
>
> RISC-V: Add support for XCValu extension in CV32E40P
> RISC-V: Add support for XCVmac extension in CV32E40P
>
> bfd/elfxx-riscv.c | 11 ++
> gas/config/tc-riscv.c | 42 ++++-
> gas/doc/c-riscv.texi | 10 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
> gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
> gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
> gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-01.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-02.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
> .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-03.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
> .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
> .../gas/riscv/cv-alu-fail-operand-04.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.l | 3 +
> .../gas/riscv/cv-alu-fail-operand-04.s | 4 +
> .../gas/riscv/cv-alu-fail-operand-05.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-05.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-06.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-06.l | 9 +
> .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
> .../gas/riscv/cv-alu-fail-operand-07.d | 3 +
> .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
> .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
> gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
> gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
> gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
> gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
> gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
> include/opcode/riscv-opc.h | 104 ++++++++++++
> include/opcode/riscv.h | 12 ++
> opcodes/riscv-dis.c | 14 +-
> opcodes/riscv-opc.c | 61 +++++++
> 44 files changed, 1428 insertions(+), 2 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
>
--
Embecosm Limited
22 London Road
Southampton
SO15 2AF
Registered Number: 6577021.
Registered in England & Wales.
Name: Mary Bennett
Title: Compiler Tool Chain Engineer
Phone: 07802418997
Website: www.embecosm.com
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3203 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
2023-11-06 17:27 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
@ 2023-11-07 4:12 ` Nelson Chu
0 siblings, 0 replies; 16+ messages in thread
From: Nelson Chu @ 2023-11-07 4:12 UTC (permalink / raw)
To: Mary Bennett; +Cc: Binutils
[-- Attachment #1: Type: text/plain, Size: 426 bytes --]
On Tue, Nov 7, 2023 at 1:27 AM Mary Bennett <mary.bennett@embecosm.com>
wrote:
> Hi
>
> I'm wondering if there are any other changes required for these patches?
> If not, are they all good to merge?
>
> Kind regards,
>
> Mary
>
No, at least looks good to me, so committed. We can update them if any
changes are needed in the future patches.
Thanks for contributing the vendor stuffs to upstream
Nelson
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-11-07 4:12 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-05 14:52 [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-07 4:35 ` Nelson Chu
2023-09-05 14:53 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-09-07 4:37 ` Nelson Chu
2023-09-07 4:49 ` [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Nelson Chu
2023-09-07 6:57 ` Kito Cheng
2023-09-07 10:11 ` Tsukasa OI
2023-09-12 14:24 ` [PATCH v2 " Mary Bennett
2023-09-12 14:24 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-12 14:24 ` [PATCH v2 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-10-02 2:02 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-10-02 2:02 ` [PATCH v3 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-11-06 17:27 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-11-07 4:12 ` Nelson Chu
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