* [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function Victor Do Nascimento
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 3 +++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-tbl.h | 4 ++++
4 files changed, 10 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 7eb732adbb6..66df5b863dd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10335,6 +10335,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
{"d128", AARCH64_FEATURE (D128),
AARCH64_FEATURE (LSE128)},
+ {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index ccf18ee2661..61044b78190 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -276,6 +276,9 @@ automatically cause those extensions to be disabled.
@tab Enable TRCIT instruction.
@item @code{d128} @tab Armv9.4-A @tab No
@tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
+@item @code{rcpc3} @tab Armv9.4-A @tab No
+ @tab Enable the rcpc3 additional Support for Release Consistency Model
+ Extension. This implies @code{rcpc2}.
@end multitable
@node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9d64d7a0ebe..8ac48edf6a8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,6 +222,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PMUv3_ICNTR,
/* Performance Monitors Synchronous-Exception-Based Event Extension. */
AARCH64_FEATURE_SEBEP,
+ /* RCPC3 instructions. */
+ AARCH64_FEATURE_RCPC3,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0cf195d0321..708459e287d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2608,6 +2608,9 @@ static const aarch64_feature_set aarch64_feature_the =
AARCH64_FEATURE (THE);
static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
+static const aarch64_feature_set aarch64_feature_rcpc3 =
+ AARCH64_FEATURE (RCPC3);
+
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2670,6 +2673,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define D128 &aarch64_feature_d128
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
+#define RCPC3 &aarch64_feature_rcpc3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors Victor Do Nascimento
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
The allowed immediate offsets in integer rcpc3 load store instructions
are not encoded explicitly in the instruction itself, being rather
implicitly equivalent to the amount of data loaded/stored by the
instruction.
This leads to the requirement that this quantity be calculated based on
the number of registers involved in the transfer, either as data
source or destination registers and their respective qualifiers.
This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)'
implemented here, using a cumulative sum of qualifier sizes preceding
the address operand in the OPNDS operand list argument.
---
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-opc.c | 22 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8ac48edf6a8..fe54de7cffe 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1832,6 +1832,9 @@ aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
extern bool
aarch64_cpu_supports_inst_p (aarch64_feature_set, aarch64_inst *);
+extern int
+calc_ldst_datasize (const aarch64_opnd_info *opnds);
+
#ifdef DEBUG_AARCH64
extern int debug_dump;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e3ad32f5a1e..bf506546fd0 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1658,6 +1658,28 @@ check_za_access (const aarch64_opnd_info *opnd,
return true;
}
+/* Given a load/store operation, calculate the size of transferred data via a
+ cumulative sum of qualifier sizes preceding the address operand in the
+ OPNDS operand list argument. */
+int
+calc_ldst_datasize (const aarch64_opnd_info *opnds)
+{
+ unsigned num_bytes = 0; /* total number of bytes transferred. */
+ enum aarch64_operand_class opnd_class;
+ enum aarch64_opnd type;
+
+ for (int i = 0; i < AARCH64_MAX_OPND_NUM; i++)
+ {
+ type = opnds[i].type;
+ opnd_class = aarch64_operands[type].op_class;
+ if (opnd_class == AARCH64_OPND_CLASS_ADDRESS)
+ break;
+ num_bytes += aarch64_get_qualifier_esize (opnds[i].qualifier);
+ }
+ return num_bytes;
+}
+
+
/* General constraint checking based on operand code.
Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 1/8] aarch64: rcpc3: Add +rcpc3 architectural feature support flag Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 2/8] aarch64: rcpc3: Create implicit load/store size calc function Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types Victor Do Nascimento
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.
The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.
This therefore defines the following functions:
- aarch64_ins_rcpc3_addr_opt_offset
- aarch64_ins_rcpc3_addr_offset
- aarch64_ext_rcpc3_addr_opt_offset
- aarch64_ext_rcpc3_addr_offset
It extends the `do_special_{encoding|decoding}' functions and defines
two rcpc3 instruction fields:
- FLD_opc2
- FLD_rcpc3_size
---
include/opcode/aarch64.h | 6 ++-
opcodes/aarch64-asm.c | 56 +++++++++++++++++++++++++++
opcodes/aarch64-asm.h | 2 +
opcodes/aarch64-dis.c | 84 ++++++++++++++++++++++++++++++++++++++++
opcodes/aarch64-dis.h | 3 ++
opcodes/aarch64-opc.c | 2 +
opcodes/aarch64-opc.h | 2 +
7 files changed, 153 insertions(+), 2 deletions(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index fe54de7cffe..dc9c98353d4 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1261,7 +1261,9 @@ extern const aarch64_opcode aarch64_opcode_table[];
allow. This impacts the constraintts on assembly but yelds no
impact on disassembly. */
#define F_OPD_NARROW (1ULL << 33)
-/* Next bit is 34. */
+/* RCPC3 instruction has the field of 'size'. */
+#define F_RCPC3_SIZE (1ULL << 34)
+/* Next bit is 35. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
@@ -1328,7 +1330,7 @@ static inline bool
opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
- | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0;
+ | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND | F_RCPC3_SIZE)) != 0;
}
\f
struct aarch64_name_value_pair
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 1db290eea7e..4be60964102 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -702,6 +702,24 @@ aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
return true;
}
+/* Encode the address operand for e.g.
+ stlur <Xt>, [<Xn|SP>{, <amount>}]. */
+bool
+aarch64_ins_rcpc3_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ insert_field (self->fields[0], code, info->addr.base_regno, 0);
+
+ /* simm9 */
+ int imm = info->addr.offset.imm;
+ insert_field (self->fields[1], code, imm, 0);
+
+ return true;
+}
+
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
bool
aarch64_ins_addr_simm (const aarch64_operand *self,
@@ -736,6 +754,28 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
return true;
}
+/* Encode the address operand, potentially offset by the load/store ammount,
+ e.g. LDIAPP <Xt>, <Xt2> [<Xn|SP>, #<simm>]
+ and STILP <Xt>, <Xt2> [<Xn|SP>], #<simm>.*/
+bool
+aarch64_ins_rcpc3_addr_opt_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int imm;
+
+ /* Rn */
+ insert_field (FLD_Rn, code, info->addr.base_regno, 0);
+ /* simm */
+ imm = info->addr.offset.imm;
+ if (!imm)
+ insert_field (FLD_opc2, code, 1, 0);
+
+ return true;
+}
+
/* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
bool
aarch64_ins_addr_simm10 (const aarch64_operand *self,
@@ -1858,6 +1898,22 @@ do_special_encoding (struct aarch64_inst *inst)
? 1 : 0;
insert_field (FLD_lse_sz, &inst->value, value, 0);
}
+ if (inst->opcode->flags & F_RCPC3_SIZE)
+ {
+ switch (inst->operands[0].qualifier)
+ {
+ case AARCH64_OPND_QLF_W: value = 2; break;
+ case AARCH64_OPND_QLF_X: value = 3; break;
+ case AARCH64_OPND_QLF_S_B: value = 0; break;
+ case AARCH64_OPND_QLF_S_H: value = 1; break;
+ case AARCH64_OPND_QLF_S_S: value = 2; break;
+ case AARCH64_OPND_QLF_S_D: value = 3; break;
+ case AARCH64_OPND_QLF_S_Q: value = 0; break;
+ default: return;
+ }
+ insert_field (FLD_rcpc3_size, &inst->value, value, 0);
+ }
+
if (inst->opcode->flags & F_SIZEQ)
encode_sizeq (inst);
if (inst->opcode->flags & F_FPTYPE)
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index a3bf7bda013..0b4ae7625db 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -112,6 +112,8 @@ AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30);
AARCH64_DECL_OPD_INSERTER (ins_simple_index);
AARCH64_DECL_OPD_INSERTER (ins_plain_shrimm);
+AARCH64_DECL_OPD_INSERTER (ins_rcpc3_addr_opt_offset);
+AARCH64_DECL_OPD_INSERTER (ins_rcpc3_addr_offset);
#undef AARCH64_DECL_OPD_INSERTER
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 7e088a93c10..0734c448e32 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1032,6 +1032,70 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return true;
}
+/* Decode the address operand for rcpc3 instructions with optional load/store
+ datasize offset, e.g. STILPP <Xs>, <Xt>, [<Xn|SP>{,#-16}]! and
+ LIDAP <Xs>, <Xt>, [<Xn|SP>]{,#-16}. */
+bool
+aarch64_ext_rcpc3_addr_opt_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *err ATTRIBUTE_UNUSED)
+{
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ if (!extract_field (FLD_opc2, code, 0))
+ {
+ info->addr.writeback = 1;
+
+ enum aarch64_opnd type;
+ for (int i = 0; i < AARCH64_MAX_OPND_NUM; i++)
+ {
+ aarch64_opnd_info opnd = info[i];
+ type = opnd.type;
+ if (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS)
+ break;
+ }
+
+ assert (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS);
+ int offset = calc_ldst_datasize (inst->operands);
+
+ switch (type)
+ {
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ info->addr.offset.imm = -offset;
+ info->addr.preind = 1;
+ break;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ info->addr.offset.imm = offset;
+ info->addr.postind = 1;
+ break;
+ default:
+ return false;
+ }
+ }
+ return true;
+}
+
+bool
+aarch64_ext_rcpc3_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+
+ /* Rn */
+ info->addr.base_regno = extract_field (self->fields[0], code, 0);
+
+ /* simm9 */
+ aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
+ info->addr.offset.imm = sign_extend (imm, 8);
+ return true;
+}
+
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bool
@@ -2465,6 +2529,26 @@ do_special_decoding (aarch64_inst *inst)
value = extract_field (FLD_lse_sz, inst->value, 0);
inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
}
+ /* rcpc3 'size' field. */
+ if (inst->opcode->flags & F_RCPC3_SIZE)
+ {
+ value = extract_field (FLD_rcpc3_size, inst->value, 0);
+ for (int i = 0;
+ aarch64_operands[inst->operands[i].type].op_class != AARCH64_OPND_CLASS_ADDRESS;
+ i++)
+ {
+ if (aarch64_operands[inst->operands[i].type].op_class
+ == AARCH64_OPND_CLASS_INT_REG)
+ inst->operands[i].qualifier = get_greg_qualifier_from_value (value & 1);
+ else if (aarch64_operands[inst->operands[i].type].op_class
+ == AARCH64_OPND_CLASS_FP_REG)
+ {
+ value += (extract_field (FLD_opc1, inst->value, 0) << 2);
+ inst->operands[i].qualifier = get_sreg_qualifier_from_value (value);
+ }
+ }
+ }
+
/* size:Q fields. */
if (inst->opcode->flags & F_SIZEQ)
return decode_sizeq (inst);
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 20387db7b39..2d3af5b3ee3 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -136,6 +136,9 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm);
+AARCH64_DECL_OPD_EXTRACTOR (ext_rcpc3_addr_opt_offset);
+AARCH64_DECL_OPD_EXTRACTOR (ext_rcpc3_addr_offset);
+
#undef AARCH64_DECL_OPD_EXTRACTOR
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index bf506546fd0..9d994c12f1a 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -400,6 +400,8 @@ const aarch64_field fields[] =
{ 22, 1 }, /* sz: 1-bit element size select. */
{ 22, 2 }, /* type: floating point type field in fp data inst. */
{ 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
+ { 12, 4 }, /* opc2: in rcpc3 ld/st pair inst deciding the pre/post-index. */
+ { 30, 2 }, /* rcpc3_size: in rcpc3 ld/st pair, field controls Rt/Rt2 width. */
};
enum aarch64_operand_class
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index f193a90ecc5..b05aaadb5dc 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -210,6 +210,8 @@ enum aarch64_field_kind
FLD_sz,
FLD_type,
FLD_vldst_size,
+ FLD_opc2,
+ FLD_rcpc3_size,
};
/* Field description. */
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (2 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 3/8] aarch64: rcpc3: Define address operand fields and inserter/extractors Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p Victor Do Nascimento
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
---
gas/config/tc-aarch64.c | 65 ++++++++++++++++++++++++++++++++++++++++
include/opcode/aarch64.h | 5 ++++
opcodes/aarch64-opc.c | 5 ++++
opcodes/aarch64-tbl.h | 16 +++++++++-
4 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 66df5b863dd..9a3480b565b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7263,7 +7263,52 @@ parse_operands (char *str, const aarch64_opcode *opcode)
inst.reloc.pc_rel = 1;
}
break;
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.writeback)
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ {
+ char *start = str;
+ /* First use the normal address-parsing routines, to get
+ the usual syntax errors. */
+ po_misc_or_fail (parse_address (&str, info));
+ if ((operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
+ && info->addr.writeback && info->addr.preind)
+ || (operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
+ && info->addr.writeback && info->addr.postind))
+ {
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+ }
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ /* Then retry, matching the specific syntax of these addresses. */
+ str = start;
+ po_char_or_fail ('[');
+ po_reg_or_fail (REG_TYPE_R64_SP);
+ po_char_or_fail (']');
+ break;
+ }
case AARCH64_OPND_ADDR_SIMPLE:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
@@ -7384,6 +7429,26 @@ parse_operands (char *str, const aarch64_opcode *opcode)
/* skip_p */ 0);
break;
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind
+ || info->addr.writeback)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ set_syntax_error (_("relocation not allowed"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
case AARCH64_OPND_ADDR_UIMM12:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dc9c98353d4..f337d14eb24 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -783,6 +783,11 @@ enum aarch64_opnd
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */
+ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
+ AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
+ AARCH64_OPND_RCPC3_ADDR_OFFSET
};
/* Qualifier constrains an operand. It either specifies a variant of an
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 9d994c12f1a..cf0eabeb946 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4488,7 +4488,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_ADDR_SIMM10:
case AARCH64_OPND_ADDR_SIMM11:
case AARCH64_OPND_ADDR_SIMM13:
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
case AARCH64_OPND_ADDR_OFFSET:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
case AARCH64_OPND_SME_ADDR_RI_U4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 708459e287d..3176cb877c2 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6875,4 +6875,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \
"an 8-bit signed immediate") \
Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \
- "an 8-bit unsigned immediate")
+ "an 8-bit unsigned immediate") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_POSTIND", 0, F(), \
+ "an address with post-incrementing by ammount of loaded bytes") \
+ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
+ "RCPC3_ADDR_PREIND_WB", 0, F(), \
+ "an address with pre-incrementing with write-back by ammount of stored bytes") \
+ Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \
+ "an address with an optional 8-bit signed immediate offset")
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (3 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 4/8] aarch64: rcpc3: New RCPC3_ADDR operand types Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro Victor Do Nascimento
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
---
opcodes/aarch64-opc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index cf0eabeb946..e6f2d937875 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2046,6 +2046,19 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
}
break;
+ case rcpc3:
+ if (opnd->addr.writeback)
+ if ((type == AARCH64_OPND_RCPC3_ADDR_PREIND_WB
+ && !opnd->addr.preind)
+ || (type == AARCH64_OPND_RCPC3_ADDR_POSTIND
+ && !opnd->addr.postind))
+ {
+ set_syntax_error (mismatch_detail, idx,
+ _("unexpected address writeback"));
+ return 0;
+ }
+
+ break;
default:
assert (opnd->addr.writeback == 0);
break;
@@ -2425,6 +2438,33 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
modifiers = 1 << AARCH64_MOD_UXTW;
goto sve_zz_operand;
+ case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
+ case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
+ case AARCH64_OPND_RCPC3_ADDR_POSTIND:
+ {
+ int num_bytes = calc_ldst_datasize (opnds);
+ int abs_offset = (type == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
+ || type == AARCH64_OPND_RCPC3_ADDR_PREIND_WB)
+ ? opnd->addr.offset.imm * -1
+ : opnd->addr.offset.imm;
+ if ((int) num_bytes != abs_offset
+ && opnd->addr.offset.imm != 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("invalid increment amount"));
+ return 0;
+ }
+ }
+ break;
+
+ case AARCH64_OPND_RCPC3_ADDR_OFFSET:
+ if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, -256, 255);
+ return 0;
+ }
+
default:
break;
}
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (4 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 5/8] aarch64: rcpc3: add support in general_constraint_met_p Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns Victor Do Nascimento
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
This patch adds the necessary macro for encoding FEAT_RCPC3-dependent
instructions in Binutils.
---
opcodes/aarch64-tbl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 3176cb877c2..3f24603069b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2829,6 +2829,8 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
{ NAME, OPCODE, MASK, the, 0, THE, OPS, QUALS, FLAGS, 0, 0, NULL }
#define D128_THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, the, 0, D128_THE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define RCPC3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, RCPC3, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (5 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 6/8] aarch64: rcpc3: Define RCPC3_INSN macro Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-12 16:56 ` [PATCH 8/8] aarch64: rcpc3: Add FP " Victor Do Nascimento
2024-01-15 11:55 ` [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Nick Clifton
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Along with the relevant unit tests and updates to the existing
regression tests, this adds support for the following novel rcpc3
insns:
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>]
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>]
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16
STILP <Wt1>, <Wt2>, [<Xn|SP>]
STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
STILP <Xt1>, <Xt2>, [<Xn|SP>]
STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]!
LDAPR <Wt>, [<Xn|SP>], #4
LDAPR <Xt>, [<Xn|SP>], #8
STLR <Wt>, [<Xn|SP>, #-4]!
STLR <Xt>, [<Xn|SP>, #-8]!
---
gas/testsuite/gas/aarch64/illegal-ldapr.l | 4 ++--
gas/testsuite/gas/aarch64/rcpc3-fail.d | 3 +++
gas/testsuite/gas/aarch64/rcpc3-fail.l | 9 +++++++++
gas/testsuite/gas/aarch64/rcpc3-fail.s | 13 +++++++++++++
gas/testsuite/gas/aarch64/rcpc3.d | 21 +++++++++++++++++++++
gas/testsuite/gas/aarch64/rcpc3.s | 17 +++++++++++++++++
include/opcode/aarch64.h | 1 +
opcodes/aarch64-tbl.h | 5 +++++
8 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.d
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.l
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fail.s
create mode 100644 gas/testsuite/gas/aarch64/rcpc3.d
create mode 100644 gas/testsuite/gas/aarch64/rcpc3.s
diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l
index 5e3ca6d2e5c..8811b730011 100644
--- a/gas/testsuite/gas/aarch64/illegal-ldapr.l
+++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l
@@ -22,7 +22,7 @@
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
-[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!'
+[^:]+:7: Error: unexpected address writeback at operand 2 -- `ldapr w1,\[x7,#8\]!'
[^:]+:23: Info: macro .*
-[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8'
+[^:]+:8: Error: invalid increment amount at operand 2 -- `ldapr w1,\[x7\],#8'
[^:]+:23: Info: macro .*
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.d b/gas/testsuite/gas/aarch64/rcpc3-fail.d
new file mode 100644
index 00000000000..508a27f5a39
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fail.d
@@ -0,0 +1,3 @@
+#name: RCPC3 GPR load/store illegal
+#as: -march=armv8.3-a+rcpc3 -mno-verbose-error
+#error_output: rcpc3-fail.l
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.l b/gas/testsuite/gas/aarch64/rcpc3-fail.l
new file mode 100644
index 00000000000..4b33c8524e5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fail.l
@@ -0,0 +1,9 @@
+[^:]+: Assembler messages:
+[^:]+:3: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp w0,w1,\[x3,#8\]'
+[^:]+:4: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp x0,x1,\[x3,#16\]'
+[^:]+:6: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp w0,w1,\[x3,#8\]'
+[^:]+:7: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp x0,x1,\[x3,#16\]'
+[^:]+:9: Error: invalid addressing mode at operand 3 -- `stilp w0,w1,\[x3\],#8'
+[^:]+:10: Error: invalid addressing mode at operand 3 -- `stilp x0,x1,\[x3\],#16'
+[^:]+:12: Error: invalid addressing mode at operand 3 -- `ldiapp w0,w1,\[x3,#-8\]!'
+[^:]+:13: Error: invalid addressing mode at operand 3 -- `ldiapp x0,x1,\[x3,#-16\]!'
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.s b/gas/testsuite/gas/aarch64/rcpc3-fail.s
new file mode 100644
index 00000000000..23b9eaaf19a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fail.s
@@ -0,0 +1,13 @@
+.text
+
+ ldiapp w0, w1, [x3, #8]
+ ldiapp x0, x1, [x3, #16]
+
+ stilp w0, w1, [x3, #8]
+ stilp x0, x1, [x3, #16]
+
+ stilp w0, w1, [x3], #8
+ stilp x0, x1, [x3], #16
+
+ ldiapp w0, w1, [x3, #-8]!
+ ldiapp x0, x1, [x3, #-16]!
diff --git a/gas/testsuite/gas/aarch64/rcpc3.d b/gas/testsuite/gas/aarch64/rcpc3.d
new file mode 100644
index 00000000000..4560ed09e5d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3.d
@@ -0,0 +1,21 @@
+#name: RCPC3 GPR load/store
+#as: -march=armv8.2-a+rcpc3
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: d9411860 ldiapp x0, x1, \[x3\]
+ 4: 99411860 ldiapp w0, w1, \[x3\]
+ 8: d9410860 ldiapp x0, x1, \[x3\], #16
+ c: 99410860 ldiapp w0, w1, \[x3\], #8
+ 10: d9011860 stilp x0, x1, \[x3\]
+ 14: 99011860 stilp w0, w1, \[x3\]
+ 18: d9010860 stilp x0, x1, \[x3, #-16\]!
+ 1c: 99010860 stilp w0, w1, \[x3, #-8\]!
+ 20: 99c00841 ldapr w1, \[x2\], #4
+ 24: d9c00841 ldapr x1, \[x2\], #8
+ 28: 99800841 stlr w1, \[x2, #-4\]!
+ 2c: d9800841 stlr x1, \[x2, #-8\]!
diff --git a/gas/testsuite/gas/aarch64/rcpc3.s b/gas/testsuite/gas/aarch64/rcpc3.s
new file mode 100644
index 00000000000..2a877341e41
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3.s
@@ -0,0 +1,17 @@
+.text
+
+ ldiapp x0, x1, [x3]
+ ldiapp w0, w1, [x3]
+ ldiapp x0, x1, [x3], #16
+ ldiapp w0, w1, [x3], #8
+
+ stilp x0, x1, [x3]
+ stilp w0, w1, [x3]
+ stilp x0, x1, [x3, #-16]!
+ stilp w0, w1, [x3, #-8]!
+
+ ldapr w1, [x2], #4
+ ldapr x1, [x2], #8
+
+ stlr w1, [x2, #-4]!
+ stlr x1, [x2, #-8]!
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f337d14eb24..82894ba2400 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -994,6 +994,7 @@ enum aarch64_insn_class
cssc,
gcs,
the,
+ rcpc3
};
/* Opcode enumerators. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 3f24603069b..5a403811102 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4159,6 +4159,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
_LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
_LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
_LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+ /* RCPC3 extension. */
+ RCPC3_INSN ("ldiapp", 0x19400800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_POSTIND), QL_R2NIL, F_RCPC3_SIZE),
+ RCPC3_INSN ("stilp", 0x19000800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_PREIND_WB), QL_R2NIL, F_RCPC3_SIZE),
+ RCPC3_INSN ("ldapr", 0x19c00800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_POSTIND), QL_R1NIL, F_RCPC3_SIZE),
+ RCPC3_INSN ("stlr", 0x19800800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_PREIND_WB), QL_R1NIL, F_RCPC3_SIZE),
/* Move wide (immediate). */
CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS),
CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 8/8] aarch64: rcpc3: Add FP load/store insns
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (6 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 7/8] aarch64: rcpc3: Add integer load/store insns Victor Do Nascimento
@ 2024-01-12 16:56 ` Victor Do Nascimento
2024-01-15 11:55 ` [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Nick Clifton
8 siblings, 0 replies; 10+ messages in thread
From: Victor Do Nascimento @ 2024-01-12 16:56 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
---
gas/testsuite/gas/aarch64/rcpc3-fp-fail.d | 3 +++
gas/testsuite/gas/aarch64/rcpc3-fp-fail.l | 13 +++++++++++
gas/testsuite/gas/aarch64/rcpc3-fp-fail.s | 27 +++++++++++++++++++++++
gas/testsuite/gas/aarch64/rcpc3-fp.d | 26 ++++++++++++++++++++++
gas/testsuite/gas/aarch64/rcpc3-fp.s | 21 ++++++++++++++++++
opcodes/aarch64-tbl.h | 4 ++++
6 files changed, 94 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fp-fail.d
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fp-fail.l
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fp-fail.s
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fp.d
create mode 100644 gas/testsuite/gas/aarch64/rcpc3-fp.s
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fp-fail.d b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.d
new file mode 100644
index 00000000000..31c12793a03
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.d
@@ -0,0 +1,3 @@
+#name: RCPC3 fp load/store illegal
+#as: -march=armv8.3-a+rcpc3 -mno-verbose-error
+#error_output: rcpc3-fp-fail.l
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fp-fail.l b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.l
new file mode 100644
index 00000000000..20c08f8901a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.l
@@ -0,0 +1,13 @@
+[^:]+: Assembler messages:
+[^:]+:3: Error: register element index out of range 0 to 1 at operand 1 -- `stl1 {v1.d}\[-1\],\[x1\]'
+[^:]+:6: Error: register element index out of range 0 to 1 at operand 1 -- `stl1 {v1.d}\[2\],\[x1\]'
+[^:]+:8: Error: register element index out of range 0 to 1 at operand 1 -- `ldap1 {v2.d}\[-1\],\[sp\]'
+[^:]+:11: Error: register element index out of range 0 to 1 at operand 1 -- `ldap1 {v2.d}\[2\],\[sp\]'
+[^:]+:13: Error: immediate value out of range -256 to 255 at operand 2 -- `ldapur b1,\[x1,#-257\]'
+[^:]+:16: Error: immediate value out of range -256 to 255 at operand 2 -- `ldapur b1,\[x1,#256\]'
+[^:]+:18: Error: immediate value out of range -256 to 255 at operand 2 -- `stlur q1,\[x1,#-257\]'
+[^:]+:21: Error: immediate value out of range -256 to 255 at operand 2 -- `stlur q1,\[x1,#256\]'
+[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldapur b1,\[x1\],#255'
+[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapur b1,\[x1,#-255\]!'
+[^:]+:26: Error: invalid addressing mode at operand 2 -- `stlur b1,\[x1\],#255'
+[^:]+:27: Error: invalid addressing mode at operand 2 -- `stlur b1,\[x1,#-255\]!'
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fp-fail.s b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.s
new file mode 100644
index 00000000000..d5d92002c0f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fp-fail.s
@@ -0,0 +1,27 @@
+.text
+
+ stl1 { v1.d }[-1], [x1] // BAD
+ stl1 { v1.d }[0], [x1] // OK
+ stl1 { v1.d }[1], [x1] // OK
+ stl1 { v1.d }[2], [x1] // BAD
+
+ ldap1 { v2.d }[-1], [sp] // BAD
+ ldap1 { v2.d }[0], [sp] // OK
+ ldap1 { v2.d }[1], [sp] // OK
+ ldap1 { v2.d }[2], [sp] // BAD
+
+ ldapur b1, [x1, #-257] // BAD
+ ldapur b1, [x1, #-256] // OK
+ ldapur b1, [x1, #255] // OK
+ ldapur b1, [x1, #256] // BAD
+
+ stlur q1, [x1, #-257] // BAD
+ stlur q1, [x1, #-256] // OK
+ stlur q1, [x1, #255] // OK
+ stlur q1, [x1, #256] // BAD
+
+ ldapur b1, [x1], #255 // BAD
+ ldapur b1, [x1, #-255]! // BAD
+
+ stlur b1, [x1], #255 // BAD
+ stlur b1, [x1, #-255]! // BAD
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fp.d b/gas/testsuite/gas/aarch64/rcpc3-fp.d
new file mode 100644
index 00000000000..b070e42ade5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fp.d
@@ -0,0 +1,26 @@
+#name: RCPC3 fp load/store
+#as: -march=armv8.2-a+rcpc3
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: 0d4187e1 ldap1 {v1.d}\[0], \[sp]
+ 4: 4d418422 ldap1 {v2.d}\[1], \[x1]
+ 8: 0d018443 stl1 {v3.d}\[0], \[x2]
+ c: 4d018464 stl1 {v4.d}\[1], \[x3]
+ 10: 1d400be1 ldapur b1, \[sp\]
+ 14: 1d500be1 ldapur b1, \[sp, #-256\]
+ 18: 1d4ffbe1 ldapur b1, \[sp, #255\]
+ 1c: 5d400842 ldapur h2, \[x2\]
+ 20: 9d400863 ldapur s3, \[x3\]
+ 24: dd400884 ldapur d4, \[x4\]
+ 28: 1dc00be1 ldapur q1, \[sp\]
+ 2c: 1d000be1 stlur b1, \[sp\]
+ 30: 1d100be1 stlur b1, \[sp, #-256\]
+ 34: 1d0ffbe1 stlur b1, \[sp, #255\]
+ 38: 9d000863 stlur s3, \[x3\]
+ 3c: dd000884 stlur d4, \[x4\]
+ 40: 1d800be1 stlur q1, \[sp\]
diff --git a/gas/testsuite/gas/aarch64/rcpc3-fp.s b/gas/testsuite/gas/aarch64/rcpc3-fp.s
new file mode 100644
index 00000000000..d99f96d8cb4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rcpc3-fp.s
@@ -0,0 +1,21 @@
+.text
+
+ ldap1 {v1.d}[0], [sp]
+ ldap1 {v2.d}[1], [x1]
+ stl1 {v3.d}[0], [x2]
+ stl1 {v4.d}[1], [x3]
+
+ ldapur b1, [sp]
+ ldapur b1, [sp, #-256]
+ ldapur b1, [sp, #255]
+ ldapur h2, [x2]
+ ldapur s3, [x3]
+ ldapur d4, [x4]
+ ldapur q1, [sp]
+
+ stlur b1, [sp]
+ stlur b1, [sp, #-256]
+ stlur b1, [sp, #255]
+ stlur s3, [x3]
+ stlur d4, [x4]
+ stlur q1, [sp]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5a403811102..5cc7d031e5a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4164,6 +4164,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
RCPC3_INSN ("stilp", 0x19000800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_PREIND_WB), QL_R2NIL, F_RCPC3_SIZE),
RCPC3_INSN ("ldapr", 0x19c00800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_POSTIND), QL_R1NIL, F_RCPC3_SIZE),
RCPC3_INSN ("stlr", 0x19800800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_PREIND_WB), QL_R1NIL, F_RCPC3_SIZE),
+ RCPC3_INSN ("stl1", 0x0d018400, 0xbffffc00, rcpc3, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_IMM_D, F_OD(1)),
+ RCPC3_INSN ("ldap1", 0x0d418400, 0xbffffc00, rcpc3, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_IMM_D, F_OD(1)),
+ RCPC3_INSN ("ldapur", 0x1d400800, 0x3f600C00, rcpc3, OP2 (Ft, RCPC3_ADDR_OFFSET), QL_LDST_FP, F_RCPC3_SIZE),
+ RCPC3_INSN ("stlur", 0x1d000800, 0x3f600C00, rcpc3, OP2 (Ft, RCPC3_ADDR_OFFSET), QL_LDST_FP, F_RCPC3_SIZE),
/* Move wide (immediate). */
CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS),
CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension
2024-01-12 16:56 [PATCH 0/8] aarch64: Enable the RCpc3 (Release Consistency) extension Victor Do Nascimento
` (7 preceding siblings ...)
2024-01-12 16:56 ` [PATCH 8/8] aarch64: rcpc3: Add FP " Victor Do Nascimento
@ 2024-01-15 11:55 ` Nick Clifton
8 siblings, 0 replies; 10+ messages in thread
From: Nick Clifton @ 2024-01-15 11:55 UTC (permalink / raw)
To: Victor Do Nascimento, binutils; +Cc: richard.earnshaw
On 1/12/24 16:56, Victor Do Nascimento wrote:
> Given the introduction of the third set of Release Consistency
> processor consistent (RCpc) memory model-compliant instructions in
> the form of FEAT_LRCPC3 as an optional extension from Armv8.2-a
> onward, this patch series adds the relevant machinery to Binutils to
> add support for the instructions it adds to the instruction set.
>
> Victor Do Nascimento (8):
> aarch64: rcpc3: Add +rcpc3 architectural feature support flag
> aarch64: rcpc3: Create implicit load/store size calc function
> aarch64: rcpc3: Define address operand fields and inserter/extractors
> aarch64: rcpc3: New RCPC3_ADDR operand types
> aarch64: rcpc3: add support in general_constraint_met_p
> aarch64: rcpc3: Define RCPC3_INSN macro
> aarch64: rcpc3: Add integer load/store insns
> aarch64: rcpc3: Add FP load/store insns
Patch series approved - please apply. (You will need to rebase your
patches as they do not apply cleanly to the latest mainline sources).
If you are quick you can get this series in before the 2.42 branch
is created. If not, you have approval to apply the patch series to
the branch as well.
Cheers
Nick
^ permalink raw reply [flat|nested] 10+ messages in thread