* [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction.
@ 2023-11-16 11:26 Srinath Parvathaneni
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
2023-11-16 11:55 ` [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Richard Earnshaw
0 siblings, 2 replies; 11+ messages in thread
From: Srinath Parvathaneni @ 2023-11-16 11:26 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc
[-- Attachment #1: Type: text/plain, Size: 220 bytes --]
Hi,
This patch adds support for FEAT_PRFMSLC feature which enables
SLC target for PRFM instructions.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb17872.patch --]
[-- Type: text/plain, Size: 6200 bytes --]
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index bb1a94cb0204b953ba204365c075493622d24c16..dbb7c0a96ffbe7043865f29dd04cab6807388dd0 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -240,16 +240,16 @@ Disassembly of section \.text:
.*: f8af6be5 prfm pldl3strm, \[sp, x15\]
.*: f8be58e5 prfm pldl3strm, \[x7, w30, uxtw #3\]
.*: f9800c65 prfm pldl3strm, \[x3, #24\]
-.*: d8000006 prfm #0x06, 0 <LABEL1>
+.*: d8000006 prfm pldslckeep, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6be6 prfm #0x06, \[sp, x15\]
-.*: f8be58e6 prfm #0x06, \[x7, w30, uxtw #3\]
-.*: f9800c66 prfm #0x06, \[x3, #24\]
-.*: d8000007 prfm #0x07, 0 <LABEL1>
+.*: f8af6be6 prfm pldslckeep, \[sp, x15\]
+.*: f8be58e6 prfm pldslckeep, \[x7, w30, uxtw #3\]
+.*: f9800c66 prfm pldslckeep, \[x3, #24\]
+.*: d8000007 prfm pldslcstrm, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6be7 prfm #0x07, \[sp, x15\]
-.*: f8be58e7 prfm #0x07, \[x7, w30, uxtw #3\]
-.*: f9800c67 prfm #0x07, \[x3, #24\]
+.*: f8af6be7 prfm pldslcstrm, \[sp, x15\]
+.*: f8be58e7 prfm pldslcstrm, \[x7, w30, uxtw #3\]
+.*: f9800c67 prfm pldslcstrm, \[x3, #24\]
.*: d8000008 prfm plil1keep, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
.*: f8af6be8 prfm plil1keep, \[sp, x15\]
@@ -280,16 +280,16 @@ Disassembly of section \.text:
.*: f8af6bed prfm plil3strm, \[sp, x15\]
.*: f8be58ed prfm plil3strm, \[x7, w30, uxtw #3\]
.*: f9800c6d prfm plil3strm, \[x3, #24\]
-.*: d800000e prfm #0x0e, 0 <LABEL1>
+.*: d800000e prfm plislckeep, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bee prfm #0x0e, \[sp, x15\]
-.*: f8be58ee prfm #0x0e, \[x7, w30, uxtw #3\]
-.*: f9800c6e prfm #0x0e, \[x3, #24\]
-.*: d800000f prfm #0x0f, 0 <LABEL1>
+.*: f8af6bee prfm plislckeep, \[sp, x15\]
+.*: f8be58ee prfm plislckeep, \[x7, w30, uxtw #3\]
+.*: f9800c6e prfm plislckeep, \[x3, #24\]
+.*: d800000f prfm plislcstrm, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bef prfm #0x0f, \[sp, x15\]
-.*: f8be58ef prfm #0x0f, \[x7, w30, uxtw #3\]
-.*: f9800c6f prfm #0x0f, \[x3, #24\]
+.*: f8af6bef prfm plislcstrm, \[sp, x15\]
+.*: f8be58ef prfm plislcstrm, \[x7, w30, uxtw #3\]
+.*: f9800c6f prfm plislcstrm, \[x3, #24\]
.*: d8000010 prfm pstl1keep, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
.*: f8af6bf0 prfm pstl1keep, \[sp, x15\]
@@ -320,16 +320,16 @@ Disassembly of section \.text:
.*: f8af6bf5 prfm pstl3strm, \[sp, x15\]
.*: f8be58f5 prfm pstl3strm, \[x7, w30, uxtw #3\]
.*: f9800c75 prfm pstl3strm, \[x3, #24\]
-.*: d8000016 prfm #0x16, 0 <LABEL1>
+.*: d8000016 prfm pstslckeep, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf6 prfm #0x16, \[sp, x15\]
-.*: f8be58f6 prfm #0x16, \[x7, w30, uxtw #3\]
-.*: f9800c76 prfm #0x16, \[x3, #24\]
-.*: d8000017 prfm #0x17, 0 <LABEL1>
+.*: f8af6bf6 prfm pstslckeep, \[sp, x15\]
+.*: f8be58f6 prfm pstslckeep, \[x7, w30, uxtw #3\]
+.*: f9800c76 prfm pstslckeep, \[x3, #24\]
+.*: d8000017 prfm pstslcstrm, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
-.*: f8af6bf7 prfm #0x17, \[sp, x15\]
-.*: f8be58f7 prfm #0x17, \[x7, w30, uxtw #3\]
-.*: f9800c77 prfm #0x17, \[x3, #24\]
+.*: f8af6bf7 prfm pstslcstrm, \[sp, x15\]
+.*: f8be58f7 prfm pstslcstrm, \[x7, w30, uxtw #3\]
+.*: f9800c77 prfm pstslcstrm, \[x3, #24\]
.*: d8000018 prfm #0x18, 0 <LABEL1>
.*: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
.*: f9800c78 prfm #0x18, \[x3, #24\]
@@ -360,17 +360,23 @@ Disassembly of section \.text:
.*: f9800c63 prfm pldl2strm, \[x3, #24\]
.*: f9800c64 prfm pldl3keep, \[x3, #24\]
.*: f9800c65 prfm pldl3strm, \[x3, #24\]
+.*: f9800c66 prfm pldslckeep, \[x3, #24\]
+.*: f9800c67 prfm pldslcstrm, \[x3, #24\]
.*: f9800c68 prfm plil1keep, \[x3, #24\]
.*: f9800c69 prfm plil1strm, \[x3, #24\]
.*: f9800c6a prfm plil2keep, \[x3, #24\]
.*: f9800c6b prfm plil2strm, \[x3, #24\]
.*: f9800c6c prfm plil3keep, \[x3, #24\]
.*: f9800c6d prfm plil3strm, \[x3, #24\]
+.*: f9800c6e prfm plislckeep, \[x3, #24\]
+.*: f9800c6f prfm plislcstrm, \[x3, #24\]
.*: f9800c70 prfm pstl1keep, \[x3, #24\]
.*: f9800c71 prfm pstl1strm, \[x3, #24\]
.*: f9800c72 prfm pstl2keep, \[x3, #24\]
.*: f9800c73 prfm pstl2strm, \[x3, #24\]
.*: f9800c74 prfm pstl3keep, \[x3, #24\]
.*: f9800c75 prfm pstl3strm, \[x3, #24\]
-.*: f8a04817 prfm #0x17, \[x0, w0, uxtw\]
+.*: f9800c76 prfm pstslckeep, \[x3, #24\]
+.*: f9800c77 prfm pstslcstrm, \[x3, #24\]
+.*: f8a04817 prfm pstslcstrm, \[x0, w0, uxtw\]
.*: f8a04818 rprfm pldkeep, x0, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/system.s b/gas/testsuite/gas/aarch64/system.s
index 48e7bfeb10398190ee26338c7e83f363ba4a4bd8..9457b392f785f89af7cbf7aa81c36de9de94ad80 100644
--- a/gas/testsuite/gas/aarch64/system.s
+++ b/gas/testsuite/gas/aarch64/system.s
@@ -87,7 +87,7 @@
//
.irp op, pld, pli, pst
- .irp l, l1, l2, l3
+ .irp l, l1, l2, l3, slc
.irp t, keep, strm
prfm \op\l\t, [x3, #24]
.endr
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5a0f0e9f52e31e8a0823e544122f4e65c2541570..80816d633661eb5a39e0da28c1cd5d4c87df308f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -575,24 +575,24 @@ const struct aarch64_name_value_pair aarch64_prfops[32] =
{ "pldl2strm", B(0, 2, 1) },
{ "pldl3keep", B(0, 3, 0) },
{ "pldl3strm", B(0, 3, 1) },
- { NULL, 0x06 },
- { NULL, 0x07 },
+ { "pldslckeep", B(0, 4, 0) },
+ { "pldslcstrm", B(0, 4, 1) },
{ "plil1keep", B(1, 1, 0) },
{ "plil1strm", B(1, 1, 1) },
{ "plil2keep", B(1, 2, 0) },
{ "plil2strm", B(1, 2, 1) },
{ "plil3keep", B(1, 3, 0) },
{ "plil3strm", B(1, 3, 1) },
- { NULL, 0x0e },
- { NULL, 0x0f },
+ { "plislckeep", B(1, 4, 0) },
+ { "plislcstrm", B(1, 4, 1) },
{ "pstl1keep", B(2, 1, 0) },
{ "pstl1strm", B(2, 1, 1) },
{ "pstl2keep", B(2, 2, 0) },
{ "pstl2strm", B(2, 2, 1) },
{ "pstl3keep", B(2, 3, 0) },
{ "pstl3strm", B(2, 3, 1) },
- { NULL, 0x16 },
- { NULL, 0x17 },
+ { "pstslckeep", B(2, 4, 0) },
+ { "pstslcstrm", B(2, 4, 1) },
{ NULL, 0x18 },
{ NULL, 0x19 },
{ NULL, 0x1a },
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension.
2023-11-16 11:26 [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Srinath Parvathaneni
@ 2023-11-16 11:28 ` Srinath Parvathaneni
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
2023-11-16 11:58 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Richard Earnshaw
2023-11-16 11:55 ` [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Richard Earnshaw
1 sibling, 2 replies; 11+ messages in thread
From: Srinath Parvathaneni @ 2023-11-16 11:28 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc
[-- Attachment #1: Type: text/plain, Size: 345 bytes --]
Hi,
This patch adds features to the Statistical Profiling Extension,
identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
are enabled by default from Armv9.4-A.
Also adds support for system register "pmsdsfr_el1".
Regression tested for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb17873.patch --]
[-- Type: text/plain, Size: 3747 bytes --]
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..2471b6b52c31183b0aef6f089fcc3ce22089ee98
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.8-a
+#source: armv8_9-a-sysregs.s
+#error_output: armv8_9-a-sysregs-bad.l
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..48c55680aa07618cd1f0c165435533fe4dd31e41
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
+.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
new file mode 100644
index 0000000000000000000000000000000000000000..d4cb769fdf63aaa89ac4c410982cd20ac12bbd4d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -0,0 +1,10 @@
+#as: -march=armv8.9-a
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d53c9a83 mrs x3, pmsdsfr_el1
+.*: d51c9a83 msr pmsdsfr_el1, x3
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
new file mode 100644
index 0000000000000000000000000000000000000000..4200d7ce60ed21822731a836214bb44aeeea57ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -0,0 +1,2 @@
+ mrs x3, PMSDSFR_EL1
+ msr PMSDSFR_EL1, x3
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6be2885c78fbd5213220d22ce3218c39bb03916f..881a4211eabfad2cc4442efc78eb37c06d26973d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -163,6 +163,12 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_CHK,
/* Guarded Control Stack. */
AARCH64_FEATURE_GCS,
+ /* SPE Call Return branch records. */
+ AARCH64_FEATURE_SPE_CRR,
+ /* SPE Filter by data source. */
+ AARCH64_FEATURE_SPE_FDS,
+ /* Additional SPE events. */
+ AARCH64_FEATURE_SPEv1p4,
/* SME2. */
AARCH64_FEATURE_SME2,
/* Translation Hardening Extension. */
@@ -224,7 +230,10 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \
| AARCH64_FEATBIT (X, MOPS) \
| AARCH64_FEATBIT (X, HBC))
-#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A))
+#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \
+ | AARCH64_FEATBIT (X, SPEv1p4) \
+ | AARCH64_FEATBIT (X, SPE_CRR) \
+ | AARCH64_FEATBIT (X, SPE_FDS))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 96bdadb0b0fe56f25ec2c210264900d6936db06b..aab2c7264cab0b4ca34ab8135194abd0126b7430 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -676,6 +676,7 @@
SYSREG ("pmscr_el1", CPENC (3,0,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el12", CPENC (3,5,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el2", CPENC (3,4,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
+ SYSREG ("pmsdsfr_el1", CPENC (3,4,9,10,4), F_ARCHEXT, AARCH64_FEATURE (SPE_FDS))
SYSREG ("pmselr_el0", CPENC (3,3,9,12,5), 0, AARCH64_NO_FEATURES)
SYSREG ("pmsevfr_el1", CPENC (3,0,9,9,5), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmsfcr_el1", CPENC (3,0,9,9,4), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension.
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
@ 2023-11-16 11:31 ` Srinath Parvathaneni
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
2023-11-16 12:04 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Richard Earnshaw
2023-11-16 11:58 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Richard Earnshaw
1 sibling, 2 replies; 11+ messages in thread
From: Srinath Parvathaneni @ 2023-11-16 11:31 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc
[-- Attachment #1: Type: text/plain, Size: 835 bytes --]
Hi,
This patch also adds support for:
1. FEAT_RASv2 feature and "ERXGSR_EL1" system register.
RASv2 feature is enabled by passing +rasv2 to -march (eg:
-march=armv8-a+rasv2).
2. FEAT_SCTLR2 and following system registers.
SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3.
3. FEAT_FGT2 and following system registers.
HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2
4. FEAT_PFAR and following system registers.
PFAR_EL1, PFAR_EL2 and PFAR_EL12.
FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default
enabled from Armv9.4-A architecture.
This patch also adds support for two read only system registers
id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from
Armv8-A Architecture.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb17874.patch --]
[-- Type: text/plain, Size: 13047 bytes --]
diff --git a/gas/NEWS b/gas/NEWS
index ddf48fca37bbc87b78a78d4162ba71e4391a3cff..9d0fb3b63d03b730ef8b33fea84d038aa0d3d15a 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
-*- text -*-
+* Add support for Reliability, Availability and Serviceability extension v2
+ (RASv2) for AArch64.
+
* Add support for 128-bit Atomic Instructions (LSE128) for AArch64.
* Add support for Guarded Control Stack (GCS) for AArch64.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 70c0ed652a551ada46755a3ce96a704d050a9b44..5646de781d4502c0aa434368f0603c11ee456966 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10292,6 +10292,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"chk", AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES},
{"gcs", AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES},
{"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES},
+ {"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 81c18181831a530f8596b8838a6b1751d5852305..cbf06bf3ec6d1680c74aad3a1a9364721ae7ca34 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -267,7 +267,8 @@ automatically cause those extensions to be disabled.
@tab Enable Translation Hardening extension.
@item @code{lse128} @tab Armv9.4-A @tab No
@tab Enable the 128-bit Atomic Instructions extension. This implies @code{lse}.
-
+@item @code{rasv2} @tab N/A @tab Armv9.4-A or later
+ @tab Enable the Reliability, Availability and Serviceability extension v2.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 48c55680aa07618cd1f0c165435533fe4dd31e41..63397bcb162747c9fe77ebcf6f0066c286c6c620 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -1,3 +1,26 @@
.*: Assembler messages:
.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
+.*: Error: selected processor does not support system register name 'erxgsr_el1'
+.*: Error: selected processor does not support system register name 'sctlr2_el1'
+.*: Error: selected processor does not support system register name 'sctlr2_el12'
+.*: Error: selected processor does not support system register name 'sctlr2_el2'
+.*: Error: selected processor does not support system register name 'sctlr2_el3'
+.*: Error: selected processor does not support system register name 'sctlr2_el1'
+.*: Error: selected processor does not support system register name 'sctlr2_el12'
+.*: Error: selected processor does not support system register name 'sctlr2_el2'
+.*: Error: selected processor does not support system register name 'sctlr2_el3'
+.*: Error: selected processor does not support system register name 'hdfgrtr2_el2'
+.*: Error: selected processor does not support system register name 'hdfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgrtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hdfgrtr2_el2'
+.*: Error: selected processor does not support system register name 'hdfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgrtr2_el2'
+.*: Error: selected processor does not support system register name 'hfgwtr2_el2'
+.*: Error: selected processor does not support system register name 'pfar_el1'
+.*: Error: selected processor does not support system register name 'pfar_el2'
+.*: Error: selected processor does not support system register name 'pfar_el12'
+.*: Error: selected processor does not support system register name 'pfar_el1'
+.*: Error: selected processor does not support system register name 'pfar_el2'
+.*: Error: selected processor does not support system register name 'pfar_el12'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index d4cb769fdf63aaa89ac4c410982cd20ac12bbd4d..3b66e2bc57c1be243737679e2b85758bfe2af871 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -8,3 +8,26 @@ Disassembly of section \.text:
0+ <.*>:
.*: d53c9a83 mrs x3, pmsdsfr_el1
.*: d51c9a83 msr pmsdsfr_el1, x3
+.*: d5385340 mrs x0, erxgsr_el1
+.*: d5181063 msr sctlr2_el1, x3
+.*: d51d1063 msr sctlr2_el12, x3
+.*: d51c1063 msr sctlr2_el2, x3
+.*: d51e1063 msr sctlr2_el3, x3
+.*: d5381063 mrs x3, sctlr2_el1
+.*: d53d1063 mrs x3, sctlr2_el12
+.*: d53c1063 mrs x3, sctlr2_el2
+.*: d53e1063 mrs x3, sctlr2_el3
+.*: d53c3103 mrs x3, hdfgrtr2_el2
+.*: d53c3123 mrs x3, hdfgwtr2_el2
+.*: d53c3143 mrs x3, hfgrtr2_el2
+.*: d53c3163 mrs x3, hfgwtr2_el2
+.*: d51c3103 msr hdfgrtr2_el2, x3
+.*: d51c3123 msr hdfgwtr2_el2, x3
+.*: d51c3143 msr hfgrtr2_el2, x3
+.*: d51c3163 msr hfgwtr2_el2, x3
+.*: d53860a0 mrs x0, pfar_el1
+.*: d53c60a0 mrs x0, pfar_el2
+.*: d53d60a0 mrs x0, pfar_el12
+.*: d51860a0 msr pfar_el1, x0
+.*: d51c60a0 msr pfar_el2, x0
+.*: d51d60a0 msr pfar_el12, x0
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 4200d7ce60ed21822731a836214bb44aeeea57ac..9ad0a532acc1bd8714f89b193d1b41f57ffb80d2 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -1,2 +1,29 @@
mrs x3, PMSDSFR_EL1
msr PMSDSFR_EL1, x3
+
+ mrs x0, ERXGSR_EL1
+
+ msr SCTLR2_EL1, x3
+ msr SCTLR2_EL12, x3
+ msr SCTLR2_EL2, x3
+ msr SCTLR2_EL3, x3
+ mrs x3, SCTLR2_EL1
+ mrs x3, SCTLR2_EL12
+ mrs x3, SCTLR2_EL2
+ mrs x3, SCTLR2_EL3
+
+ mrs x3, HDFGRTR2_EL2
+ mrs x3, HDFGWTR2_EL2
+ mrs x3, HFGRTR2_EL2
+ mrs x3, HFGWTR2_EL2
+ msr HDFGRTR2_EL2, x3
+ msr HDFGWTR2_EL2, x3
+ msr HFGRTR2_EL2, x3
+ msr HFGWTR2_EL2, x3
+
+ mrs x0, PFAR_EL1
+ mrs x0, PFAR_EL2
+ mrs x0, PFAR_EL12
+ msr PFAR_EL1, x0
+ msr PFAR_EL2, x0
+ msr PFAR_EL12, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index 097f27292739b810e7b6840d096e3fad9901f1cd..ac0a8621bfa88a21a2e0f7be69117357c9e16b06 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -7,10 +7,12 @@
Disassembly of section .text:
0+ <.*>:
- [0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1
- [0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
- [0-9a-f]+: d5385305 mrs x5, erridr_el1
- [0-9a-f]+: d5185327 msr errselr_el1, x7
+.*: d5380725 mrs x5, id_aa64mmfr1_el1
+.*: d5380747 mrs x7, id_aa64mmfr2_el1
+.*: d5380769 mrs x9, id_aa64mmfr3_el1
+.*: d538078b mrs x11, id_aa64mmfr4_el1
+ [0-9a-f]+: d5385305 mrs x5, erridr_el1
+ [0-9a-f]+: d5185327 msr errselr_el1, x7
[0-9a-f]+: d5385327 mrs x7, errselr_el1
[0-9a-f]+: d5385405 mrs x5, erxfr_el1
[0-9a-f]+: d5185425 msr erxctlr_el1, x5
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index 57eb08f33521076314260b68f3e322280d9ff93b..ae2bb145e72a0786078fe60b0082dd09a618ce4d 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -13,6 +13,8 @@
rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
+ rw_sys_reg sys_reg=id_aa64mmfr3_el1 xreg=x9 r=1 w=0
+ rw_sys_reg sys_reg=id_aa64mmfr4_el1 xreg=x11 r=1 w=0
/* RAS extension. */
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 881a4211eabfad2cc4442efc78eb37c06d26973d..03ef907cac1c574516f1e1cc4d0537b33c803986 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -175,6 +175,14 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_THE,
/* LSE128. */
AARCH64_FEATURE_LSE128,
+ /* ARMv8.9-A RAS Extensions. */
+ AARCH64_FEATURE_RASv2,
+ /* System Control Register2. */
+ AARCH64_FEATURE_SCTLR2,
+ /* Fine Grained Traps. */
+ AARCH64_FEATURE_FGT2,
+ /* Physical Fault Address. */
+ AARCH64_FEATURE_PFAR,
AARCH64_NUM_FEATURES
};
@@ -233,7 +241,11 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \
| AARCH64_FEATBIT (X, SPEv1p4) \
| AARCH64_FEATBIT (X, SPE_CRR) \
- | AARCH64_FEATBIT (X, SPE_FDS))
+ | AARCH64_FEATBIT (X, SPE_FDS) \
+ | AARCH64_FEATBIT (X, RASv2) \
+ | AARCH64_FEATBIT (X, SCTLR2) \
+ | AARCH64_FEATBIT (X, FGT2) \
+ | AARCH64_FEATBIT (X, PFAR))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index aab2c7264cab0b4ca34ab8135194abd0126b7430..b51c5aa14598abe8628d6a1363b43d6604dc8fda 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -400,6 +400,7 @@
SYSREG ("erxaddr_el1", CPENC (3,0,5,4,3), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("erxctlr_el1", CPENC (3,0,5,4,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("erxfr_el1", CPENC (3,0,5,4,0), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (RAS))
+ SYSREG ("erxgsr_el1", CPENC (3,0,5,3,2), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (RASv2))
SYSREG ("erxmisc0_el1", CPENC (3,0,5,5,0), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("erxmisc1_el1", CPENC (3,0,5,5,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("erxmisc2_el1", CPENC (3,0,5,5,2), F_ARCHEXT, AARCH64_FEATURE (RAS))
@@ -438,10 +439,14 @@
SYSREG ("hcr_el2", CPENC (3,4,1,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("hcrx_el2", CPENC (3,4,1,2,2), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
SYSREG ("hdfgrtr_el2", CPENC (3,4,3,1,4), F_ARCHEXT, AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgrtr2_el2", CPENC (3,4,3,1,0), F_ARCHEXT, AARCH64_FEATURE (FGT2))
SYSREG ("hdfgwtr_el2", CPENC (3,4,3,1,5), F_ARCHEXT, AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgwtr2_el2", CPENC (3,4,3,1,1), F_ARCHEXT, AARCH64_FEATURE (FGT2))
SYSREG ("hfgitr_el2", CPENC (3,4,1,1,6), F_ARCHEXT, AARCH64_FEATURE (V8_6A))
SYSREG ("hfgrtr_el2", CPENC (3,4,1,1,4), F_ARCHEXT, AARCH64_FEATURE (V8_6A))
+ SYSREG ("hfgrtr2_el2", CPENC (3,4,3,1,2), F_ARCHEXT, AARCH64_FEATURE (FGT2))
SYSREG ("hfgwtr_el2", CPENC (3,4,1,1,5), F_ARCHEXT, AARCH64_FEATURE (V8_6A))
+ SYSREG ("hfgwtr2_el2", CPENC (3,4,3,1,3), F_ARCHEXT, AARCH64_FEATURE (FGT2))
SYSREG ("hpfar_el2", CPENC (3,4,6,0,4), 0, AARCH64_NO_FEATURES)
SYSREG ("hstr_el2", CPENC (3,4,1,1,3), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_ap0r0_el1", CPENC (3,0,12,8,4), 0, AARCH64_NO_FEATURES)
@@ -515,6 +520,8 @@
SYSREG ("id_aa64mmfr0_el1", CPENC (3,0,0,7,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr1_el1", CPENC (3,0,0,7,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr2_el1", CPENC (3,0,0,7,2), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("id_aa64mmfr3_el1", CPENC (3,0,0,7,3), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("id_aa64mmfr4_el1", CPENC (3,0,0,7,4), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64pfr0_el1", CPENC (3,0,0,4,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64pfr1_el1", CPENC (3,0,0,4,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64smfr0_el1", CPENC (3,0,0,4,5), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (SME))
@@ -595,6 +602,9 @@
SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN))
SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES)
+ SYSREG ("pfar_el1", CPENC (3,0,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR))
+ SYSREG ("pfar_el12", CPENC (3,5,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR))
+ SYSREG ("pfar_el2", CPENC (3,4,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR))
SYSREG ("pmbidr_el1", CPENC (3,0,9,10,7), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmblimitr_el1", CPENC (3,0,9,10,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmbptr_el1", CPENC (3,0,9,10,1), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
@@ -774,6 +784,10 @@
SYSREG ("sctlr_el12", CPENC (3,5,1,0,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("sctlr_el2", CPENC (3,4,1,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("sctlr_el3", CPENC (3,6,1,0,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("sctlr2_el1", CPENC (3,0,1,0,3), F_ARCHEXT, AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el12", CPENC (3,5,1,0,3), F_ARCHEXT, AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el2", CPENC (3,4,1,0,3), F_ARCHEXT, AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el3", CPENC (3,6,1,0,3), F_ARCHEXT, AARCH64_FEATURE (SCTLR2))
SYSREG ("scxtnum_el0", CPENC (3,3,13,0,7), F_ARCHEXT, AARCH64_FEATURE (SCXTNUM))
SYSREG ("scxtnum_el1", CPENC (3,0,13,0,7), F_ARCHEXT, AARCH64_FEATURE (SCXTNUM))
SYSREG ("scxtnum_el12", CPENC (3,5,13,0,7), F_ARCHEXT, AARCH64_FEATURE (SCXTNUM))
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions.
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
@ 2023-11-16 11:38 ` Srinath Parvathaneni
2023-11-16 11:39 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Srinath Parvathaneni
2023-11-16 14:13 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Richard Earnshaw
2023-11-16 12:04 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Richard Earnshaw
1 sibling, 2 replies; 11+ messages in thread
From: Srinath Parvathaneni @ 2023-11-16 11:38 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc
[-- Attachment #1: Type: text/plain, Size: 254 bytes --]
HI,
This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
Regression tested for aarch64-none-elf target and found
no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb18001.patch --]
[-- Type: text/plain, Size: 3715 bytes --]
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 63397bcb162747c9fe77ebcf6f0066c286c6c620..1b67843a4dd1744ef1ab2a7f9af3013922b7dbec 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -24,3 +24,6 @@
.*: Error: selected processor does not support system register name 'pfar_el1'
.*: Error: selected processor does not support system register name 'pfar_el2'
.*: Error: selected processor does not support system register name 'pfar_el12'
+.*: Error: selected processor does not support system register name 's1e1a'
+.*: Error: selected processor does not support system register name 's1e2a'
+.*: Error: selected processor does not support system register name 's1e3a'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index 3b66e2bc57c1be243737679e2b85758bfe2af871..18376bb5ac19d821c8fcef2dcb272cdc2b9c5e52 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -31,3 +31,6 @@ Disassembly of section \.text:
.*: d51860a0 msr pfar_el1, x0
.*: d51c60a0 msr pfar_el2, x0
.*: d51d60a0 msr pfar_el12, x0
+.*: d5087941 at s1e1a, x1
+.*: d50c7943 at s1e2a, x3
+.*: d50e7945 at s1e3a, x5
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 9ad0a532acc1bd8714f89b193d1b41f57ffb80d2..4e494a965f6a9196395b2da1f8fb7da3e42faa7c 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -27,3 +27,8 @@
msr PFAR_EL1, x0
msr PFAR_EL2, x0
msr PFAR_EL12, x0
+
+ /* AT. */
+ at s1e1a, x1
+ at s1e2a, x3
+ at s1e3a, x5
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 03ef907cac1c574516f1e1cc4d0537b33c803986..792d6a4f4a7603487899f175c2b49763cbb47697 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FGT2,
/* Physical Fault Address. */
AARCH64_FEATURE_PFAR,
+ /* Address Translate Stage 1. */
+ AARCH64_FEATURE_ATS1A,
AARCH64_NUM_FEATURES
};
@@ -245,7 +247,8 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, RASv2) \
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
- | AARCH64_FEATBIT (X, PFAR))
+ | AARCH64_FEATBIT (X, PFAR) \
+ | AARCH64_FEATBIT (X, ATS1A))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 80816d633661eb5a39e0da28c1cd5d4c87df308f..126a4aa0a4cd559a4697eab678cca160660d615a 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
{ "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
+ { "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};
@@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, THE))
return true;
+ if ((reg_value == CPENS (0, C7, C9, 2)
+ || reg_value == CPENS (4, C7, C9, 2)
+ || reg_value == CPENS (6, C7, C9, 2))
+ && AARCH64_CPU_HAS_FEATURE (features, ATS1A))
+ return true;
+
return false;
}
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements.
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
@ 2023-11-16 11:39 ` Srinath Parvathaneni
2023-11-16 14:16 ` Richard Earnshaw
2023-11-28 14:01 ` Jan Beulich
2023-11-16 14:13 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Richard Earnshaw
1 sibling, 2 replies; 11+ messages in thread
From: Srinath Parvathaneni @ 2023-11-16 11:39 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, nickc
[-- Attachment #1: Type: text/plain, Size: 564 bytes --]
Hi,
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)
These features are available by default from Armv9.4-A architecture.
Regression tested for aarch64-none-elf target and found
no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb18002.patch --]
[-- Type: text/plain, Size: 14614 bytes --]
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 1b67843a4dd1744ef1ab2a7f9af3013922b7dbec..71ec06e3cb47ae629e9fd023268c9e5b0c55cda6 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -27,3 +27,53 @@
.*: Error: selected processor does not support system register name 's1e1a'
.*: Error: selected processor does not support system register name 's1e2a'
.*: Error: selected processor does not support system register name 's1e3a'
+.*: Error: selected processor does not support system register name 'amair2_el1'
+.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el2'
+.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'mair2_el1'
+.*: Error: selected processor does not support system register name 'mair2_el12'
+.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el3'
+.*: Error: selected processor does not support system register name 'amair2_el1'
+.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el2'
+.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'mair2_el1'
+.*: Error: selected processor does not support system register name 'mair2_el12'
+.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el3'
+.*: Error: selected processor does not support system register name 'pir_el1'
+.*: Error: selected processor does not support system register name 'pir_el12'
+.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el3'
+.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el12'
+.*: Error: selected processor does not support system register name 'pire0_el2'
+.*: Error: selected processor does not support system register name 'pir_el1'
+.*: Error: selected processor does not support system register name 'pir_el12'
+.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el3'
+.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el12'
+.*: Error: selected processor does not support system register name 'pire0_el2'
+.*: Error: selected processor does not support system register name 's2pir_el2'
+.*: Error: selected processor does not support system register name 's2pir_el2'
+.*: Error: selected processor does not support system register name 'por_el0'
+.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el12'
+.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el3'
+.*: Error: selected processor does not support system register name 'por_el0'
+.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el12'
+.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el3'
+.*: Error: selected processor does not support system register name 's2por_el1'
+.*: Error: selected processor does not support system register name 's2por_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el2'
+.*: Error: selected processor does not support system register name 'tcr2_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el2'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index 18376bb5ac19d821c8fcef2dcb272cdc2b9c5e52..ea4cc867ec3ea9595f7076e49d5d48c7794921dd 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -34,3 +34,53 @@ Disassembly of section \.text:
.*: d5087941 at s1e1a, x1
.*: d50c7943 at s1e2a, x3
.*: d50e7945 at s1e3a, x5
+.*: d538a320 mrs x0, amair2_el1
+.*: d53da320 mrs x0, amair2_el12
+.*: d53ca320 mrs x0, amair2_el2
+.*: d53ea320 mrs x0, amair2_el3
+.*: d538a220 mrs x0, mair2_el1
+.*: d53da220 mrs x0, mair2_el12
+.*: d53ca120 mrs x0, mair2_el2
+.*: d53ea120 mrs x0, mair2_el3
+.*: d518a320 msr amair2_el1, x0
+.*: d51da320 msr amair2_el12, x0
+.*: d51ca320 msr amair2_el2, x0
+.*: d51ea320 msr amair2_el3, x0
+.*: d518a220 msr mair2_el1, x0
+.*: d51da220 msr mair2_el12, x0
+.*: d51ca120 msr mair2_el2, x0
+.*: d51ea120 msr mair2_el3, x0
+.*: d538a260 mrs x0, pir_el1
+.*: d53da260 mrs x0, pir_el12
+.*: d53ca260 mrs x0, pir_el2
+.*: d53ea260 mrs x0, pir_el3
+.*: d538a240 mrs x0, pire0_el1
+.*: d53da240 mrs x0, pire0_el12
+.*: d53ca240 mrs x0, pire0_el2
+.*: d518a260 msr pir_el1, x0
+.*: d51da260 msr pir_el12, x0
+.*: d51ca260 msr pir_el2, x0
+.*: d51ea260 msr pir_el3, x0
+.*: d518a240 msr pire0_el1, x0
+.*: d51da240 msr pire0_el12, x0
+.*: d51ca240 msr pire0_el2, x0
+.*: d53ca2a0 mrs x0, s2pir_el2
+.*: d51ca2a0 msr s2pir_el2, x0
+.*: d53ba280 mrs x0, por_el0
+.*: d538a280 mrs x0, por_el1
+.*: d53da280 mrs x0, por_el12
+.*: d53ca280 mrs x0, por_el2
+.*: d53ea280 mrs x0, por_el3
+.*: d51ba280 msr por_el0, x0
+.*: d518a280 msr por_el1, x0
+.*: d51da280 msr por_el12, x0
+.*: d51ca280 msr por_el2, x0
+.*: d51ea280 msr por_el3, x0
+.*: d538a2a0 mrs x0, s2por_el1
+.*: d518a2a0 msr s2por_el1, x0
+.*: d5382060 mrs x0, tcr2_el1
+.*: d53d2060 mrs x0, tcr2_el12
+.*: d53c2060 mrs x0, tcr2_el2
+.*: d5182060 msr tcr2_el1, x0
+.*: d51d2060 msr tcr2_el12, x0
+.*: d51c2060 msr tcr2_el2, x0
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 4e494a965f6a9196395b2da1f8fb7da3e42faa7c..2768c2686903629d88ca36ef1404b4ea0a0c477a 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -32,3 +32,69 @@
at s1e1a, x1
at s1e2a, x3
at s1e3a, x5
+
+ /* FEAT_AIE. */
+ mrs x0, amair2_el1
+ mrs x0, amair2_el12
+ mrs x0, amair2_el2
+ mrs x0, amair2_el3
+ mrs x0, mair2_el1
+ mrs x0, mair2_el12
+ mrs x0, mair2_el2
+ mrs x0, mair2_el3
+
+ msr amair2_el1, x0
+ msr amair2_el12, x0
+ msr amair2_el2, x0
+ msr amair2_el3, x0
+ msr mair2_el1, x0
+ msr mair2_el12, x0
+ msr mair2_el2, x0
+ msr mair2_el3, x0
+
+ /* FEAT_S1PIE. */
+ mrs x0, pir_el1
+ mrs x0, pir_el12
+ mrs x0, pir_el2
+ mrs x0, pir_el3
+ mrs x0, pire0_el1
+ mrs x0, pire0_el12
+ mrs x0, pire0_el2
+
+ msr pir_el1, x0
+ msr pir_el12, x0
+ msr pir_el2, x0
+ msr pir_el3, x0
+ msr pire0_el1, x0
+ msr pire0_el12, x0
+ msr pire0_el2, x0
+
+ /* FEAT_S2PIE. */
+ mrs x0, s2pir_el2
+ msr s2pir_el2, x0
+
+ /* FEAT_S1POE. */
+ mrs x0, por_el0
+ mrs x0, por_el1
+ mrs x0, por_el12
+ mrs x0, por_el2
+ mrs x0, por_el3
+
+ msr por_el0, x0
+ msr por_el1, x0
+ msr por_el12, x0
+ msr por_el2, x0
+ msr por_el3, x0
+
+ /* FEAT_S21POE. */
+ mrs x0, s2por_el1
+ msr s2por_el1, x0
+
+ /* FEAT_TCR2. */
+ mrs x0, tcr2_el1
+ mrs x0, tcr2_el12
+ mrs x0, tcr2_el2
+
+ msr tcr2_el1, x0
+ msr tcr2_el12, x0
+ msr tcr2_el2, x0
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 792d6a4f4a7603487899f175c2b49763cbb47697..df0864009fe145028aef9c8d5e5e76badd616f1b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -185,6 +185,18 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PFAR,
/* Address Translate Stage 1. */
AARCH64_FEATURE_ATS1A,
+ /* Memory Attribute Index Enhancement. */
+ AARCH64_FEATURE_AIE,
+ /* Stage 1 Permission Indirection Extension. */
+ AARCH64_FEATURE_S1PIE,
+ /* Stage 2 Permission Indirection Extension. */
+ AARCH64_FEATURE_S2PIE,
+ /* Stage 1 Permission Overlay Extension. */
+ AARCH64_FEATURE_S1POE,
+ /* Stage 2 Permission Overlay Extension. */
+ AARCH64_FEATURE_S2POE,
+ /* Extension to Translation Control Registers. */
+ AARCH64_FEATURE_TCR2,
AARCH64_NUM_FEATURES
};
@@ -248,7 +260,13 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
| AARCH64_FEATBIT (X, PFAR) \
- | AARCH64_FEATBIT (X, ATS1A))
+ | AARCH64_FEATBIT (X, ATS1A) \
+ | AARCH64_FEATBIT (X, AIE) \
+ | AARCH64_FEATBIT (X, S1PIE) \
+ | AARCH64_FEATBIT (X, S2PIE) \
+ | AARCH64_FEATBIT (X, S1POE) \
+ | AARCH64_FEATBIT (X, S2POE) \
+ | AARCH64_FEATBIT (X, TCR2))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index b51c5aa14598abe8628d6a1363b43d6604dc8fda..0f647efca7e46a8554ac5c850fb315860bbede33 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -54,6 +54,10 @@
SYSREG ("amair_el12", CPENC (3,5,10,3,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("amair_el2", CPENC (3,4,10,3,0), 0, AARCH64_NO_FEATURES)
SYSREG ("amair_el3", CPENC (3,6,10,3,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("amair2_el1", CPENC (3,0,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el12", CPENC (3,5,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el2", CPENC (3,4,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el3", CPENC (3,6,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
SYSREG ("amcfgr_el0", CPENC (3,3,13,2,1), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("amcg1idr_el0", CPENC (3,3,13,2,6), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_6A))
SYSREG ("amcgcr_el0", CPENC (3,3,13,2,2), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
@@ -556,6 +560,10 @@
SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
SYSREG ("mdccint_el1", CPENC (2,0,0,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mdccsr_el0", CPENC (2,3,0,1,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("mdcr_el2", CPENC (3,4,1,1,1), 0, AARCH64_NO_FEATURES)
@@ -600,6 +608,13 @@
SYSREG ("oseccr_el1", CPENC (2,0,0,6,2), 0, AARCH64_NO_FEATURES)
SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("pir_el1", CPENC (3,0,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el12", CPENC (3,5,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el2", CPENC (3,4,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el3", CPENC (3,6,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el1", CPENC (3,0,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el12", CPENC (3,5,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el2", CPENC (3,4,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN))
SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES)
SYSREG ("pfar_el1", CPENC (3,0,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR))
@@ -699,6 +714,11 @@
SYSREG ("pmuserenr_el0", CPENC (3,3,9,14,0), 0, AARCH64_NO_FEATURES)
SYSREG ("pmxevcntr_el0", CPENC (3,3,9,13,2), 0, AARCH64_NO_FEATURES)
SYSREG ("pmxevtyper_el0", CPENC (3,3,9,13,1), 0, AARCH64_NO_FEATURES)
+ SYSREG ("por_el0", CPENC (3,3,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el1", CPENC (3,0,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el12", CPENC (3,5,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el2", CPENC (3,4,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el3", CPENC (3,6,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
SYSREG ("prbar10_el1", CPENC (3,0,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prbar10_el2", CPENC (3,4,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prbar11_el1", CPENC (3,0,6,13,4), F_ARCHEXT, AARCH64_FEATURE (V8R))
@@ -818,11 +838,16 @@
SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES)
SYSREG ("ssbs", CPENC (3,3,4,2,6), F_ARCHEXT, AARCH64_FEATURE (SSBS))
SYSREG ("svcr", CPENC (3,3,4,2,2), F_ARCHEXT, AARCH64_FEATURE (SME))
+ SYSREG ("s2pir_el2", CPENC (3,4,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2PIE))
+ SYSREG ("s2por_el1", CPENC (3,0,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2POE))
SYSREG ("tco", CPENC (3,3,4,2,7), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tcr_el12", CPENC (3,5,2,0,2), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("tcr_el2", CPENC (3,4,2,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tcr_el3", CPENC (3,6,2,0,2), 0, AARCH64_NO_FEATURES)
+ SYSREG ("tcr2_el1", CPENC (3,0,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el12", CPENC (3,5,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el2", CPENC (3,4,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
SYSREG ("teecr32_el1", CPENC (2,2,0,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("teehbr32_el1", CPENC (2,2,1,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("tfsr_el1", CPENC (3,0,5,6,0), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction.
2023-11-16 11:26 [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Srinath Parvathaneni
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
@ 2023-11-16 11:55 ` Richard Earnshaw
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw @ 2023-11-16 11:55 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: Richard Earnshaw, nickc
On 16/11/2023 11:26, Srinath Parvathaneni wrote:
> Hi,
>
> This patch adds support for FEAT_PRFMSLC feature which enables
> SLC target for PRFM instructions.
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
OK.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension.
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
@ 2023-11-16 11:58 ` Richard Earnshaw
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw @ 2023-11-16 11:58 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: Richard Earnshaw, nickc
On 16/11/2023 11:28, Srinath Parvathaneni wrote:
> Hi,
>
> This patch adds features to the Statistical Profiling Extension,
> identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
> are enabled by default from Armv9.4-A.
>
> Also adds support for system register "pmsdsfr_el1".
>
> Regression tested for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
OK.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension.
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
@ 2023-11-16 12:04 ` Richard Earnshaw
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw @ 2023-11-16 12:04 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: Richard Earnshaw, nickc
On 16/11/2023 11:31, Srinath Parvathaneni wrote:
> Hi,
>
> This patch also adds support for:
> 1. FEAT_RASv2 feature and "ERXGSR_EL1" system register.
> RASv2 feature is enabled by passing +rasv2 to -march (eg:
> -march=armv8-a+rasv2).
>
> 2. FEAT_SCTLR2 and following system registers.
> SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3.
>
> 3. FEAT_FGT2 and following system registers.
> HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2
>
> 4. FEAT_PFAR and following system registers.
> PFAR_EL1, PFAR_EL2 and PFAR_EL12.
>
> FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default
> enabled from Armv9.4-A architecture.
>
> This patch also adds support for two read only system registers
> id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from
> Armv8-A Architecture.
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
OK.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions.
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
2023-11-16 11:39 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Srinath Parvathaneni
@ 2023-11-16 14:13 ` Richard Earnshaw
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw @ 2023-11-16 14:13 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: Richard Earnshaw, nickc
On 16/11/2023 11:38, Srinath Parvathaneni wrote:
> HI,
>
> This patch adds 3 new AT system instructions through FEAT_ATS1A
> feature, which are available by default from Armv9.4-A architecture.
>
> Regression tested for aarch64-none-elf target and found
> no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
@@ -245,7 +247,8 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, RASv2) \
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
- | AARCH64_FEATBIT (X, PFAR))
+ | AARCH64_FEATBIT (X, PFAR) \
+ | AARCH64_FEATBIT (X, ATS1A))
If you put the final closing parenthesis on the following line, then the
next update will cause less churn in the diffs.
Otherwise OK.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements.
2023-11-16 11:39 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Srinath Parvathaneni
@ 2023-11-16 14:16 ` Richard Earnshaw
2023-11-28 14:01 ` Jan Beulich
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw @ 2023-11-16 14:16 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: Richard Earnshaw, nickc
On 16/11/2023 11:39, Srinath Parvathaneni wrote:
> Hi,
>
> This patch adds the permission model enhancement and memory
> attribute index enhancement features and their corresponding
> system registers in AArch64 assembler.
> Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
> Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
> Memory Attribute Index Enhancement (FEAT_AIE)
> Extension to Translation Control Registers (FEAT_TCR2)
>
> These features are available by default from Armv9.4-A architecture.
>
> Regression tested for aarch64-none-elf target and found
> no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
@@ -248,7 +260,13 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
| AARCH64_FEATBIT (X, PFAR) \
- | AARCH64_FEATBIT (X, ATS1A))
+ | AARCH64_FEATBIT (X, ATS1A) \
+ | AARCH64_FEATBIT (X, AIE) \
+ | AARCH64_FEATBIT (X, S1PIE) \
+ | AARCH64_FEATBIT (X, S2PIE) \
+ | AARCH64_FEATBIT (X, S1POE) \
+ | AARCH64_FEATBIT (X, S2POE) \
+ | AARCH64_FEATBIT (X, TCR2))
Hmm, it's this one where the change I suggested on patch 4 really needs
doing so that next time we win.
Otherwise OK.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements.
2023-11-16 11:39 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Srinath Parvathaneni
2023-11-16 14:16 ` Richard Earnshaw
@ 2023-11-28 14:01 ` Jan Beulich
1 sibling, 0 replies; 11+ messages in thread
From: Jan Beulich @ 2023-11-28 14:01 UTC (permalink / raw)
To: Srinath Parvathaneni; +Cc: Richard Earnshaw, nickc, binutils
On 16.11.2023 12:39, Srinath Parvathaneni wrote:
> This patch adds the permission model enhancement and memory
> attribute index enhancement features and their corresponding
> system registers in AArch64 assembler.
> Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
> Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
> Memory Attribute Index Enhancement (FEAT_AIE)
> Extension to Translation Control Registers (FEAT_TCR2)
With the public documentation not (yet) mentioning these registers
(and you also not providing references to, perhaps, incremental
documentation which is going to be folded into the ARM), it's
pretty hard to judge whether what might look like a typo actually
is one. In particular in
@@ -556,6 +560,10 @@
SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
the EL2 and EL3 values using 1s where the EL1 and EL12 values use 2s
looks somewhat suspicious. No similar inconsistency exists for AMAIR2,
for example.
Jan
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-11-28 14:01 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-16 11:26 [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Srinath Parvathaneni
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
2023-11-16 11:39 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Srinath Parvathaneni
2023-11-16 14:16 ` Richard Earnshaw
2023-11-28 14:01 ` Jan Beulich
2023-11-16 14:13 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Richard Earnshaw
2023-11-16 12:04 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Richard Earnshaw
2023-11-16 11:58 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Richard Earnshaw
2023-11-16 11:55 ` [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Richard Earnshaw
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