Re: [PATCH] x86: Add Evw to emit w suffix for several instrctions for word ptr

[Jan Beulich <jbeulich@suse.com>]

On 31.05.2023 07:48, Jiang, Haochen wrote:
>>>> Maybe I got some wrong understanding on that. It comes from the
>>>> current testcase.
>>>> Trying to clarify that on disassembler.
>>>>
>>>> Let's take lldt as example. Will 0f00d2 emit eax register or ax register for
>> lldt?
>>>
>>> One thing to add the current behavior for disassembler or trunk is to
>>> emit ax register. Which I mean always is to as always with other instructions.
>>
>> I'm afraid I don't really get what you concern is. Yes, ...
> 
> I mean, for bytecode 0f00d2, should it emit 'lldt %ax' or 'lldt %eax'?

The former in 16-bit code, the latter elsewhere.

> Currently, in the testcase, it emits 'lldt %ax'. I suppose it actually fits documentation
> and we should not change it.

I think we should change it. Expressing operand size by proper GPR
selection is better than emitting (bogus imo) prefixes. Plus, as
said, before, please see the (in principle similar) move to/from
SREG insn handling.

> BTW, I read SDM today again, for SLDT/STR, they have the exact explanation for
> handling of r32/r64.
> 
> For STR, we have:
> "When the destination operand is a 32-bit register, ..."
> "In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits.
> In register stores, the 2-byte TR is zero extended if stored to a 64-bit register."
> 
> For SLDT, we have:
> "Outside IA-32e mode, when the destination operand is a 32-bit register,..."
> "In compatibility mode, when the destination operand is a 32-bit register,..."
> "In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
> registers (R8-R15). "
> 
> But for LLDT/LTR/VERW/VERR, things are different. The operands at least will be fixed at 16 bits
> in 64-bit mode.
> For LLDT, we have:
> "The operand-size attribute has no effect on this instruction.
> The LLDT instruction is provided for use in operating-system software; it should not be used
> in application programs. This instruction can only be executed in protected mode or 64-bit mode.
> In 64-bit mode, the operand size is fixed at 16 bits."
> 
> For LTR, we have:
> "The operand-size attribute has no effect on this instruction.
> In 64-bit mode, the operand size is still fixed at 16 bits."
> 
> For VERR/VERW, we have:
> "This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size
> is fixed at 16 bits."
> 
> Therefore, I suppose for VERR/VERW, the 32/64 bit register should never be allowed under any
> circumstances. For LLDT/LTR, in 64-bit mode, it should also the same conclusion. In protected mode
> and compatibility mode, it is questionable. The current implementation of assembler might need a
> fix.

Once again, please compare to other insns where we handle things properly.
Moves to/from SREG, as mentioned above, and things like PEXTRW/PINSRW. The
way the SDM puts things isn't always best; the main goal ought to be
consistency within the disassembler (and, just that it's not relevant here,
the assembler as well, of course).

Jan