From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>,
"Zhang, Jun" <jun.zhang@intel.com>
Subject: Re: [PATCH v2] Support Intel FRED LKGS
Date: Fri, 26 May 2023 09:00:09 +0200 [thread overview]
Message-ID: <a74e51c4-686b-4cfa-6616-5a3a823164b9@suse.com> (raw)
In-Reply-To: <SA1PR11MB59460753C0916773CB08C2F0EC479@SA1PR11MB5946.namprd11.prod.outlook.com>
On 26.05.2023 08:50, Jiang, Haochen wrote:
>
>>> I just take a look at the whole thing.
>>>
>>> From my perspective, if we are going to use the same pattern like SLDT
>>> and STR. Does that mean for the instruction below:
>>>
>>> lldt %ax
>>>
>>> We will need to add a 66 prefix for gas to make it happen or it will drop
>> to %eax?
>>>
>>> It will change the current assembler behavior. Is my understanding correct?
>>
>> No. The assembler was changed already. The disassembler simply wants to
>> follow suit. IOW the assembler already avoids emitting any unnecessary
>> prefixes. The disassembler, otoh, should correctly represent redundant
>> prefixes (and preferably not as raw ones, e.g. not "data16" but a 16-bit sized
>> register or an insn suffix for AT&T memory operands).
>
> So for all the registers, is the ideal case that we should not emit suffixes since the
> register will always be 16 bit?
The _part of the register that's used_ is always 16 bits. That doesn't mean
that's what we need to print. See e.g. pextrw/pinsrw. Imo GPRs here (like
elsewhere) should be printed according to the present prefixes: 16-bit when
a data size prefix is present, 32-bit when no size prefix is present, and
64-bit when REX.W is present. (Obviously adjusted when dealing with 16-bit
code.) This then eliminates the need for any insn suffix; that'll be needed
only for suffix-always mode, and specifically not for memory operands (which
are always 16-bit) outside of suffix-always mode. If this isn't what Sv + D
do, then it probably needs adjusting.
Jan
> If we are using D, I suppose we will emit suffixes under the current scenario.
>
> Haochen
>
>>
>> Jan
next prev parent reply other threads:[~2023-05-26 7:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-22 6:07 Zhang, Jun
2023-05-22 9:11 ` Jan Beulich
2023-05-24 6:36 ` Jiang, Haochen
2023-05-25 7:57 ` Jiang, Haochen
2023-05-25 8:42 ` Jan Beulich
2023-05-26 6:50 ` Jiang, Haochen
2023-05-26 7:00 ` Jan Beulich [this message]
2023-05-26 8:26 ` [PATCH] x86: Add Evw to emit w suffix for several instrctions for word ptr Haochen Jiang
2023-05-26 8:46 ` Jan Beulich
2023-05-26 8:54 ` Jiang, Haochen
2023-05-26 10:52 ` Jan Beulich
2023-05-29 2:01 ` Jiang, Haochen
2023-05-29 2:08 ` Jiang, Haochen
2023-05-30 8:09 ` Jan Beulich
2023-05-31 5:48 ` Jiang, Haochen
2023-05-31 8:43 ` Jan Beulich
2023-06-01 2:14 ` H.J. Lu
-- strict thread matches above, loose matches on Subject: below --
2023-05-22 6:00 [PATCH v2] Support Intel FRED LKGS Zhang, Jun
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