From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 1/2] RISC-V: Improve "bits undefined" diagnostics
Date: Sat, 9 Jul 2022 12:50:57 +0900 [thread overview]
Message-ID: <67e288adfa4ac6cd90215d7203eca56056f01bbf.1657338656.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1657338656.git.research_trasio@irq.a4lg.com>
This commit improves internal error message
"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"
to display actual unused bits (excluding non-instruction bits).
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Exclude non-
instruction bits from displaying internal diagnostics.
Change error message slightly.
---
gas/config/tc-riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a0e8456a0d1..8a961c05d95 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1265,8 +1265,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
if (used_bits != required_bits)
{
as_bad (_("internal: bad RISC-V opcode "
- "(bits 0x%lx undefined): %s %s"),
- ~(unsigned long)(used_bits & required_bits),
+ "(bits 0x%lx undefined or invalid): %s %s"),
+ (unsigned long)(used_bits ^ required_bits),
opc->name, opc->args);
return false;
}
--
2.34.1
next prev parent reply other threads:[~2022-07-09 3:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 3:50 [PATCH 0/2] " Tsukasa OI
2022-07-09 3:50 ` Tsukasa OI [this message]
2022-07-09 3:50 ` [PATCH 2/2] RISC-V: Fix required bits on certain environments Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 0/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-06 8:22 ` Jan Beulich
2022-10-06 9:52 ` Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06 8:26 ` Jan Beulich
2022-10-06 8:34 ` Tsukasa OI
2022-10-06 8:43 ` Jan Beulich
2022-10-06 9:56 ` [PATCH v3 0/2] " Tsukasa OI
2022-10-06 9:56 ` [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-14 1:32 ` Nelson Chu
2022-10-14 7:07 ` Jan Beulich
2022-10-16 13:32 ` Tsukasa OI
2022-10-28 9:41 ` Nelson Chu
2022-10-06 9:56 ` [PATCH v3 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
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