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From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics
Date: Thu, 6 Oct 2022 10:43:36 +0200	[thread overview]
Message-ID: <cd0ab393-8c36-a1aa-5fe1-46875c7b6a55@suse.com> (raw)
In-Reply-To: <65f01021-9da7-a895-3cfb-95b959e930c7@irq.a4lg.com>

On 06.10.2022 10:34, Tsukasa OI wrote:
> On 2022/10/06 17:26, Jan Beulich wrote:
>> On 06.10.2022 06:40, Tsukasa OI via Binutils wrote:
>>> --- a/gas/config/tc-riscv.c
>>> +++ b/gas/config/tc-riscv.c
>>> @@ -1312,8 +1312,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>>>    if (used_bits != required_bits)
>>>      {
>>>        as_bad (_("internal: bad RISC-V opcode "
>>> -		"(bits 0x%lx undefined): %s %s"),
>>> -	      ~(unsigned long)(used_bits & required_bits),
>>> +		"(bits 0x%llx undefined or invalid): %s %s"),
>>> +	      (unsigned long long)(used_bits ^ required_bits),
>>
>> May I encourage the use of the # format modifier in cases like this
>> one (i.e. %#llx here), for producing a one character shorter string
>> literal? Iirc a respective adjustment was done pretty recently to
>> some other parts of binutils.
> 
> I would disagree if it was a part of the core disassembling portion
> but...

Sure - typically in disassembly you want to output leading zeros, and
in that case using # isn't desirable. (I've observed RISC-V disassembly
to omit leading zeros in certain cases though, which personally I find
confusing.)

Jan

> seems okay here (as exact formatting is not important).  It would
> have changed the behavior if (used_bits ^ required_bits) is not zero
> (e.g. with "%#x": "0" (0), "0x1" (1)...) but here, (used_bits ^
> required_bits) cannot be zero.  So, the behavior won't change either.
> 
> Thanks,
> Tsukasa


  reply	other threads:[~2022-10-06  8:43 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-09  3:50 [PATCH 0/2] " Tsukasa OI
2022-07-09  3:50 ` [PATCH 1/2] " Tsukasa OI
2022-07-09  3:50 ` [PATCH 2/2] RISC-V: Fix required bits on certain environments Tsukasa OI
2022-10-06  4:40 ` [PATCH v2 0/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06  4:40   ` [PATCH v2 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-06  8:22     ` Jan Beulich
2022-10-06  9:52       ` Tsukasa OI
2022-10-06  4:40   ` [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06  8:26     ` Jan Beulich
2022-10-06  8:34       ` Tsukasa OI
2022-10-06  8:43         ` Jan Beulich [this message]
2022-10-06  9:56   ` [PATCH v3 0/2] " Tsukasa OI
2022-10-06  9:56     ` [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-14  1:32       ` Nelson Chu
2022-10-14  7:07         ` Jan Beulich
2022-10-16 13:32         ` Tsukasa OI
2022-10-28  9:41           ` Nelson Chu
2022-10-06  9:56     ` [PATCH v3 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI

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