From: Jan Beulich <jbeulich@suse.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
binutils@sourceware.org,
Tsukasa OI <research_trasio@irq.a4lg.com>
Subject: Re: [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b
Date: Fri, 14 Oct 2022 09:07:04 +0200 [thread overview]
Message-ID: <8ad79a0f-e90b-07e3-93e3-70924aaf4965@suse.com> (raw)
In-Reply-To: <CAPpQWtAKAbqfGzZEn--nb-V5O5z8R+OXTWq68GuzrFhvzevCNw@mail.gmail.com>
On 14.10.2022 03:32, Nelson Chu wrote:
> In fact we don't really need this change, since so far the parameter
> length of validate_riscv_insn will only be 2 and 4,
> https://github.com/bminor/binutils-gdb/blob/master/gas/config/tc-riscv.c#L1349
Hmm, it is clearly said ...
> On Thu, Oct 6, 2022 at 5:56 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>>
>> We don't support instructions longer than 64-bits yet. Still, we can
>> modify validate_riscv_insn function to prevent unexpected behavior by
>> limiting the "length" of an instruction to 64-bit (or less).
... here that the change is to avoid surprises going forward.
Jan
>> gas/ChangeLog:
>>
>> * config/tc-riscv.c (validate_riscv_insn): Fix function
>> description comment based on current spec. Limit instruction
>> length up to 64-bit for now. Make sure that required_bits does
>> not corrupt even if unsigned long long is longer than 64-bit.
>> ---
>> gas/config/tc-riscv.c | 13 ++++++++-----
>> 1 file changed, 8 insertions(+), 5 deletions(-)
>>
>> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
>> index 22385d1baa0..41d6dfc6062 100644
>> --- a/gas/config/tc-riscv.c
>> +++ b/gas/config/tc-riscv.c
>> @@ -1109,7 +1109,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
>>
>> /* For consistency checking, verify that all bits are specified either
>> by the match/mask part of the instruction definition, or by the
>> - operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
>> + operand list. The `length` could be the actual instruction length or
>> + 0 for auto-detection. */
>>
>> static bool
>> validate_riscv_insn (const struct riscv_opcode *opc, int length)
>> @@ -1120,11 +1121,13 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>> insn_t required_bits;
>>
>> if (length == 0)
>> - insn_width = 8 * riscv_insn_length (opc->match);
>> - else
>> - insn_width = 8 * length;
>> + length = riscv_insn_length (opc->match);
>> + /* We don't support instructions longer than 64-bits yet. */
>> + if (length > 8)
>> + length = 8;
>> + insn_width = 8 * length;
>>
>> - required_bits = ~0ULL >> (64 - insn_width);
>> + required_bits = ((insn_t)~0ULL) >> (64 - insn_width);
>>
>> if ((used_bits & opc->match) != (opc->match & required_bits))
>> {
>> --
>> 2.34.1
>>
next prev parent reply other threads:[~2022-10-14 7:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 3:50 [PATCH 0/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-07-09 3:50 ` [PATCH 1/2] " Tsukasa OI
2022-07-09 3:50 ` [PATCH 2/2] RISC-V: Fix required bits on certain environments Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 0/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-06 8:22 ` Jan Beulich
2022-10-06 9:52 ` Tsukasa OI
2022-10-06 4:40 ` [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
2022-10-06 8:26 ` Jan Beulich
2022-10-06 8:34 ` Tsukasa OI
2022-10-06 8:43 ` Jan Beulich
2022-10-06 9:56 ` [PATCH v3 0/2] " Tsukasa OI
2022-10-06 9:56 ` [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b Tsukasa OI
2022-10-14 1:32 ` Nelson Chu
2022-10-14 7:07 ` Jan Beulich [this message]
2022-10-16 13:32 ` Tsukasa OI
2022-10-28 9:41 ` Nelson Chu
2022-10-06 9:56 ` [PATCH v3 2/2] RISC-V: Improve "bits undefined" diagnostics Tsukasa OI
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