[PATCH v8 0/7] RISC-V: Fix address printer on the disassembler

[PATCH v8 0/7] RISC-V: Fix address printer on the disassembler

[Tsukasa OI]

Hello,

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_fix_addr>

Original Issue as reported by H. Peter Anvin:
<https://sourceware.org/bugzilla/show_bug.cgi?id=29342>

Previous Information on v1...v7:
<https://sourceware.org/pipermail/binutils/2022-August/122552.html>
See this e-mail for background.



Based on Nelson's feedback, I functionally splitted the patchset to four
mostly independent parts.  Tests are self-contained to each part (unlike
dis-addr-2.s in PATCH v7) so that we can review each part independently.

(1) [PATCH 1-1] Additional tests for existing part: sequence with ADDIW
                (because we will test other cases in detail on other parts)
(2) [PATCH 2-3] Fix to PR29342 and a new JALR issue
                (both discovered by H. Peter Anvin)
(3) [PATCH 4-5] Make the disassembler able to print the highest address
                and GP-relative addresses even if the GP is the top addr
(4) [PATCH 6-7] Code Tidying: Rename and retype `wide' parameter of
                `maybe_print_address' for further clarification of the code


On 2022/08/24 20:22, Nelson Chu wrote:
> I think there are three dis-assembler issues here,
> 
> 1. PR29342
> 2. The target address of jump
> 3. Should we show the target address when it is -1

cf. <https://sourceware.org/pipermail/binutils/2022-August/122573.html>

Based on Nelson's classification, part (2) corresponds [1.] and [2.] and
(3) corresponds [3.].  About issues [1.] and [2.], PATCH 2 fixes [2.] and
PATCH 3 fixes [1.] but tests for [2.] is in the PATCH 3 (not PATCH 2).

This is because PATCH 3 tests address printing in various ways including
JALR instructions.  So splitting them to PATCH 2 seemed too redundant.


And, I couldn't come up with a good explanation to `binutils/NEWS'
describing the changes in the part (3).  Could someone help me?  It enables
printing following addresses on disassembling:

-   The highest address (-1)
-   GP-relative addresses if GP has the highest address (-1)



[Extraction Guide]

If we extract each part ((1) through (4)) using git rebase, we may
encounter some conflicts and test failures.  Even so, to extract (3) and
(4), I recommend to apply at least (2) through (4) first and then extract
using git rebase.

(1)
    This is completely independent from the rest.
(2)
    This is independent from (1).
(3)
    This is independent from (1).
    This is MOSTLY independent from (2) but extracting causes one conflict
    and two test errors (that depend on the bugfix on (2)):
        # Conflict: keep those lines
          else
            return;  /* Don't print the address.  */
          pd->to_print_addr = true;
        # Test Failures: two changes are required to pass check-gas
            # gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
                old: <addr_top>
                new: <addr_top\+0x0>
            # gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
                old: <addr_rel_gp_pos>
                new: <__global_pointer\$\+0x5>
(4)
    This is independent from (1).
    This is independent from (3).
    This is MOSTLY independent from (2) but extracting causes one conflict.
        # Conflict: change like this and keep (to NOT keep the bugfix in (2))
        old: maybe_print_address (pd, rs1, 0, 0);
        new: maybe_print_address (pd, rs1, 0, false);




Tsukasa OI (7):
  RISC-V: Add address printer tests with ADDIW
  RISC-V: Fix JALR target address computation
  RISC-V: Fix RV32 disassembler address computation
  RISC-V: Print highest address on the disassembler
  RISC-V: Print top GP-relative addresses on the disassembler
  RISC-V: Clarify that `wide' is only used for ADDIW
  RISC-V: Make `is_addiw' parameter bool

 gas/testsuite/gas/riscv/dis-addr-addiw-a.d    | 18 +++++
 gas/testsuite/gas/riscv/dis-addr-addiw-b.d    | 18 +++++
 gas/testsuite/gas/riscv/dis-addr-addiw.s      | 28 ++++++++
 .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
 .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
 gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++
 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++
 .../gas/riscv/dis-addr-topaddr-gp-32.d        | 12 ++++
 .../gas/riscv/dis-addr-topaddr-gp-64.d        | 12 ++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 15 ++++
 gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 +++
 gas/testsuite/gas/riscv/lla32.d               |  2 +-
 opcodes/riscv-dis.c                           | 46 +++++++-----
 14 files changed, 300 insertions(+), 17 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s


base-commit: 46e59b72f21029f2a863e3828cec76a03283b49d
-- 
2.34.1

[PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW

[Tsukasa OI]

Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.

This commit tests whether this sign-extension works.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
	computation with sign extension as used in ADDIW/C.ADDIW.
	* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
	* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
	* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
	* testsuite/gas/riscv/dis-addr-addiw.s: New test.
---
 gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 18 ++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 18 ++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-addiw.s   | 28 ++++++++++++++++++++++
 3 files changed, 64 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
new file mode 100644
index 00000000000..3cd9d4e3805
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-addiw.s
+#objdump: -d --adjust-vma=0xffffffe0
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+ffffffe0 <_start>:
+[ 	]+ffffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
+[ 	]+ffffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
+[ 	]+ffffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+ffffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
+[ 	]+fffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
+[ 	]+fffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
+[ 	]+fffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
+[ 	]+fffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
new file mode 100644
index 00000000000..2c68d6b6e5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-addiw.s
+#objdump: -d --adjust-vma=0x7fffffe0
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+7fffffe0 <_start>:
+[ 	]+7fffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
+[ 	]+7fffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
+[ 	]+7fffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+7fffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
+[ 	]+7ffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
+[ 	]+7ffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
+[ 	]+7ffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
+[ 	]+7ffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw.s b/gas/testsuite/gas/riscv/dis-addr-addiw.s
new file mode 100644
index 00000000000..7c878f86dd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw.s
@@ -0,0 +1,28 @@
+.set addr_rv64_addiw_0a,   0xfffffffffffffff8  # 0xffffffe0 + 0x18 (sext:32->64)
+.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc  # 0xfffffff0 + 0x0c (sext:32->64)
+.set addr_rv64_addiw_0b,           0x00000004  # 0xffffffe8 + 0x1c
+.set addr_rv64_c_addiw_0b,         0x00000008  # 0xfffffff6 + 0x12
+.set addr_rv64_addiw_1a,           0x7ffffff8  # 0x7fffffe0 + 0x18
+.set addr_rv64_c_addiw_1a,         0x7ffffffc  # 0x7ffffff0 + 0x0c
+.set addr_rv64_addiw_1b,   0xffffffff80000004  # 0x7fffffe8 + 0x1c (sext:32->64)
+.set addr_rv64_c_addiw_1b, 0xffffffff80000008  # 0x7ffffff6 + 0x12 (sext:32->64)
+
+	.text
+	.global	_start
+_start:
+	.option	push
+	.option	arch, -c
+	# _start + 0x00
+	auipc	t0, 0
+	addiw	t1, t0, 0x18
+	# _start + 0x08
+	auipc	t2, 0
+	addiw	t3, t2, 0x1c
+
+	.option	pop
+	# _start + 0x10
+	auipc	t4, 0
+	c.addiw	t4, 0x0c
+	# _start + 0x16
+	auipc	t5, 0
+	c.addiw	t5, 0x12
-- 
2.34.1

[PATCH v8 2/7] RISC-V: Fix JALR target address computation

[Tsukasa OI]

H. Peter Anvin discovered that we have wrong address computation for JALR
instruction (the initial bug is back in 2018).  This commit will fix that
based on the idea of Palmer Dabbelt.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix JALR address computation.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args):
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 164fd209dbd..4c03f113650 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -397,7 +397,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, 0, 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
-- 
2.34.1

[PATCH v8 3/7] RISC-V: Fix RV32 disassembler address computation

[Tsukasa OI]

If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing.  This commit
fixes this bug (including PR29342) by fitting an address into a 32-bit value
on RV32.

gas/ChangeLog:

	* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
	* testsuite/gas/riscv/dis-addr-overflow.s: New test for RV32/64
	address overflow.
	* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Fit the address into 32-bit
	on RV32.
---
 .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
 .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
 gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
 gas/testsuite/gas/riscv/lla32.d               |  2 +-
 opcodes/riscv-dis.c                           |  6 ++
 5 files changed, 141 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
new file mode 100644
index 00000000000..43f712a2263
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
@@ -0,0 +1,30 @@
+#as: -march=rv32ic
+#source: dis-addr-overflow.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fffff2b7[ 	]+lui[  	]+t0,0xfffff
+[ 	]+[0-9a-f]+:[ 	]+ffc2a903[ 	]+lw[   	]+s2,-4\(t0\) # ffffeffc <addr_load>
+[ 	]+[0-9a-f]+:[ 	]+ffffe337[ 	]+lui[  	]+t1,0xffffe
+[ 	]+[0-9a-f]+:[ 	]+ff332c23[ 	]+sw[   	]+s3,-8\(t1\) # ffffdff8 <addr_store>
+[ 	]+[0-9a-f]+:[ 	]+ffffd3b7[ 	]+lui[  	]+t2,0xffffd
+[ 	]+[0-9a-f]+:[ 	]+000380e7[ 	]+jalr[ 	]+t2 # ffffd000 <addr_jalr_1>
+[ 	]+[0-9a-f]+:[ 	]+ffffce37[ 	]+lui[  	]+t3,0xffffc
+[ 	]+[0-9a-f]+:[ 	]+ff4e00e7[ 	]+jalr[ 	]+-12\(t3\) # ffffbff4 <addr_jalr_2>
+[ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
+[ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffb000 <addr_jalr_3>
+[ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
+[ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80002e03[ 	]+lw[   	]+t3,-2048\(zero\) # fffff800 <addr_rel_zero_neg>
+[ 	]+[0-9a-f]+:[ 	]+10400ee7[ 	]+jalr[ 	]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80400f67[ 	]+jalr[ 	]+t5,-2044\(zero\) # fffff804 <addr_jalr_rel_zero_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
new file mode 100644
index 00000000000..065ee2591e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
@@ -0,0 +1,34 @@
+#as: -march=rv64ic -defsym rv64=1
+#source: dis-addr-overflow.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fffff2b7[ 	]+lui[  	]+t0,0xfffff
+[ 	]+[0-9a-f]+:[ 	]+ffc2a903[ 	]+lw[   	]+s2,-4\(t0\) # ffffffffffffeffc <addr_load>
+[ 	]+[0-9a-f]+:[ 	]+ffffe337[ 	]+lui[  	]+t1,0xffffe
+[ 	]+[0-9a-f]+:[ 	]+ff332c23[ 	]+sw[   	]+s3,-8\(t1\) # ffffffffffffdff8 <addr_store>
+[ 	]+[0-9a-f]+:[ 	]+ffffd3b7[ 	]+lui[  	]+t2,0xffffd
+[ 	]+[0-9a-f]+:[ 	]+000380e7[ 	]+jalr[ 	]+t2 # ffffffffffffd000 <addr_jalr_1>
+[ 	]+[0-9a-f]+:[ 	]+ffffce37[ 	]+lui[  	]+t3,0xffffc
+[ 	]+[0-9a-f]+:[ 	]+ff4e00e7[ 	]+jalr[ 	]+-12\(t3\) # ffffffffffffbff4 <addr_jalr_2>
+[ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
+[ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
+[ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+ffff8b37[ 	]+lui[  	]+s6,0xffff8
+[ 	]+[0-9a-f]+:[ 	]+fe8b0b9b[ 	]+addiw[ 	]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
+[ 	]+[0-9a-f]+:[ 	]+ffff7c37[ 	]+lui[  	]+s8,0xffff7
+[ 	]+[0-9a-f]+:[ 	]+3c11[ 	]+addiw[ 	]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
+[ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
+[ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80002e03[ 	]+lw[   	]+t3,-2048\(zero\) # fffffffffffff800 <addr_rel_zero_neg>
+[ 	]+[0-9a-f]+:[ 	]+10400ee7[ 	]+jalr[ 	]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80400f67[ 	]+jalr[ 	]+t5,-2044\(zero\) # fffffffffffff804 <addr_jalr_rel_zero_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s
new file mode 100644
index 00000000000..046fcaa6117
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s
@@ -0,0 +1,70 @@
+.set __global_pointer$, 0x00000200
+
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set addr_load,              topbase + 0xffffeffc  # -0x1000 -4
+.set addr_store,             topbase + 0xffffdff8  # -0x2000 -8
+.set addr_jalr_1,            topbase + 0xffffd000  # -0x3000
+.set addr_jalr_2,            topbase + 0xffffbff4  # -0x4000 -12
+.set addr_jalr_3,            topbase + 0xffffb000  # -0x5000
+.set addr_loadaddr,          topbase + 0xffff9ff0  # -0x6000 -16
+.set addr_loadaddr_c,        topbase + 0xffff8fec  # -0x7000 -20
+.set addr_loadaddr_w,        topbase + 0xffff7fe8  # -0x8000 -24
+.set addr_loadaddr_w_c,      topbase + 0xffff6fe4  # -0x9000 -28
+.set addr_rel_gp_pos,                  0x00000600  # __global_pointer$ + 0x400
+.set addr_rel_gp_neg,        topbase + 0xfffffe00  # __global_pointer$ - 0x400
+.set addr_rel_zero_pos,                0x00000100
+.set addr_rel_zero_neg,      topbase + 0xfffff800  # -0x800
+.set addr_jalr_rel_zero_pos,           0x00000104  # 0x104
+.set addr_jalr_rel_zero_neg, topbase + 0xfffff804  # -0x7fc
+
+target:
+	.option	push
+	.option	arch, -c
+	## Use hi_addr
+	# Load
+	lui	t0, 0xfffff
+	lw	s2, -4(t0)
+	# Store
+	lui	t1, 0xffffe
+	sw	s3, -8(t1)
+	# JALR (implicit destination, no offset)
+	lui	t2, 0xffffd
+	jalr	t2
+	# JALR (implicit destination, with offset)
+	lui	t3, 0xffffc
+	jalr	-12(t3)
+	# JALR (explicit destination, no offset)
+	lui	t4, 0xffffb
+	jalr	s4, t4
+	# ADDI (not compressed)
+	lui	t5, 0xffffa
+	addi	s5, t5, -16
+	# C.ADDI
+	lui	t6, 0xffff9
+	.option	pop
+	c.addi	t6, -20
+.ifdef rv64
+	.option	push
+	.option	arch, -c
+	# ADDIW (not compressed)
+	lui	s6, 0xffff8
+	addiw	s7, s6, -24
+	# C.ADDIW
+	lui	s8, 0xffff7
+	.option	pop
+	c.addiw	s8, -28
+.endif
+
+	# Use addresses relative to gp
+	lw	t0, 0x400(gp)
+	lw	t1, -0x400(gp)
+	# Use addresses relative to zero
+	lw	t2, 0x100(zero)
+	lw	t3, -0x800(zero)
+	jalr	t4, 0x104(zero)
+	jalr	t5, -0x7fc(zero)
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index 9d875629064..8e9324c1c96 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -14,6 +14,6 @@ Disassembly of section .text:
   10:	00001537          	lui	a0,0x1
   14:	fff50513          	addi	a0,a0,-1 # fff <d>
   18:	80000537          	lui	a0,0x80000
-  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <e>
   20:	00000513          	li	a0,0
   24:	fff00513          	li	a0,-1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 4c03f113650..b3ca680e506 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -181,10 +181,16 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = pd->gp + offset;
   else if (base_reg == X_TP || base_reg == 0)
     pd->print_addr = offset;
+  else
+    return;  /* Don't print the address.  */
 
   /* Sign-extend a 32-bit value to a 64-bit value.  */
   if (wide)
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
+
+  /* Fit into a 32-bit value on RV32.  */
+  if (xlen == 32)
+    pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
 }
 
 /* Print insn arguments for 32/64-bit code.  */
-- 
2.34.1

[PATCH v8 4/7] RISC-V: Print highest address on the disassembler

[Tsukasa OI]

This patch makes possible to print the highest address (0xffffffff on RV32,
0xffffffff_ffffffff on RV64).  This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols
are defined.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
	address printing.
	* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
	enable printing the highest address.
	(maybe_print_address): Utilize `to_print_addr'.
	(riscv_disassemble_insn): Likewise.
---
 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 ++++++++++
 opcodes/riscv-dis.c                           |  9 ++++++---
 4 files changed, 38 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
new file mode 100644
index 00000000000..87854cd58e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
@@ -0,0 +1,11 @@
+#as: -march=rv32ic
+#source: dis-addr-topaddr.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fff00283[ 	]+lb[   	]+t0,-1\(zero\) # ffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
new file mode 100644
index 00000000000..38f67efdcaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
@@ -0,0 +1,11 @@
+#as: -march=rv64ic -defsym rv64=1
+#source: dis-addr-topaddr.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fff00283[ 	]+lb[   	]+t0,-1\(zero\) # ffffffffffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr.s b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
new file mode 100644
index 00000000000..b66587f448d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
@@ -0,0 +1,10 @@
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set addr_top, topbase + 0xffffffff  # -1
+
+target:
+	lb	t0, -1(zero)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index b3ca680e506..7532c72187d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -52,6 +52,7 @@ struct riscv_private_data
   bfd_vma gp;
   bfd_vma print_addr;
   bfd_vma hi_addr[OP_MASK_RD + 1];
+  bool to_print_addr;
 };
 
 /* Used for mapping symbols.  */
@@ -183,6 +184,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = offset;
   else
     return;  /* Don't print the address.  */
+  pd->to_print_addr = true;
 
   /* Sign-extend a 32-bit value to a 64-bit value.  */
   if (wide)
@@ -602,9 +604,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
       pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
       pd->gp = -1;
-      pd->print_addr = -1;
+      pd->print_addr = 0;
       for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
 	pd->hi_addr[i] = -1;
+      pd->to_print_addr = false;
 
       for (i = 0; i < info->symtab_size; i++)
 	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
@@ -668,13 +671,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  print_insn_args (op->args, word, memaddr, info);
 
 	  /* Try to disassemble multi-instruction addressing sequences.  */
-	  if (pd->print_addr != (bfd_vma)-1)
+	  if (pd->to_print_addr)
 	    {
 	      info->target = pd->print_addr;
 	      (*info->fprintf_styled_func)
 		(info->stream, dis_style_comment_start, " # ");
 	      (*info->print_address_func) (info->target, info);
-	      pd->print_addr = -1;
+	      pd->to_print_addr = false;
 	    }
 
 	  /* Finish filling out insn_info fields.  */
-- 
2.34.1

[PATCH v8 5/7] RISC-V: Print top GP-relative addresses on the disassembler

[Tsukasa OI]

This patch makes possible to print the address relative to the global
pointer even if the corresponding symbol is the highest address (0xffffffff
on RV32, 0xffffffff_ffffffff on RV64).

Despite that it is very rare to have GP the highest address, it would be
nice because we enabled highest address printing on regular cases.

opcodes/ChangeLog:

	* riscv-dis.c (struct riscv_private_data): Add `has_gp' to enable
	printing the addresses relative to GP with the highest address.
	(maybe_print_address): Utilize `has_gp'.
	(riscv_disassemble_insn): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-
	relative addressing when GP is the highest address.
	* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
---
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s    | 15 +++++++++++++++
 opcodes/riscv-dis.c                              | 11 ++++++++---
 4 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
new file mode 100644
index 00000000000..875bfe73189
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i
+#source: dis-addr-topaddr-gp.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0051a283[ 	]+lw[   	]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+ffd1a303[ 	]+lw[   	]+t1,-3\(gp\) # fffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
new file mode 100644
index 00000000000..5ac4b52b18d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i -defsym rv64=1
+#source: dis-addr-topaddr-gp.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0051a283[ 	]+lw[   	]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+ffd1a303[ 	]+lw[   	]+t1,-3\(gp\) # fffffffffffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
new file mode 100644
index 00000000000..6ba9fc7a39d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
@@ -0,0 +1,15 @@
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set __global_pointer$, topbase + 0xffffffff  # -1
+.set addr_rel_gp_pos,             0x00000004  # +4
+.set addr_rel_gp_neg,   topbase + 0xfffffffc  # -4
+
+target:
+	# Use addresses relative to gp
+	# (gp is the highest address)
+	lw	t0, +5(gp)
+	lw	t1, -3(gp)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7532c72187d..160cc40f865 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -53,6 +53,7 @@ struct riscv_private_data
   bfd_vma print_addr;
   bfd_vma hi_addr[OP_MASK_RD + 1];
   bool to_print_addr;
+  bool has_gp;
 };
 
 /* Used for mapping symbols.  */
@@ -178,7 +179,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
       pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
       pd->hi_addr[base_reg] = -1;
     }
-  else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
+  else if (base_reg == X_GP && pd->has_gp)
     pd->print_addr = pd->gp + offset;
   else if (base_reg == X_TP || base_reg == 0)
     pd->print_addr = offset;
@@ -603,15 +604,19 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
       int i;
 
       pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
-      pd->gp = -1;
+      pd->gp = 0;
       pd->print_addr = 0;
       for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
 	pd->hi_addr[i] = -1;
       pd->to_print_addr = false;
+      pd->has_gp = false;
 
       for (i = 0; i < info->symtab_size; i++)
 	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
-	  pd->gp = bfd_asymbol_value (info->symtab[i]);
+	  {
+	    pd->gp = bfd_asymbol_value (info->symtab[i]);
+	    pd->has_gp = true;
+	  }
     }
   else
     pd = info->private_data;
-- 
2.34.1

[PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW

[Tsukasa OI]

The `wide' parameter on the `maybe_print_address' function is only used
for the ADDIW/C.ADDIW instructions and there's no reasonable usecases except
those two.

This commit renames the parameter from `wide' to `is_addiw' to clarify that
this parameter is only used for ADDIW instructions.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Clarify and rename the last
	parameter so that this is only used for ADDIW instructions.
---
 opcodes/riscv-dis.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 160cc40f865..7322db10d24 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
 
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
-		     int wide)
+		     int is_addiw)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -187,8 +187,8 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     return;  /* Don't print the address.  */
   pd->to_print_addr = true;
 
-  /* Sign-extend a 32-bit value to a 64-bit value.  */
-  if (wide)
+  /* On ADDIW, sign-extend a 32-bit value to a 64-bit value.  */
+  if (is_addiw)
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
 
   /* Fit into a 32-bit value on RV32.  */
-- 
2.34.1

[PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool

[Tsukasa OI]

Because we widely use `bool' type, this commit makes this parameter `bool'
in the process of tidying.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Change `is_addiw' type from
	`int' to `bool'.  (print_insn_args): Use boolean values.
---
 opcodes/riscv-dis.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7322db10d24..d4c1a5505b1 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
 
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
-		     int is_addiw)
+		     bool is_addiw)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -243,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'o':
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false);
 	      if (info->mach == bfd_mach_riscv64
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true);
 	      print (info->stream, dis_style_immediate, "%d",
 		     (int)EXTRACT_CITYPE_IMM (l));
 	      break;
@@ -406,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
@@ -436,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  break;
 
 	case 'o':
-	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  /* Fall through.  */
 	case 'j':
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  if (info->mach == bfd_mach_riscv64
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true);
 	  print (info->stream, dis_style_immediate, "%d",
 		 (int)EXTRACT_ITYPE_IMM (l));
 	  break;
 
 	case 'q':
-	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false);
 	  print (info->stream, dis_style_address_offset, "%d",
 		 (int)EXTRACT_STYPE_IMM (l));
 	  break;
-- 
2.34.1

[PATCH v8 0/7] RISC-V: Fix address printer on the disassembler

[Tsukasa OI]

Hello,

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_fix_addr>

Original Issue as reported by H. Peter Anvin:
<https://sourceware.org/bugzilla/show_bug.cgi?id=29342>

Previous Information on v1...v7:
<https://sourceware.org/pipermail/binutils/2022-August/122552.html>
See this e-mail for background.


[Changes: v8 -> v9]

Sorry! I forgot to remove redundant ChangeLog lines.



Based on Nelson's feedback, I functionally splitted the patchset to four
mostly independent parts.  Tests are self-contained to each part (unlike
dis-addr-2.s in PATCH v7) so that we can review each part independently.

(1) [PATCH 1-1] Additional tests for existing part: sequence with ADDIW
                (because we will test other cases in detail on other parts)
(2) [PATCH 2-3] Fix to PR29342 and a new JALR issue
                (both discovered by H. Peter Anvin)
(3) [PATCH 4-5] Make the disassembler able to print the highest address
                and GP-relative addresses even if the GP is the top addr
(4) [PATCH 6-7] Code Tidying: Rename and retype `wide' parameter of
                `maybe_print_address' for further clarification of the code


On 2022/08/24 20:22, Nelson Chu wrote:
> I think there are three dis-assembler issues here,
> 
> 1. PR29342
> 2. The target address of jump
> 3. Should we show the target address when it is -1

cf. <https://sourceware.org/pipermail/binutils/2022-August/122573.html>

Based on Nelson's classification, part (2) corresponds [1.] and [2.] and
(3) corresponds [3.].  About issues [1.] and [2.], PATCH 2 fixes [2.] and
PATCH 3 fixes [1.] but tests for [2.] is in the PATCH 3 (not PATCH 2).

This is because PATCH 3 tests address printing in various ways including
JALR instructions.  So splitting them to PATCH 2 seemed too redundant.


And, I couldn't come up with a good explanation to `binutils/NEWS'
describing the changes in the part (3).  Could someone help me?  It enables
printing following addresses on disassembling:

-   The highest address (-1)
-   GP-relative addresses if GP has the highest address (-1)



[Extraction Guide]

If we extract each part ((1) through (4)) using git rebase, we may
encounter some conflicts and test failures.  Even so, to extract (3) and
(4), I recommend to apply at least (2) through (4) first and then extract
using git rebase.

(1)
    This is completely independent from the rest.
(2)
    This is independent from (1).
(3)
    This is independent from (1).
    This is MOSTLY independent from (2) but extracting causes one conflict
    and two test errors (that depend on the bugfix on (2)):
        # Conflict: keep those lines
          else
            return;  /* Don't print the address.  */
          pd->to_print_addr = true;
        # Test Failures: two changes are required to pass check-gas
            # gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
                old: <addr_top>
                new: <addr_top\+0x0>
            # gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
                old: <addr_rel_gp_pos>
                new: <__global_pointer\$\+0x5>
(4)
    This is independent from (1).
    This is independent from (3).
    This is MOSTLY independent from (2) but extracting causes one conflict.
        # Conflict: change like this and keep (to NOT keep the bugfix in (2))
        old: maybe_print_address (pd, rs1, 0, 0);
        new: maybe_print_address (pd, rs1, 0, false);




Tsukasa OI (7):
  RISC-V: Add address printer tests with ADDIW
  RISC-V: Fix JALR target address computation
  RISC-V: Fix RV32 disassembler address computation
  RISC-V: Print highest address on the disassembler
  RISC-V: Print top GP-relative addresses on the disassembler
  RISC-V: Clarify that `wide' is only used for ADDIW
  RISC-V: Make `is_addiw' parameter bool

 gas/testsuite/gas/riscv/dis-addr-addiw-a.d    | 18 +++++
 gas/testsuite/gas/riscv/dis-addr-addiw-b.d    | 18 +++++
 gas/testsuite/gas/riscv/dis-addr-addiw.s      | 28 ++++++++
 .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
 .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
 gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++
 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++
 .../gas/riscv/dis-addr-topaddr-gp-32.d        | 12 ++++
 .../gas/riscv/dis-addr-topaddr-gp-64.d        | 12 ++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 15 ++++
 gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 +++
 gas/testsuite/gas/riscv/lla32.d               |  2 +-
 opcodes/riscv-dis.c                           | 46 +++++++-----
 14 files changed, 300 insertions(+), 17 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s


base-commit: 46e59b72f21029f2a863e3828cec76a03283b49d
-- 
2.34.1

[PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW

[Tsukasa OI]

Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.

This commit tests whether this sign-extension works.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
	computation with sign extension as used in ADDIW/C.ADDIW.
	* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
	* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
---
 gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 18 ++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 18 ++++++++++++++
 gas/testsuite/gas/riscv/dis-addr-addiw.s   | 28 ++++++++++++++++++++++
 3 files changed, 64 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
new file mode 100644
index 00000000000..3cd9d4e3805
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-addiw.s
+#objdump: -d --adjust-vma=0xffffffe0
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+ffffffe0 <_start>:
+[ 	]+ffffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
+[ 	]+ffffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
+[ 	]+ffffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+ffffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
+[ 	]+fffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
+[ 	]+fffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
+[ 	]+fffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
+[ 	]+fffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
new file mode 100644
index 00000000000..2c68d6b6e5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-addiw.s
+#objdump: -d --adjust-vma=0x7fffffe0
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+7fffffe0 <_start>:
+[ 	]+7fffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
+[ 	]+7fffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
+[ 	]+7fffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+7fffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
+[ 	]+7ffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
+[ 	]+7ffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
+[ 	]+7ffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
+[ 	]+7ffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw.s b/gas/testsuite/gas/riscv/dis-addr-addiw.s
new file mode 100644
index 00000000000..7c878f86dd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw.s
@@ -0,0 +1,28 @@
+.set addr_rv64_addiw_0a,   0xfffffffffffffff8  # 0xffffffe0 + 0x18 (sext:32->64)
+.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc  # 0xfffffff0 + 0x0c (sext:32->64)
+.set addr_rv64_addiw_0b,           0x00000004  # 0xffffffe8 + 0x1c
+.set addr_rv64_c_addiw_0b,         0x00000008  # 0xfffffff6 + 0x12
+.set addr_rv64_addiw_1a,           0x7ffffff8  # 0x7fffffe0 + 0x18
+.set addr_rv64_c_addiw_1a,         0x7ffffffc  # 0x7ffffff0 + 0x0c
+.set addr_rv64_addiw_1b,   0xffffffff80000004  # 0x7fffffe8 + 0x1c (sext:32->64)
+.set addr_rv64_c_addiw_1b, 0xffffffff80000008  # 0x7ffffff6 + 0x12 (sext:32->64)
+
+	.text
+	.global	_start
+_start:
+	.option	push
+	.option	arch, -c
+	# _start + 0x00
+	auipc	t0, 0
+	addiw	t1, t0, 0x18
+	# _start + 0x08
+	auipc	t2, 0
+	addiw	t3, t2, 0x1c
+
+	.option	pop
+	# _start + 0x10
+	auipc	t4, 0
+	c.addiw	t4, 0x0c
+	# _start + 0x16
+	auipc	t5, 0
+	c.addiw	t5, 0x12
-- 
2.34.1

[PATCH v8 2/7] RISC-V: Fix JALR target address computation

[Tsukasa OI]

H. Peter Anvin discovered that we have wrong address computation for JALR
instruction (the initial bug is back in 2018).  This commit will fix that
based on the idea of Palmer Dabbelt.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix JALR address computation.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 164fd209dbd..4c03f113650 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -397,7 +397,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, 0, 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
-- 
2.34.1

[PATCH v8 3/7] RISC-V: Fix RV32 disassembler address computation

[Tsukasa OI]

If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing.  This commit
fixes this bug (including PR29342) by fitting an address into a 32-bit value
on RV32.

gas/ChangeLog:

	* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
	* testsuite/gas/riscv/dis-addr-overflow.s: New test for RV32/64
	address overflow.
	* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Fit the address into 32-bit
	on RV32.
---
 .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
 .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
 gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
 gas/testsuite/gas/riscv/lla32.d               |  2 +-
 opcodes/riscv-dis.c                           |  6 ++
 5 files changed, 141 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
new file mode 100644
index 00000000000..43f712a2263
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
@@ -0,0 +1,30 @@
+#as: -march=rv32ic
+#source: dis-addr-overflow.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fffff2b7[ 	]+lui[  	]+t0,0xfffff
+[ 	]+[0-9a-f]+:[ 	]+ffc2a903[ 	]+lw[   	]+s2,-4\(t0\) # ffffeffc <addr_load>
+[ 	]+[0-9a-f]+:[ 	]+ffffe337[ 	]+lui[  	]+t1,0xffffe
+[ 	]+[0-9a-f]+:[ 	]+ff332c23[ 	]+sw[   	]+s3,-8\(t1\) # ffffdff8 <addr_store>
+[ 	]+[0-9a-f]+:[ 	]+ffffd3b7[ 	]+lui[  	]+t2,0xffffd
+[ 	]+[0-9a-f]+:[ 	]+000380e7[ 	]+jalr[ 	]+t2 # ffffd000 <addr_jalr_1>
+[ 	]+[0-9a-f]+:[ 	]+ffffce37[ 	]+lui[  	]+t3,0xffffc
+[ 	]+[0-9a-f]+:[ 	]+ff4e00e7[ 	]+jalr[ 	]+-12\(t3\) # ffffbff4 <addr_jalr_2>
+[ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
+[ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffb000 <addr_jalr_3>
+[ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
+[ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80002e03[ 	]+lw[   	]+t3,-2048\(zero\) # fffff800 <addr_rel_zero_neg>
+[ 	]+[0-9a-f]+:[ 	]+10400ee7[ 	]+jalr[ 	]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80400f67[ 	]+jalr[ 	]+t5,-2044\(zero\) # fffff804 <addr_jalr_rel_zero_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
new file mode 100644
index 00000000000..065ee2591e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
@@ -0,0 +1,34 @@
+#as: -march=rv64ic -defsym rv64=1
+#source: dis-addr-overflow.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fffff2b7[ 	]+lui[  	]+t0,0xfffff
+[ 	]+[0-9a-f]+:[ 	]+ffc2a903[ 	]+lw[   	]+s2,-4\(t0\) # ffffffffffffeffc <addr_load>
+[ 	]+[0-9a-f]+:[ 	]+ffffe337[ 	]+lui[  	]+t1,0xffffe
+[ 	]+[0-9a-f]+:[ 	]+ff332c23[ 	]+sw[   	]+s3,-8\(t1\) # ffffffffffffdff8 <addr_store>
+[ 	]+[0-9a-f]+:[ 	]+ffffd3b7[ 	]+lui[  	]+t2,0xffffd
+[ 	]+[0-9a-f]+:[ 	]+000380e7[ 	]+jalr[ 	]+t2 # ffffffffffffd000 <addr_jalr_1>
+[ 	]+[0-9a-f]+:[ 	]+ffffce37[ 	]+lui[  	]+t3,0xffffc
+[ 	]+[0-9a-f]+:[ 	]+ff4e00e7[ 	]+jalr[ 	]+-12\(t3\) # ffffffffffffbff4 <addr_jalr_2>
+[ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
+[ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
+[ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+ffff8b37[ 	]+lui[  	]+s6,0xffff8
+[ 	]+[0-9a-f]+:[ 	]+fe8b0b9b[ 	]+addiw[ 	]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
+[ 	]+[0-9a-f]+:[ 	]+ffff7c37[ 	]+lui[  	]+s8,0xffff7
+[ 	]+[0-9a-f]+:[ 	]+3c11[ 	]+addiw[ 	]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
+[ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
+[ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80002e03[ 	]+lw[   	]+t3,-2048\(zero\) # fffffffffffff800 <addr_rel_zero_neg>
+[ 	]+[0-9a-f]+:[ 	]+10400ee7[ 	]+jalr[ 	]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ 	]+[0-9a-f]+:[ 	]+80400f67[ 	]+jalr[ 	]+t5,-2044\(zero\) # fffffffffffff804 <addr_jalr_rel_zero_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s
new file mode 100644
index 00000000000..046fcaa6117
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s
@@ -0,0 +1,70 @@
+.set __global_pointer$, 0x00000200
+
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set addr_load,              topbase + 0xffffeffc  # -0x1000 -4
+.set addr_store,             topbase + 0xffffdff8  # -0x2000 -8
+.set addr_jalr_1,            topbase + 0xffffd000  # -0x3000
+.set addr_jalr_2,            topbase + 0xffffbff4  # -0x4000 -12
+.set addr_jalr_3,            topbase + 0xffffb000  # -0x5000
+.set addr_loadaddr,          topbase + 0xffff9ff0  # -0x6000 -16
+.set addr_loadaddr_c,        topbase + 0xffff8fec  # -0x7000 -20
+.set addr_loadaddr_w,        topbase + 0xffff7fe8  # -0x8000 -24
+.set addr_loadaddr_w_c,      topbase + 0xffff6fe4  # -0x9000 -28
+.set addr_rel_gp_pos,                  0x00000600  # __global_pointer$ + 0x400
+.set addr_rel_gp_neg,        topbase + 0xfffffe00  # __global_pointer$ - 0x400
+.set addr_rel_zero_pos,                0x00000100
+.set addr_rel_zero_neg,      topbase + 0xfffff800  # -0x800
+.set addr_jalr_rel_zero_pos,           0x00000104  # 0x104
+.set addr_jalr_rel_zero_neg, topbase + 0xfffff804  # -0x7fc
+
+target:
+	.option	push
+	.option	arch, -c
+	## Use hi_addr
+	# Load
+	lui	t0, 0xfffff
+	lw	s2, -4(t0)
+	# Store
+	lui	t1, 0xffffe
+	sw	s3, -8(t1)
+	# JALR (implicit destination, no offset)
+	lui	t2, 0xffffd
+	jalr	t2
+	# JALR (implicit destination, with offset)
+	lui	t3, 0xffffc
+	jalr	-12(t3)
+	# JALR (explicit destination, no offset)
+	lui	t4, 0xffffb
+	jalr	s4, t4
+	# ADDI (not compressed)
+	lui	t5, 0xffffa
+	addi	s5, t5, -16
+	# C.ADDI
+	lui	t6, 0xffff9
+	.option	pop
+	c.addi	t6, -20
+.ifdef rv64
+	.option	push
+	.option	arch, -c
+	# ADDIW (not compressed)
+	lui	s6, 0xffff8
+	addiw	s7, s6, -24
+	# C.ADDIW
+	lui	s8, 0xffff7
+	.option	pop
+	c.addiw	s8, -28
+.endif
+
+	# Use addresses relative to gp
+	lw	t0, 0x400(gp)
+	lw	t1, -0x400(gp)
+	# Use addresses relative to zero
+	lw	t2, 0x100(zero)
+	lw	t3, -0x800(zero)
+	jalr	t4, 0x104(zero)
+	jalr	t5, -0x7fc(zero)
diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d
index 9d875629064..8e9324c1c96 100644
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -14,6 +14,6 @@ Disassembly of section .text:
   10:	00001537          	lui	a0,0x1
   14:	fff50513          	addi	a0,a0,-1 # fff <d>
   18:	80000537          	lui	a0,0x80000
-  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <e>
   20:	00000513          	li	a0,0
   24:	fff00513          	li	a0,-1
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 4c03f113650..b3ca680e506 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -181,10 +181,16 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = pd->gp + offset;
   else if (base_reg == X_TP || base_reg == 0)
     pd->print_addr = offset;
+  else
+    return;  /* Don't print the address.  */
 
   /* Sign-extend a 32-bit value to a 64-bit value.  */
   if (wide)
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
+
+  /* Fit into a 32-bit value on RV32.  */
+  if (xlen == 32)
+    pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
 }
 
 /* Print insn arguments for 32/64-bit code.  */
-- 
2.34.1

[PATCH v8 4/7] RISC-V: Print highest address on the disassembler

[Tsukasa OI]

This patch makes possible to print the highest address (0xffffffff on RV32,
0xffffffff_ffffffff on RV64).  This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols
are defined.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
	address printing.
	* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
	enable printing the highest address.
	(maybe_print_address): Utilize `to_print_addr'.
	(riscv_disassemble_insn): Likewise.
---
 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 ++++++++++
 opcodes/riscv-dis.c                           |  9 ++++++---
 4 files changed, 38 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
new file mode 100644
index 00000000000..87854cd58e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
@@ -0,0 +1,11 @@
+#as: -march=rv32ic
+#source: dis-addr-topaddr.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fff00283[ 	]+lb[   	]+t0,-1\(zero\) # ffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
new file mode 100644
index 00000000000..38f67efdcaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
@@ -0,0 +1,11 @@
+#as: -march=rv64ic -defsym rv64=1
+#source: dis-addr-topaddr.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+fff00283[ 	]+lb[   	]+t0,-1\(zero\) # ffffffffffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr.s b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
new file mode 100644
index 00000000000..b66587f448d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
@@ -0,0 +1,10 @@
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set addr_top, topbase + 0xffffffff  # -1
+
+target:
+	lb	t0, -1(zero)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index b3ca680e506..7532c72187d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -52,6 +52,7 @@ struct riscv_private_data
   bfd_vma gp;
   bfd_vma print_addr;
   bfd_vma hi_addr[OP_MASK_RD + 1];
+  bool to_print_addr;
 };
 
 /* Used for mapping symbols.  */
@@ -183,6 +184,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = offset;
   else
     return;  /* Don't print the address.  */
+  pd->to_print_addr = true;
 
   /* Sign-extend a 32-bit value to a 64-bit value.  */
   if (wide)
@@ -602,9 +604,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
       pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
       pd->gp = -1;
-      pd->print_addr = -1;
+      pd->print_addr = 0;
       for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
 	pd->hi_addr[i] = -1;
+      pd->to_print_addr = false;
 
       for (i = 0; i < info->symtab_size; i++)
 	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
@@ -668,13 +671,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  print_insn_args (op->args, word, memaddr, info);
 
 	  /* Try to disassemble multi-instruction addressing sequences.  */
-	  if (pd->print_addr != (bfd_vma)-1)
+	  if (pd->to_print_addr)
 	    {
 	      info->target = pd->print_addr;
 	      (*info->fprintf_styled_func)
 		(info->stream, dis_style_comment_start, " # ");
 	      (*info->print_address_func) (info->target, info);
-	      pd->print_addr = -1;
+	      pd->to_print_addr = false;
 	    }
 
 	  /* Finish filling out insn_info fields.  */
-- 
2.34.1

[PATCH v8 5/7] RISC-V: Print top GP-relative addresses on the disassembler

[Tsukasa OI]

This patch makes possible to print the address relative to the global
pointer even if the corresponding symbol is the highest address (0xffffffff
on RV32, 0xffffffff_ffffffff on RV64).

Despite that it is very rare to have GP the highest address, it would be
nice because we enabled highest address printing on regular cases.

opcodes/ChangeLog:

	* riscv-dis.c (struct riscv_private_data): Add `has_gp' to enable
	printing the addresses relative to GP with the highest address.
	(maybe_print_address): Utilize `has_gp'.
	(riscv_disassemble_insn): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-
	relative addressing when GP is the highest address.
	* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
	* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
---
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s    | 15 +++++++++++++++
 opcodes/riscv-dis.c                              | 11 ++++++++---
 4 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
 create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s

diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
new file mode 100644
index 00000000000..875bfe73189
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i
+#source: dis-addr-topaddr-gp.s
+#objdump: -d
+
+.*:     file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0051a283[ 	]+lw[   	]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+ffd1a303[ 	]+lw[   	]+t1,-3\(gp\) # fffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
new file mode 100644
index 00000000000..5ac4b52b18d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i -defsym rv64=1
+#source: dis-addr-topaddr-gp.s
+#objdump: -d
+
+.*:     file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0051a283[ 	]+lw[   	]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ 	]+[0-9a-f]+:[ 	]+ffd1a303[ 	]+lw[   	]+t1,-3\(gp\) # fffffffffffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
new file mode 100644
index 00000000000..6ba9fc7a39d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
@@ -0,0 +1,15 @@
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set __global_pointer$, topbase + 0xffffffff  # -1
+.set addr_rel_gp_pos,             0x00000004  # +4
+.set addr_rel_gp_neg,   topbase + 0xfffffffc  # -4
+
+target:
+	# Use addresses relative to gp
+	# (gp is the highest address)
+	lw	t0, +5(gp)
+	lw	t1, -3(gp)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7532c72187d..160cc40f865 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -53,6 +53,7 @@ struct riscv_private_data
   bfd_vma print_addr;
   bfd_vma hi_addr[OP_MASK_RD + 1];
   bool to_print_addr;
+  bool has_gp;
 };
 
 /* Used for mapping symbols.  */
@@ -178,7 +179,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
       pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
       pd->hi_addr[base_reg] = -1;
     }
-  else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
+  else if (base_reg == X_GP && pd->has_gp)
     pd->print_addr = pd->gp + offset;
   else if (base_reg == X_TP || base_reg == 0)
     pd->print_addr = offset;
@@ -603,15 +604,19 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
       int i;
 
       pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
-      pd->gp = -1;
+      pd->gp = 0;
       pd->print_addr = 0;
       for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
 	pd->hi_addr[i] = -1;
       pd->to_print_addr = false;
+      pd->has_gp = false;
 
       for (i = 0; i < info->symtab_size; i++)
 	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
-	  pd->gp = bfd_asymbol_value (info->symtab[i]);
+	  {
+	    pd->gp = bfd_asymbol_value (info->symtab[i]);
+	    pd->has_gp = true;
+	  }
     }
   else
     pd = info->private_data;
-- 
2.34.1

[PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW

[Tsukasa OI]

The `wide' parameter on the `maybe_print_address' function is only used
for the ADDIW/C.ADDIW instructions and there's no reasonable usecases except
those two.

This commit renames the parameter from `wide' to `is_addiw' to clarify that
this parameter is only used for ADDIW instructions.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Clarify and rename the last
	parameter so that this is only used for ADDIW instructions.
---
 opcodes/riscv-dis.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 160cc40f865..7322db10d24 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
 
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
-		     int wide)
+		     int is_addiw)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -187,8 +187,8 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     return;  /* Don't print the address.  */
   pd->to_print_addr = true;
 
-  /* Sign-extend a 32-bit value to a 64-bit value.  */
-  if (wide)
+  /* On ADDIW, sign-extend a 32-bit value to a 64-bit value.  */
+  if (is_addiw)
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
 
   /* Fit into a 32-bit value on RV32.  */
-- 
2.34.1

[PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool

[Tsukasa OI]

Because we widely use `bool' type, this commit makes this parameter `bool'
in the process of tidying.

opcodes/ChangeLog:

	* riscv-dis.c (maybe_print_address): Change `is_addiw' type from
	`int' to `bool'.  (print_insn_args): Use boolean values.
---
 opcodes/riscv-dis.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7322db10d24..d4c1a5505b1 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
 
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
-		     int is_addiw)
+		     bool is_addiw)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
@@ -243,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'o':
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false);
 	      if (info->mach == bfd_mach_riscv64
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
-		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
+		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true);
 	      print (info->stream, dis_style_immediate, "%d",
 		     (int)EXTRACT_CITYPE_IMM (l));
 	      break;
@@ -406,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	case 'b':
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
 	  break;
 
@@ -436,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  break;
 
 	case 'o':
-	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  /* Fall through.  */
 	case 'j':
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
 	  if (info->mach == bfd_mach_riscv64
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
-	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
+	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true);
 	  print (info->stream, dis_style_immediate, "%d",
 		 (int)EXTRACT_ITYPE_IMM (l));
 	  break;
 
 	case 'q':
-	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
+	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false);
 	  print (info->stream, dis_style_address_offset, "%d",
 		 (int)EXTRACT_STYPE_IMM (l));
 	  break;
-- 
2.34.1

Re: [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler

[Tsukasa OI]

Gahhh... this time, I now have wrong subject lines.
Nothing goes right if I'm in a hurry.

Please consider the base e-mail (with [Changes: v8 -> v9]) as PATCH v9.

Thanks,
Tsukasa

On 2022/08/27 9:22, Tsukasa OI wrote:
> Hello,
> 
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_fix_addr>
> 
> Original Issue as reported by H. Peter Anvin:
> <https://sourceware.org/bugzilla/show_bug.cgi?id=29342>
> 
> Previous Information on v1...v7:
> <https://sourceware.org/pipermail/binutils/2022-August/122552.html>
> See this e-mail for background.
> 
> 
> [Changes: v8 -> v9]
> 
> Sorry! I forgot to remove redundant ChangeLog lines.
> 
> 
> 
> Based on Nelson's feedback, I functionally splitted the patchset to four
> mostly independent parts.  Tests are self-contained to each part (unlike
> dis-addr-2.s in PATCH v7) so that we can review each part independently.
> 
> (1) [PATCH 1-1] Additional tests for existing part: sequence with ADDIW
>                 (because we will test other cases in detail on other parts)
> (2) [PATCH 2-3] Fix to PR29342 and a new JALR issue
>                 (both discovered by H. Peter Anvin)
> (3) [PATCH 4-5] Make the disassembler able to print the highest address
>                 and GP-relative addresses even if the GP is the top addr
> (4) [PATCH 6-7] Code Tidying: Rename and retype `wide' parameter of
>                 `maybe_print_address' for further clarification of the code
> 
> 
> On 2022/08/24 20:22, Nelson Chu wrote:
>> I think there are three dis-assembler issues here,
>>
>> 1. PR29342
>> 2. The target address of jump
>> 3. Should we show the target address when it is -1
> 
> cf. <https://sourceware.org/pipermail/binutils/2022-August/122573.html>
> 
> Based on Nelson's classification, part (2) corresponds [1.] and [2.] and
> (3) corresponds [3.].  About issues [1.] and [2.], PATCH 2 fixes [2.] and
> PATCH 3 fixes [1.] but tests for [2.] is in the PATCH 3 (not PATCH 2).
> 
> This is because PATCH 3 tests address printing in various ways including
> JALR instructions.  So splitting them to PATCH 2 seemed too redundant.
> 
> 
> And, I couldn't come up with a good explanation to `binutils/NEWS'
> describing the changes in the part (3).  Could someone help me?  It enables
> printing following addresses on disassembling:
> 
> -   The highest address (-1)
> -   GP-relative addresses if GP has the highest address (-1)
> 
> 
> 
> [Extraction Guide]
> 
> If we extract each part ((1) through (4)) using git rebase, we may
> encounter some conflicts and test failures.  Even so, to extract (3) and
> (4), I recommend to apply at least (2) through (4) first and then extract
> using git rebase.
> 
> (1)
>     This is completely independent from the rest.
> (2)
>     This is independent from (1).
> (3)
>     This is independent from (1).
>     This is MOSTLY independent from (2) but extracting causes one conflict
>     and two test errors (that depend on the bugfix on (2)):
>         # Conflict: keep those lines
>           else
>             return;  /* Don't print the address.  */
>           pd->to_print_addr = true;
>         # Test Failures: two changes are required to pass check-gas
>             # gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
>                 old: <addr_top>
>                 new: <addr_top\+0x0>
>             # gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
>                 old: <addr_rel_gp_pos>
>                 new: <__global_pointer\$\+0x5>
> (4)
>     This is independent from (1).
>     This is independent from (3).
>     This is MOSTLY independent from (2) but extracting causes one conflict.
>         # Conflict: change like this and keep (to NOT keep the bugfix in (2))
>         old: maybe_print_address (pd, rs1, 0, 0);
>         new: maybe_print_address (pd, rs1, 0, false);
> 
> 
> 
> 
> Tsukasa OI (7):
>   RISC-V: Add address printer tests with ADDIW
>   RISC-V: Fix JALR target address computation
>   RISC-V: Fix RV32 disassembler address computation
>   RISC-V: Print highest address on the disassembler
>   RISC-V: Print top GP-relative addresses on the disassembler
>   RISC-V: Clarify that `wide' is only used for ADDIW
>   RISC-V: Make `is_addiw' parameter bool
> 
>  gas/testsuite/gas/riscv/dis-addr-addiw-a.d    | 18 +++++
>  gas/testsuite/gas/riscv/dis-addr-addiw-b.d    | 18 +++++
>  gas/testsuite/gas/riscv/dis-addr-addiw.s      | 28 ++++++++
>  .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
>  .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
>  gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++
>  .../gas/riscv/dis-addr-topaddr-gp-32.d        | 12 ++++
>  .../gas/riscv/dis-addr-topaddr-gp-64.d        | 12 ++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 15 ++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 +++
>  gas/testsuite/gas/riscv/lla32.d               |  2 +-
>  opcodes/riscv-dis.c                           | 46 +++++++-----
>  14 files changed, 300 insertions(+), 17 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
> 
> 
> base-commit: 46e59b72f21029f2a863e3828cec76a03283b49d

Re: [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler

[Nelson Chu]

Thanks, committed patches 1-5 for pr29342.

Nelson

On Sat, Aug 27, 2022 at 8:11 AM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hello,
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_dis_fix_addr>
>
> Original Issue as reported by H. Peter Anvin:
> <https://sourceware.org/bugzilla/show_bug.cgi?id=29342>
>
> Previous Information on v1...v7:
> <https://sourceware.org/pipermail/binutils/2022-August/122552.html>
> See this e-mail for background.
>
>
>
> Based on Nelson's feedback, I functionally splitted the patchset to four
> mostly independent parts.  Tests are self-contained to each part (unlike
> dis-addr-2.s in PATCH v7) so that we can review each part independently.
>
> (1) [PATCH 1-1] Additional tests for existing part: sequence with ADDIW
>                 (because we will test other cases in detail on other parts)
> (2) [PATCH 2-3] Fix to PR29342 and a new JALR issue
>                 (both discovered by H. Peter Anvin)
> (3) [PATCH 4-5] Make the disassembler able to print the highest address
>                 and GP-relative addresses even if the GP is the top addr
> (4) [PATCH 6-7] Code Tidying: Rename and retype `wide' parameter of
>                 `maybe_print_address' for further clarification of the code
>
>
> On 2022/08/24 20:22, Nelson Chu wrote:
> > I think there are three dis-assembler issues here,
> >
> > 1. PR29342
> > 2. The target address of jump
> > 3. Should we show the target address when it is -1
>
> cf. <https://sourceware.org/pipermail/binutils/2022-August/122573.html>
>
> Based on Nelson's classification, part (2) corresponds [1.] and [2.] and
> (3) corresponds [3.].  About issues [1.] and [2.], PATCH 2 fixes [2.] and
> PATCH 3 fixes [1.] but tests for [2.] is in the PATCH 3 (not PATCH 2).
>
> This is because PATCH 3 tests address printing in various ways including
> JALR instructions.  So splitting them to PATCH 2 seemed too redundant.
>
>
> And, I couldn't come up with a good explanation to `binutils/NEWS'
> describing the changes in the part (3).  Could someone help me?  It enables
> printing following addresses on disassembling:
>
> -   The highest address (-1)
> -   GP-relative addresses if GP has the highest address (-1)
>
>
>
> [Extraction Guide]
>
> If we extract each part ((1) through (4)) using git rebase, we may
> encounter some conflicts and test failures.  Even so, to extract (3) and
> (4), I recommend to apply at least (2) through (4) first and then extract
> using git rebase.
>
> (1)
>     This is completely independent from the rest.
> (2)
>     This is independent from (1).
> (3)
>     This is independent from (1).
>     This is MOSTLY independent from (2) but extracting causes one conflict
>     and two test errors (that depend on the bugfix on (2)):
>         # Conflict: keep those lines
>           else
>             return;  /* Don't print the address.  */
>           pd->to_print_addr = true;
>         # Test Failures: two changes are required to pass check-gas
>             # gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
>                 old: <addr_top>
>                 new: <addr_top\+0x0>
>             # gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
>                 old: <addr_rel_gp_pos>
>                 new: <__global_pointer\$\+0x5>
> (4)
>     This is independent from (1).
>     This is independent from (3).
>     This is MOSTLY independent from (2) but extracting causes one conflict.
>         # Conflict: change like this and keep (to NOT keep the bugfix in (2))
>         old: maybe_print_address (pd, rs1, 0, 0);
>         new: maybe_print_address (pd, rs1, 0, false);
>
>
>
>
> Tsukasa OI (7):
>   RISC-V: Add address printer tests with ADDIW
>   RISC-V: Fix JALR target address computation
>   RISC-V: Fix RV32 disassembler address computation
>   RISC-V: Print highest address on the disassembler
>   RISC-V: Print top GP-relative addresses on the disassembler
>   RISC-V: Clarify that `wide' is only used for ADDIW
>   RISC-V: Make `is_addiw' parameter bool
>
>  gas/testsuite/gas/riscv/dis-addr-addiw-a.d    | 18 +++++
>  gas/testsuite/gas/riscv/dis-addr-addiw-b.d    | 18 +++++
>  gas/testsuite/gas/riscv/dis-addr-addiw.s      | 28 ++++++++
>  .../gas/riscv/dis-addr-overflow-32.d          | 30 ++++++++
>  .../gas/riscv/dis-addr-overflow-64.d          | 34 +++++++++
>  gas/testsuite/gas/riscv/dis-addr-overflow.s   | 70 +++++++++++++++++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-32.d | 11 +++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-64.d | 11 +++
>  .../gas/riscv/dis-addr-topaddr-gp-32.d        | 12 ++++
>  .../gas/riscv/dis-addr-topaddr-gp-64.d        | 12 ++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 15 ++++
>  gas/testsuite/gas/riscv/dis-addr-topaddr.s    | 10 +++
>  gas/testsuite/gas/riscv/lla32.d               |  2 +-
>  opcodes/riscv-dis.c                           | 46 +++++++-----
>  14 files changed, 300 insertions(+), 17 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-a.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw-b.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-addiw.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-overflow.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
>  create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
>
>
> base-commit: 46e59b72f21029f2a863e3828cec76a03283b49d
> --
> 2.34.1
>