* [PATCH 0/9] RISC-V: Combined floating point enhancements
@ 2022-06-02 14:05 Tsukasa OI
2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI
` (9 more replies)
0 siblings, 10 replies; 27+ messages in thread
From: Tsukasa OI @ 2022-06-02 14:05 UTC (permalink / raw)
To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils
PREVIOUS PATCHES:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2)
<https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2)
[Combined Enhancements / Fixes]
0. Proper Zhinx/Zhinxmin support
1. Zfh/Zhinx refactoring / new Zfhmin/Zhinxmin support
<https://sourceware.org/pipermail/binutils/2022-May/120935.html>
<https://sourceware.org/pipermail/binutils/2022-May/120952.html>
2. Zfinx fixes / test enhancements
<https://sourceware.org/pipermail/binutils/2022-February/119570.html>
<https://sourceware.org/pipermail/binutils/2022-February/119576.html>
<https://sourceware.org/pipermail/binutils/2022-May/120940.html>
They are supposed to be separate but involves similar/same locations
that need to be modified. To ease testing and integration to upstream,
I decided to merge those fixes in a single patchset. Of course, I can
split it if requested.
Also in general, I squashed some of fixes/enhancements (spanned in
multiple patches) for simplicity.
As a result, it halved the number of patches (except Zhinx support, that
is new in this version).
Zfh/Zfhmin: 5 -> 3
Zfinx/Zdinx/Zqinx: 11 -> 5
[Details of Changes]
0.1. Add 'H' to canonical extension ordering (PATCH 01)
THIS IS DUPLICATE OF:
<https://sourceware.org/pipermail/binutils/2022-June/121115.html>
To implement Zhinx/Zhinxmin extensions, we have to determine where to
place Zh* extensions. To resolve this problem, I raised an issue on
RISC-V ISA Manual GitHub:
<https://github.com/riscv/riscv-isa-manual/issues/837>
...and we made a consensus. We will put 'H' after 'V'. Considering
compatibility with QEMU and LLVM, we can put 'H' after 'N' (making
'P' -> 'V' -> 'N' -> 'H' canonical ordering for compatibility).
Although this kind of canonical ordering is not ratified yet, it's at
least worth prototyping now.
This makes a difference. On a machine with GPR-FP support for 16, 32
and 64-bit floating point numbers, Jiawei's patch allows:
-march=rv64i_zhinx_zdinx
but my patch allows:
-march=rv64i_zdinx_zhinx
The latter will be canonical. But considering canonical ordering is
too much for regular developers, former should be made valid on future
patches.
1.1. Zfhmin/Zhinxmin subset extension support (PATCH 04)
This patch implements Zfhmin/Zhinxmin extension, conversion-only subset
of Zfh/Zhinx instruction set extensions, respectively.
1.2. [minor] Refactoring for better integration (PATCH 02)
In particular, better integration with F, D and Q. To do that, it
required moving certain macros and constants. But there are no
functional changes. The whole patchset would (and should) work without
this patch.
1.3. [minor] DECLARE_INSN declarations (PATCH 03)
Zfh instructions did not have their own DECLARE_INSN declarations.
PATCH 03 resolves this problem (although not having those is harmless
on current design).
2.1. Disassembler output with Zfinx + -M numeric option (PATCH 05)
Disassembling Zhinx/Zhinxmin/Zfinx/Zdinx/Zqinx instructions with -M
numeric option has an issue. It used ABI names instead of numeric one.
This commit fixes that.
2.2. Enhanced Zfinx/Zdinx/Zqinx testcases (PATCH 06)
I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
patch. I also...
- Made indentation / coding style consistent and clean
- Started to use valid register number (on Zqinx)
- Started to use different register per operand
2.3. Relaxed requirements to fmv.[sdq] instructions (PATCH 07)
On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
On RV32_Zdinx and RV64_Z[dq]inx, it requires register pair. That means,
single...
fmv.d x10, x12
is equivalent to 2 regular instructions on RV32_Zdinx (with 32b GPRs):
mv x10, x12
mv x11, x13
Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of
Z[fdq]inx extensions, it's safe to implement this pseudoinstructions.
PATCH 07 makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
2.4. Validate register pairs on Zdinx/Zqinx (PATCH 08, 09)
For RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must
be even (x0, x2, x4... are valid, x1, x3, x5... are invalid).
For RV32_Zqinx, it would be all registers holding a FP128 value must be
a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
On the other hand, current Binutils can generate invalid instructions
with odd register numbers (or register number x % 4 != 0). PATCH 08
makes those invalid and PATCH 09 adds tests.
Due to complexity, this patch is relatively large.
Tsukasa OI (9):
RISC-V: Add 'H' to canonical extension ordering
RISC-V: Refactor Zfh/Zhinx-related constants
RISC-V: Add instruction declaration for Zfh/Zhinx
RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
RISC-V: Fix disassembling Zfinx with -M numeric
RISC-V: Reorganize and enhance Zfinx tests
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Validate Zdinx/Zqinx register pairs
RISC-V: Add testcases for Z[dq]inx register pairs
bfd/elfxx-riscv.c | 89 ++-
gas/config/tc-riscv.c | 39 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 +++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 27 +-
gas/testsuite/gas/riscv/zdinx.s | 46 +-
.../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail.s | 4 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 +
gas/testsuite/gas/riscv/zfinx.d | 24 +-
gas/testsuite/gas/riscv/zfinx.s | 42 +-
.../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 37 +-
.../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 ++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 ++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 ++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 ++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 86 ++-
gas/testsuite/gas/riscv/zqinx.s | 89 ++-
include/opcode/riscv-opc.h | 180 +++--
include/opcode/riscv.h | 21 +-
opcodes/riscv-dis.c | 2 +-
opcodes/riscv-opc.c | 667 +++++++++++++-----
48 files changed, 2419 insertions(+), 419 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (81%)
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%)
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: 625b6eae091709b95471eae92d42dc6bc71e6553
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI @ 2022-06-02 14:05 ` Tsukasa OI 2022-06-02 14:40 ` Palmer Dabbelt 2022-06-02 14:05 ` [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI ` (8 subsequent siblings) 9 siblings, 1 reply; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:05 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit adds 'H' to canonical extension ordering based on current consensus (not officially ratified as a new ISA specification manual but discussion for software compatibility is made). bfd/ChangeLog * elfxx-riscv.c (riscv_ext_canonical_order): Add 'H' for canonical extension ordering based on current consensus. --- bfd/elfxx-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 92ad03feea0..5c2c616a760 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1345,7 +1345,7 @@ riscv_recognized_prefixed_ext (const char *ext) } /* Canonical order for single letter extensions. */ -static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvn"; +static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvnh"; /* Array is used to compare the orders of standard extensions quickly. */ static int riscv_ext_order[26] = {0}; -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering 2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI @ 2022-06-02 14:40 ` Palmer Dabbelt 2022-06-05 3:57 ` Tsukasa OI 0 siblings, 1 reply; 27+ messages in thread From: Palmer Dabbelt @ 2022-06-02 14:40 UTC (permalink / raw) To: binutils; +Cc: research_trasio, liweiwei, Nelson Chu, kito.cheng, binutils On Thu, 02 Jun 2022 07:05:58 PDT (-0700), binutils@sourceware.org wrote: > This commit adds 'H' to canonical extension ordering based on current > consensus (not officially ratified as a new ISA specification manual > but discussion for software compatibility is made). > > bfd/ChangeLog > > * elfxx-riscv.c (riscv_ext_canonical_order): Add 'H' for > canonical extension ordering based on current consensus. > --- > bfd/elfxx-riscv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 92ad03feea0..5c2c616a760 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1345,7 +1345,7 @@ riscv_recognized_prefixed_ext (const char *ext) > } > > /* Canonical order for single letter extensions. */ > -static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvn"; > +static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvnh"; > > /* Array is used to compare the orders of standard extensions quickly. */ > static int riscv_ext_order[26] = {0}; I forget if this came up elsewhere, but it just did in Linux land. Essenitally we added the hypervisor CSRs/instructions to the base ISA under the assumption that the lack of a letter meant they were in there, but now that there's a letter it's unclear what we should do. Probably we should do the same thing for H that we do for the other ones in flight right now, though. ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering 2022-06-02 14:40 ` Palmer Dabbelt @ 2022-06-05 3:57 ` Tsukasa OI 0 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-05 3:57 UTC (permalink / raw) To: Palmer Dabbelt, binutils; +Cc: liweiwei, Nelson Chu, kito.cheng On 2022/06/02 23:40, Palmer Dabbelt wrote: > On Thu, 02 Jun 2022 07:05:58 PDT (-0700), binutils@sourceware.org wrote: >> This commit adds 'H' to canonical extension ordering based on current >> consensus (not officially ratified as a new ISA specification manual >> but discussion for software compatibility is made). >> >> bfd/ChangeLog >> >> * elfxx-riscv.c (riscv_ext_canonical_order): Add 'H' for >> canonical extension ordering based on current consensus. >> --- >> bfd/elfxx-riscv.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >> index 92ad03feea0..5c2c616a760 100644 >> --- a/bfd/elfxx-riscv.c >> +++ b/bfd/elfxx-riscv.c >> @@ -1345,7 +1345,7 @@ riscv_recognized_prefixed_ext (const char *ext) >> } >> >> /* Canonical order for single letter extensions. */ >> -static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvn"; >> +static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvnh"; >> >> /* Array is used to compare the orders of standard extensions >> quickly. */ >> static int riscv_ext_order[26] = {0}; > > I forget if this came up elsewhere, but it just did in Linux land. > Essenitally we added the hypervisor CSRs/instructions to the base ISA > under the assumption that the lack of a letter meant they were in there, > but now that there's a letter it's unclear what we should do. Probably > we should do the same thing for H that we do for the other ones in > flight right now, though. At least, I think support for Zh* needs this commit. Without that, it causes serious compatibility issues related to canonical ordering (as I outlined in the cover letter). We should temporally remove Zh* extension support (remove Zhinx from the list: riscv_supported_std_z_ext) unless some measure is implemented (not necessarily this patch but I'm sure that this is the simplest). On 2022/06/02 23:05, Tsukasa OI wrote (PATCH 0/9): > This makes a difference. On a machine with GPR-FP support for 16, 32 > and 64-bit floating point numbers, Jiawei's patch allows: > -march=rv64i_zhinx_zdinx > but my patch allows: > -march=rv64i_zdinx_zhinx For 'H', we should probably consider prototyping Binutils + GCC implementation for new extension prefix handling (making 'H' a single-letter extension) before new ISA Manual is released (considering Dr.Waterman's replies, it seems there are some _private_ ISA Manual updates [at least, not on public GitHub repo] underway). I'll try about single-letter 'H'. Thanks, Tsukasa ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI 2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI @ 2022-06-02 14:05 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI ` (7 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:05 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit just moves Zfh/Zhinx-related constants for better integration with other instructions, macros and constants. gas/ChangeLog: * config/tc-riscv.c (macro): Move M_FLH and M_FSH handlings. include/ChangeLog: * opcode/riscv.h (M_FLH, M_FSH): Move around. * opcode/riscv-opc.h (MATCH_FADD_H, MASK_FADD_H, MATCH_FSUB_H, MASK_FSUB_H, MATCH_FMUL_H, MASK_FMUL_H, MATCH_FDIV_H, MASK_FDIV_H, MATCH_FSGNJ_H, MASK_FSGNJ_H, MATCH_FSGNJN_H, MASK_FSGNJN_H, MATCH_FSGNJX_H, MASK_FSGNJX_H, MATCH_FMIN_H, MASK_FMIN_H, MATCH_FMAX_H, MASK_FMAX_H, MATCH_FCVT_H_S, MASK_FCVT_H_S, MATCH_FCVT_S_H, MASK_FCVT_S_H, MATCH_FCVT_H_D, MASK_FCVT_H_D, MATCH_FCVT_D_H, MASK_FCVT_D_H, MATCH_FCVT_H_Q, MASK_FCVT_H_Q, MATCH_FCVT_Q_H, MASK_FCVT_Q_H, MATCH_FSQRT_H, MASK_FSQRT_H, MATCH_FLE_H, MASK_FLE_H, MATCH_FLT_H, MASK_FLT_H, MATCH_FEQ_H, MASK_FEQ_H, MATCH_FCVT_W_H, MASK_FCVT_W_H, MATCH_FCVT_WU_H, MASK_FCVT_WU_H, MATCH_FCVT_L_H, MASK_FCVT_L_H, MATCH_FCVT_LU_H, MASK_FCVT_LU_H, MATCH_FMV_X_H, MASK_FMV_X_H, MATCH_FCLASS_H, MASK_FCLASS_H, MATCH_FCVT_H_W, MASK_FCVT_H_W, MATCH_FCVT_H_WU, MASK_FCVT_H_WU, MATCH_FCVT_H_L, MASK_FCVT_H_L, MATCH_FCVT_H_LU, MASK_FCVT_H_LU, MATCH_FMV_H_X, MASK_FMV_H_X, MATCH_FLH, MASK_FLH, MATCH_FSH, MASK_FSH, MATCH_FMADD_H, MASK_FMADD_H, MATCH_FMSUB_H, MASK_FMSUB_H, MATCH_FNMSUB_H, MASK_FNMSUB_H, MATCH_FNMADD_H, MASK_FNMADD_H): Move around for better integration with other instructions. --- gas/config/tc-riscv.c | 19 ++--- include/opcode/riscv-opc.h | 144 ++++++++++++++++++------------------- include/opcode/riscv.h | 4 +- 3 files changed, 84 insertions(+), 83 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 1b730b4be36..61cf383a9fb 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1843,6 +1843,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; + case M_FLH: + pcrel_load (rd, rs1, imm_expr, "flh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + case M_FLW: pcrel_load (rd, rs1, imm_expr, "flw", BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); @@ -1873,6 +1878,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); break; + case M_FSH: + pcrel_store (rs2, rs1, imm_expr, "fsh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + case M_FSW: pcrel_store (rs2, rs1, imm_expr, "fsw", BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); @@ -1908,15 +1918,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, vector_macro (ip); break; - case M_FLH: - pcrel_load (rd, rs1, imm_expr, "flh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - case M_FSH: - pcrel_store (rs2, rs1, imm_expr, "fsh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - default: as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); break; diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2e867965e12..80e0b44a096 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -267,6 +267,38 @@ #define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 #define MASK_CSRRCI 0x707f +#define MATCH_FADD_H 0x4000053 +#define MASK_FADD_H 0xfe00007f +#define MATCH_FSUB_H 0xc000053 +#define MASK_FSUB_H 0xfe00007f +#define MATCH_FMUL_H 0x14000053 +#define MASK_FMUL_H 0xfe00007f +#define MATCH_FDIV_H 0x1c000053 +#define MASK_FDIV_H 0xfe00007f +#define MATCH_FSGNJ_H 0x24000053 +#define MASK_FSGNJ_H 0xfe00707f +#define MATCH_FSGNJN_H 0x24001053 +#define MASK_FSGNJN_H 0xfe00707f +#define MATCH_FSGNJX_H 0x24002053 +#define MASK_FSGNJX_H 0xfe00707f +#define MATCH_FMIN_H 0x2c000053 +#define MASK_FMIN_H 0xfe00707f +#define MATCH_FMAX_H 0x2c001053 +#define MASK_FMAX_H 0xfe00707f +#define MATCH_FCVT_H_S 0x44000053 +#define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_S_H 0x40200053 +#define MASK_FCVT_S_H 0xfff0007f +#define MATCH_FCVT_H_D 0x44100053 +#define MASK_FCVT_H_D 0xfff0007f +#define MATCH_FCVT_D_H 0x42200053 +#define MASK_FCVT_D_H 0xfff0007f +#define MATCH_FCVT_H_Q 0x44300053 +#define MASK_FCVT_H_Q 0xfff0007f +#define MATCH_FCVT_Q_H 0x46200053 +#define MASK_FCVT_Q_H 0xfff0007f +#define MATCH_FSQRT_H 0x5c000053 +#define MASK_FSQRT_H 0xfff0007f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 @@ -339,6 +371,12 @@ #define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 #define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_H 0xa4000053 +#define MASK_FLE_H 0xfe00707f +#define MATCH_FLT_H 0xa4001053 +#define MASK_FLT_H 0xfe00707f +#define MATCH_FEQ_H 0xa4002053 +#define MASK_FEQ_H 0xfe00707f #define MATCH_FLE_S 0xa0000053 #define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 @@ -357,6 +395,18 @@ #define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 #define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_H 0xc4000053 +#define MASK_FCVT_W_H 0xfff0007f +#define MATCH_FCVT_WU_H 0xc4100053 +#define MASK_FCVT_WU_H 0xfff0007f +#define MATCH_FCVT_L_H 0xc4200053 +#define MASK_FCVT_L_H 0xfff0007f +#define MATCH_FCVT_LU_H 0xc4300053 +#define MASK_FCVT_LU_H 0xfff0007f +#define MATCH_FMV_X_H 0xe4000053 +#define MASK_FMV_X_H 0xfff0707f +#define MATCH_FCLASS_H 0xe4001053 +#define MASK_FCLASS_H 0xfff0707f #define MATCH_FCVT_W_S 0xc0000053 #define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 @@ -391,6 +441,16 @@ #define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FCLASS_Q 0xe6001053 #define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_H_W 0xd4000053 +#define MASK_FCVT_H_W 0xfff0007f +#define MATCH_FCVT_H_WU 0xd4100053 +#define MASK_FCVT_H_WU 0xfff0007f +#define MATCH_FCVT_H_L 0xd4200053 +#define MASK_FCVT_H_L 0xfff0007f +#define MATCH_FCVT_H_LU 0xd4300053 +#define MASK_FCVT_H_LU 0xfff0007f +#define MATCH_FMV_H_X 0xf4000053 +#define MASK_FMV_H_X 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 @@ -517,18 +577,30 @@ #define MASK_BINV 0xfe00707f #define MATCH_BEXT 0x48005033 #define MASK_BEXT 0xfe00707f +#define MATCH_FLH 0x1007 +#define MASK_FLH 0x707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 #define MASK_FLD 0x707f #define MATCH_FLQ 0x4007 #define MASK_FLQ 0x707f +#define MATCH_FSH 0x1027 +#define MASK_FSH 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f #define MATCH_FSD 0x3027 #define MASK_FSD 0x707f #define MATCH_FSQ 0x4027 #define MASK_FSQ 0x707f +#define MATCH_FMADD_H 0x4000043 +#define MASK_FMADD_H 0x600007f +#define MATCH_FMSUB_H 0x4000047 +#define MASK_FMSUB_H 0x600007f +#define MATCH_FNMSUB_H 0x400004b +#define MASK_FNMSUB_H 0x600007f +#define MATCH_FNMADD_H 0x400004f +#define MASK_FNMADD_H 0x600007f #define MATCH_FMADD_S 0x43 #define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 @@ -701,78 +773,6 @@ #define MASK_AES64DSM 0xfe00707f #define MATCH_AES64DS 0x3a000033 #define MASK_AES64DS 0xfe00707f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f #define MATCH_VSETVL 0x80007057 #define MASK_VSETVL 0xfe00707f #define MATCH_VSETIVLI 0xc0007057 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f0beceaec44..1226837be90 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -487,9 +487,11 @@ enum M_SH, M_SW, M_SD, + M_FLH, M_FLW, M_FLD, M_FLQ, + M_FSH, M_FSW, M_FSD, M_FSQ, @@ -502,8 +504,6 @@ enum M_SEXTH, M_VMSGE, M_VMSGEU, - M_FLH, - M_FSH, M_NUM_MACROS }; -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI 2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI 2022-06-02 14:05 ` [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI ` (6 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit adds `DECLARE_INSN' instruction declaration statements for Zfh/Zhinx half-precision floating point instruction extensions. include/ChangeLog: * opcode/riscv-opc.h: Add DECLARE_INSN macros for Zfh/Zhinx instructions. --- include/opcode/riscv-opc.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 80e0b44a096..d51b53cc40b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2585,6 +2585,22 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) +DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) +DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) +DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) +DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) +DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) +DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) +DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) +DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) +DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) +DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) +DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) +DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) +DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) +DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) +DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) @@ -2621,6 +2637,9 @@ DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) +DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) +DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) @@ -2630,6 +2649,12 @@ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) +DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) +DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) +DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) +DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) +DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) @@ -2647,6 +2672,11 @@ DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) +DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) +DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) +DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) +DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) @@ -2706,12 +2736,18 @@ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) +DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) +DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) +DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) +DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (2 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI ` (5 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Add 'Zfhmin' and 'Zhinxmin' extensions. Reorder them for canonical ordering. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Add diagnostics. (riscv_parse_check_conflicts): Change error message to include 'Zfh' and 'Zfhmin' extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Renew instruction classes INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. Remove INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask. --- bfd/elfxx-riscv.c | 79 +++++++---- .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail.s | 4 + .../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 37 ++--- .../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 ++--- include/opcode/riscv.h | 7 +- opcodes/riscv-opc.c | 126 +++++++++--------- 16 files changed, 185 insertions(+), 125 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (81%) rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 5c2c616a760..6dd3e2044a2 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1099,14 +1099,14 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvl128b", "zvl64b", check_implicit_always}, {"zvl64b", "zvl32b", check_implicit_always}, {"d", "f", check_implicit_always}, + {"zfh", "zfhmin", check_implicit_always}, + {"zfhmin", "f", check_implicit_always}, {"f", "zicsr", check_implicit_always}, - {"zfh", "f", check_implicit_always}, - {"zfh", "zicsr", check_implicit_always}, {"zqinx", "zdinx", check_implicit_always}, {"zdinx", "zfinx", check_implicit_always}, + {"zhinx", "zhinxmin", check_implicit_always}, + {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, - {"zhinx", "zfinx", check_implicit_always}, - {"zhinx", "zicsr", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1186,10 +1186,10 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zhinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1225,6 +1225,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zhinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zhinxmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1908,7 +1910,7 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) && riscv_lookup_subset (rps->subset_list, "f", &subset)) { rps->error_handler - (_("`zfinx' is conflict with the `f/d/q' extension")); + (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension")); no_conflict = false; } @@ -2366,19 +2368,24 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_Q_OR_ZQINX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); - case INSN_CLASS_ZFH: - return riscv_subset_supports (rps, "zfh"); case INSN_CLASS_ZFH_OR_ZHINX: - return riscv_subset_supports (rps, "zfh") - || riscv_subset_supports (rps, "zhinx"); - case INSN_CLASS_D_AND_ZFH_INX: - return (riscv_subset_supports (rps, "d") - && riscv_subset_supports (rps, "zfh")) - || riscv_subset_supports (rps, "zhinx"); - case INSN_CLASS_Q_AND_ZFH_INX: - return (riscv_subset_supports (rps, "q") - && riscv_subset_supports (rps, "zfh")) - || riscv_subset_supports (rps, "zhinx"); + return (riscv_subset_supports (rps, "zfh") + || riscv_subset_supports (rps, "zhinx")); + case INSN_CLASS_ZFHMIN: + return riscv_subset_supports (rps, "zfhmin"); + case INSN_CLASS_ZFHMIN_OR_ZHINXMIN: + return (riscv_subset_supports (rps, "zfhmin") + || riscv_subset_supports (rps, "zhinxmin")); + case INSN_CLASS_ZFHMIN_AND_D: + return (riscv_subset_supports (rps, "zfhmin") + && riscv_subset_supports (rps, "d")) + || (riscv_subset_supports (rps, "zhinxmin") + && riscv_subset_supports (rps, "zdinx")); + case INSN_CLASS_ZFHMIN_AND_Q: + return (riscv_subset_supports (rps, "zfhmin") + && riscv_subset_supports (rps, "q")) + || (riscv_subset_supports (rps, "zhinxmin") + && riscv_subset_supports (rps, "zqinx")); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2481,6 +2488,34 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "d' or `zdinx"; case INSN_CLASS_Q_OR_ZQINX: return "q' or `zqinx"; + case INSN_CLASS_ZFH_OR_ZHINX: + return "zfh' or `zhinx"; + case INSN_CLASS_ZFHMIN: + return "zfhmin"; + case INSN_CLASS_ZFHMIN_OR_ZHINXMIN: + return "zfhmin' or `zhinxmin"; + case INSN_CLASS_ZFHMIN_AND_D: + if (riscv_subset_supports (rps, "zfhmin")) + return "d"; + else if (riscv_subset_supports (rps, "d")) + return "zfhmin"; + else if (riscv_subset_supports (rps, "zhinxmin")) + return "zdinx"; + else if (riscv_subset_supports (rps, "zdinx")) + return "zhinxmin"; + else + return "zfhmin' and `d', or `zhinxmin' and `zdinx"; + case INSN_CLASS_ZFHMIN_AND_Q: + if (riscv_subset_supports (rps, "zfhmin")) + return "q"; + else if (riscv_subset_supports (rps, "q")) + return "zfhmin"; + else if (riscv_subset_supports (rps, "zhinxmin")) + return "zqinx"; + else if (riscv_subset_supports (rps, "zqinx")) + return "zhinxmin"; + else + return "zfhmin' and `q', or `zhinxmin' and `zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: @@ -2517,14 +2552,6 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "v' or `zve64d' or `zve64f' or `zve32f"; case INSN_CLASS_SVINVAL: return "svinval"; - case INSN_CLASS_ZFH: - return "zfh"; - case INSN_CLASS_ZFH_OR_ZHINX: - return "zfh' or 'zhinx"; - case INSN_CLASS_D_AND_ZFH_INX: - return "('d' and 'zfh') or 'zhinx"; - case INSN_CLASS_Q_AND_ZFH_INX: - return "('q' and 'zfh') or 'zhinx"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d new file mode 100644 index 00000000000..02a11943cf2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d @@ -0,0 +1,3 @@ +#as: -march=rv64i +#source: zfhmin-d-insn-class-fail.s +#error_output: zfhmin-d-insn-class-fail-1.l diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l new file mode 100644 index 00000000000..12f41a39ae0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d new file mode 100644 index 00000000000..27b5a12857e --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zhinxmin +#source: zfhmin-d-insn-class-fail.s +#error_output: zfhmin-d-insn-class-fail-2.l diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l new file mode 100644 index 00000000000..255f96cb5a1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zdinx' required diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d new file mode 100644 index 00000000000..4f195bfa7c5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zdinx +#source: zfhmin-d-insn-class-fail.s +#error_output: zfhmin-d-insn-class-fail-3.l diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l new file mode 100644 index 00000000000..7ff7b278fe3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zhinxmin' required diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d new file mode 100644 index 00000000000..940d48c5dfd --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zfhmin +#source: zfhmin-d-insn-class-fail.s +#error_output: zfhmin-d-insn-class-fail-4.l diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l new file mode 100644 index 00000000000..2d58e4ce1ce --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `d' required diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d new file mode 100644 index 00000000000..af26d5e9ea7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d @@ -0,0 +1,3 @@ +#as: -march=rv64id +#source: zfhmin-d-insn-class-fail.s +#error_output: zfhmin-d-insn-class-fail-5.l diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l new file mode 100644 index 00000000000..2fa6e8c754b --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' required diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s new file mode 100644 index 00000000000..691d0a929dc --- /dev/null +++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s @@ -0,0 +1,4 @@ +# This test checks error message corresponding required extension(s). +# Operands are invalid on Zhinxmin+Zdinx but they are not parsed since +# extension test fails. +fcvt.d.h fa0, fa1 diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.d b/gas/testsuite/gas/riscv/zhinx.d similarity index 81% rename from gas/testsuite/gas/riscv/fp-zhinx-insns.d rename to gas/testsuite/gas/riscv/zhinx.d index 6e1c40e65f5..eb989148ef2 100644 --- a/gas/testsuite/gas/riscv/fp-zhinx-insns.d +++ b/gas/testsuite/gas/riscv/zhinx.d @@ -1,5 +1,5 @@ -#as: -march=rv64ima_zhinx -#source: fp-zhinx-insns.s +#as: -march=rv64ima_zqinx_zhinx +#source: zhinx.s #objdump: -dr .*:[ ]+file format .* @@ -7,12 +7,7 @@ Disassembly of section .text: -0+000 <.text>: -[ ]+[0-9a-f]+:[ ]+24b59553[ ]+fneg.h[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+24b5a553[ ]+fabs.h[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+24c58553[ ]+fsgnj.h[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+24c59553[ ]+fsgnjn.h[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+24c5a553[ ]+fsgnjx.h[ ]+a0,a1,a2 +0+000 <target>: [ ]+[0-9a-f]+:[ ]+04c5f553[ ]+fadd.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+04c58553[ ]+fadd.h[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0cc5f553[ ]+fsub.h[ ]+a0,a1,a2 @@ -49,18 +44,24 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+d4258553[ ]+fcvt.h.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d435f553[ ]+fcvt.h.lu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d4358553[ ]+fcvt.h.lu[ ]+a0,a1,rne -[ ]+[0-9a-f]+:[ ]+40258553[ ]+fcvt.s.h[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt.d.h[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46258553[ ]+fcvt.q.h[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4405f553[ ]+fcvt.h.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+44058553[ ]+fcvt.h.s[ ]+a0,a1,rne -[ ]+[0-9a-f]+:[ ]+4415f553[ ]+fcvt.h.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+44158553[ ]+fcvt.h.d[ ]+a0,a1,rne -[ ]+[0-9a-f]+:[ ]+4435f553[ ]+fcvt.h.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+44358553[ ]+fcvt.h.q[ ]+a0,a1,rne -[ ]+[0-9a-f]+:[ ]+e4059553[ ]+fclass.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40260553[ ]+fcvt.s.h[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42260553[ ]+fcvt.d.h[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46260553[ ]+fcvt.q.h[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+44067553[ ]+fcvt.h.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+44060553[ ]+fcvt.h.s[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+44167553[ ]+fcvt.h.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+44160553[ ]+fcvt.h.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+44367553[ ]+fcvt.h.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+44360553[ ]+fcvt.h.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+24c58553[ ]+fsgnj.h[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+24c59553[ ]+fsgnjn.h[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+24c5a553[ ]+fsgnjx.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a4c5a553[ ]+feq.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+24b58553[ ]+fmv.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+24b59553[ ]+fneg.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+24b5a553[ ]+fabs.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+e4059553[ ]+fclass.h[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.s b/gas/testsuite/gas/riscv/zhinx.s similarity index 85% rename from gas/testsuite/gas/riscv/fp-zhinx-insns.s rename to gas/testsuite/gas/riscv/zhinx.s index 75e2d5a91b8..05eff34c563 100644 --- a/gas/testsuite/gas/riscv/fp-zhinx-insns.s +++ b/gas/testsuite/gas/riscv/zhinx.s @@ -1,8 +1,4 @@ - fneg.h a0, a1 - fabs.h a0, a1 - fsgnj.h a0, a1, a2 - fsgnjn.h a0, a1, a2 - fsgnjx.h a0, a1, a2 +target: fadd.h a0, a1, a2 fadd.h a0, a1, a2, rne fsub.h a0, a1, a2 @@ -41,19 +37,25 @@ fcvt.h.lu a0, a1 fcvt.h.lu a0, a1, rne - fcvt.s.h a0, a1 - fcvt.d.h a0, a1 - fcvt.q.h a0, a1 - fcvt.h.s a0, a1 - fcvt.h.s a0, a1, rne - fcvt.h.d a0, a1 - fcvt.h.d a0, a1, rne - fcvt.h.q a0, a1 - fcvt.h.q a0, a1, rne - fclass.h a0, a1 + fcvt.s.h a0, a2 + fcvt.d.h a0, a2 + fcvt.q.h a0, a2 + fcvt.h.s a0, a2 + fcvt.h.s a0, a2, rne + fcvt.h.d a0, a2 + fcvt.h.d a0, a2, rne + fcvt.h.q a0, a2 + fcvt.h.q a0, a2, rne + fsgnj.h a0, a1, a2 + fsgnjn.h a0, a1, a2 + fsgnjx.h a0, a1, a2 feq.h a0, a1, a2 flt.h a0, a1, a2 fle.h a0, a1, a2 fgt.h a0, a2, a1 fge.h a0, a2, a1 + fmv.h a0, a1 + fneg.h a0, a1 + fabs.h a0, a1 + fclass.h a0, a1 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 1226837be90..7bdb28192be 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -370,10 +370,11 @@ enum riscv_insn_class INSN_CLASS_F_OR_ZFINX, INSN_CLASS_D_OR_ZDINX, INSN_CLASS_Q_OR_ZQINX, - INSN_CLASS_ZFH, INSN_CLASS_ZFH_OR_ZHINX, - INSN_CLASS_D_AND_ZFH_INX, - INSN_CLASS_Q_AND_ZFH_INX, + INSN_CLASS_ZFHMIN, + INSN_CLASS_ZFHMIN_OR_ZHINXMIN, + INSN_CLASS_ZFHMIN_AND_D, + INSN_CLASS_ZFHMIN_AND_Q, INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6355f8059f5..e52365aab95 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -573,69 +573,69 @@ const struct riscv_opcode riscv_opcodes[] = {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, /* Half-precision floating-point instruction subset. */ -{"flh", 0, INSN_CLASS_ZFH, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE }, -{"flh", 0, INSN_CLASS_ZFH, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO }, -{"fsh", 0, INSN_CLASS_ZFH, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE }, -{"fsh", 0, INSN_CLASS_ZFH, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO }, -{"fmv.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 }, -{"fsgnjn.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 }, -{"fsgnjx.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, -{"fmin.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 }, -{"fmax.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, -{"fcvt.s.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, -{"fcvt.d.h", 0, INSN_CLASS_D_AND_ZFH_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, -{"fcvt.q.h", 0, INSN_CLASS_Q_AND_ZFH_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH_INX, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH_INX, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH_INX, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, -{"fclass.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, -{"feq.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, -{"flt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, -{"fle.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, -{"fgt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, -{"fge.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, -{"fmv.x.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 }, -{"fmv.h.x", 0, INSN_CLASS_ZFH, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, +{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO }, +{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO }, +{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 }, +{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 }, +{"fmv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 }, +{"fsgnjn.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 }, +{"fsgnjx.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 }, +{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 }, +{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, +{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 }, +{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, +{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 }, +{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, +{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 }, +{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, +{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 }, +{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, +{"fmin.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 }, +{"fmax.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 }, +{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 }, +{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, +{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 }, +{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, +{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 }, +{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, +{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 }, +{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, +{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 }, +{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, +{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 }, +{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, +{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 }, +{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, +{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, +{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, +{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, +{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, +{"fclass.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, +{"feq.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, +{"flt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, +{"fle.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, +{"fgt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, +{"fge.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, +{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, +{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, +{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, +{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, +{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, +{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, +{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, +{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, /* Single-precision floating-point instruction subset. */ {"frcsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (3 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI ` (4 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions. --- gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ opcodes/riscv-dis.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d new file mode 100644 index 00000000000..ba3f62295eb --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d @@ -0,0 +1,10 @@ +#as: -march=rv64ima_zfinx +#source: zfinx-dis-numeric.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s new file mode 100644 index 00000000000..b55cbd56b21 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s @@ -0,0 +1,2 @@ +target: + feq.s a0, a1, a2 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 9ff31167775..164fd209dbd 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* If arch has ZFINX flags, use gpr for disassemble. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) { -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (4 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI ` (3 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils, jiawei This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixes coding style. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 23 +++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 ++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 85 ++++++++++++++++++------------- gas/testsuite/gas/riscv/zqinx.s | 88 ++++++++++++++++++++------------- 6 files changed, 208 insertions(+), 100 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..f0b2ca687ee 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -8,26 +8,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +52,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..18a4e17f930 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -8,24 +8,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..f583002db0f 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,37 +7,54 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..8158108230a 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,55 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rne + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rne + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (5 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI ` (2 subsequent siblings) 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit relaxes requirements to `fmv.s' instructions from F to (F or Zfinx). The same applies to `fmv.d' and `fmv.q'. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index f0b2ca687ee..d7db4bfb18b 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -52,6 +52,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index be9a47fa404..3cff27e1458 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -47,6 +47,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 18a4e17f930..8a92fdd7fd3 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -51,6 +51,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 6687f3187ef..327d0228c17 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -45,6 +45,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index f583002db0f..f4d7300fa2e 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -55,6 +55,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 8158108230a..d5ea835498e 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -50,6 +50,7 @@ target: fle.q a0, a2, a4 fgt.q a0, a2, a4 fge.q a0, a2, a4 + fmv.q a0, a2 fneg.q a0, a2 fabs.q a0, a2 fclass.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index e52365aab95..9e9a7307205 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -666,7 +666,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -724,7 +724,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -781,7 +781,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (6 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-06-02 14:06 ` [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit adds floating point register number validation on Zdinx/Zqinx extensions by separating handling on D/Q and Zdinx/Zqinx extensions (per-xlen on Zdinx/Zqinx). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect new instruction classes. (riscv_multi_subset_supports_ext): Reflect new instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZDINX and INSN_CLASS_ZQINX narrow instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new instruction classes, matching functions and the pinfo flag. --- bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 20 +- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 539 +++++++++++++++++++++++++++++++++-------- 4 files changed, 469 insertions(+), 108 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 6dd3e2044a2..b9136198097 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2386,6 +2386,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx")); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2516,6 +2520,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return "zfhmin' and `q', or `zhinxmin' and `zqinx"; + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 61cf383a9fb..015761bcc2c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2260,6 +2260,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2286,8 +2287,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 7bdb28192be..bb05beb6fc6 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,8 +368,10 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, @@ -466,6 +468,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 9e9a7307205..c5f8a843d48 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx register pairs 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (7 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI @ 2022-06-02 14:06 ` Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 9 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-06-02 14:06 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng; +Cc: binutils This commit adds several assembler/disassembler tests for Zdinx/Zqinx register pairs. They make sure that we don't assemble/disassemble invalid encodings. gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 +++++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 21 files changed, 1416 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..aa0c72cae87 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn 0x02627153 + # fadd.d x3, x5, x7 (invalid) + .insn 0x0272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..ce4a8eaa42a --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rne' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rne' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rne' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rne' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rne' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rne' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rne' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rne' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rne' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rne' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..2243d89a6d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rne + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rne + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rne + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rne + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rne + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rne + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rne + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rne + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rne + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rne + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rne + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rne + fsqrt.d a1, a2 + fsqrt.d a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rne + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rne + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rne + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rne + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rne + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rne + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rne + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rne + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rne + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rne + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rne + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rne + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rne + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rne + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rne + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rne + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rne + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rne + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rne + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..eb8aa24b8d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2060553[ ]+fcvt.w.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt.w.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2160553[ ]+fcvt.wu.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt.wu.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40160553[ ]+fcvt.s.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt.s.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..cef479a976e --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rne + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rne + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..e11e671ecdc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn 0x06c47253 + # fadd.q x5, x9, x13 (invalid) + .insn 0x06d4f2d3 + # fadd.q x6, x10, x14 (invalid) + .insn 0x06e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..61afcc84d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rne' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rne' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rne' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rne' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rne' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rne' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rne' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rne' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rne' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rne' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rne' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rne' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rne' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rne' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rne' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rne' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rne' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rne' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rne' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rne' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rne' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rne' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rne' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rne' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..9a1981f3bb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rne + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rne + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rne + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rne + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rne + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rne + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rne + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rne + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rne + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rne + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rne + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rne + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rne + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rne + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rne + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rne + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rne + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rne + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rne + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rne + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rne + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rne + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rne + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rne + fsqrt.q x5, x8 + fsqrt.q x5, x8, rne + fsqrt.q x6, x8 + fsqrt.q x6, x8, rne + fsqrt.q x4, x5 + fsqrt.q x4, x5, rne + fsqrt.q x4, x6 + fsqrt.q x4, x6, rne + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rne + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rne + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rne + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rne + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rne + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rne + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rne + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rne + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rne + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rne + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rne + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rne + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rne + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rne + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rne + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rne + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rne + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rne + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rne + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rne + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rne + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rne + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rne + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rne + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rne + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rne + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rne + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rne + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rne + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rne + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rne + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rne + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rne + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rne + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rne + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rne + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rne + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rne + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rne + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rne + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rne + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..9edeae84ba7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn 0x06627153 + # fadd.q x3, x5, x7 (invalid) + .insn 0x0672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..5a48b7bd22f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rne' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rne' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rne' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rne' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rne' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rne' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rne' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rne' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rne' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rne' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..36680e0c47a --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rne + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rne + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rne + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rne + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rne + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rne + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rne + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rne + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rne + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rne + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rne + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rne + fsqrt.q a1, a2 + fsqrt.q a1, a2, rne + fsqrt.q a0, a1 + fsqrt.q a0, a1, rne + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rne + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rne + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rne + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rne + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rne + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rne + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rne + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rne + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rne + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rne + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rne + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rne + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rne + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rne + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rne + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rne + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rne + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rne + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rne + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rne + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rne + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rne + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rne + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rne + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rne + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rne + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rne + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rne + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rne + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rne + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rne + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..a8db277b8be --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60605d3[ ]+fcvt.w.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61605d3[ ]+fcvt.wu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62605d3[ ]+fcvt.l.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63605d3[ ]+fcvt.lu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403605d3[ ]+fcvt.s.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423605d3[ ]+fcvt.d.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..9d2de327e44 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rne + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rne + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, rne + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rne + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rne + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 0/4] RISC-V: Combined floating point enhancements 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI ` (8 preceding siblings ...) 2022-06-02 14:06 ` [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI @ 2022-07-10 6:36 ` Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI ` (4 more replies) 9 siblings, 5 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-10 6:36 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Before combining patchsets: <https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2) <https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2) Combined v1: <https://sourceware.org/pipermail/binutils/2022-June/121138.html> Combined v2: <https://sourceware.org/pipermail/binutils/2022-June/121441.html> Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined> This is a rebased version for Zfinx-related issues. [Changes: v2 -> v3] - Rebased - Postponed non-functional (coding style-related) changes for another patchset - Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests - Fixed `fcvt.q.l{,u}' instruction match values Tsukasa OI (4): RISC-V: Reorganize and enhance Zfinx tests RISC-V: Relax `fmv.[sdq]' requirements RISC-V: Validate Zdinx/Zqinx register pairs RISC-V: Add testcases for Z[dq]inx register pairs bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ gas/testsuite/gas/riscv/zdinx.d | 27 +- gas/testsuite/gas/riscv/zdinx.s | 46 +- gas/testsuite/gas/riscv/zfinx.d | 24 +- gas/testsuite/gas/riscv/zfinx.s | 42 +- .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ gas/testsuite/gas/riscv/zqinx.d | 86 +-- gas/testsuite/gas/riscv/zqinx.s | 89 +-- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 541 ++++++++++++++---- 31 files changed, 2101 insertions(+), 209 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: eb6dce11fca29245eafdde890dbf46ee2e7661bf -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI @ 2022-07-10 6:36 ` Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI ` (3 subsequent siblings) 4 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-10 6:36 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils, jiawei This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixes coding style. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 23 +++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 ++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 85 ++++++++++++++++++------------- gas/testsuite/gas/riscv/zqinx.s | 88 ++++++++++++++++++++------------- 6 files changed, 208 insertions(+), 100 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..f0b2ca687ee 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -8,26 +8,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +52,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..18a4e17f930 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -8,24 +8,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..f583002db0f 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,37 +7,54 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..8158108230a 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,55 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rne + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rne + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI @ 2022-07-10 6:36 ` Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI ` (2 subsequent siblings) 4 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-10 6:36 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit relaxes requirements to `fmv.s' instructions from F to (F or Zfinx). The same applies to `fmv.d' and `fmv.q'. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index f0b2ca687ee..d7db4bfb18b 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -52,6 +52,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index be9a47fa404..3cff27e1458 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -47,6 +47,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 18a4e17f930..8a92fdd7fd3 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -51,6 +51,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 6687f3187ef..327d0228c17 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -45,6 +45,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index f583002db0f..f4d7300fa2e 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -55,6 +55,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 8158108230a..d5ea835498e 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -50,6 +50,7 @@ target: fle.q a0, a2, a4 fgt.q a0, a2, a4 fge.q a0, a2, a4 + fmv.q a0, a2 fneg.q a0, a2 fabs.q a0, a2 fclass.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2f9945aa930..fc8978cd71a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -666,7 +666,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -724,7 +724,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -781,7 +781,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-07-10 6:36 ` Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 4 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-10 6:36 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit adds floating point register number validation on Zdinx/Zqinx extensions by separating handling on D/Q and Zdinx/Zqinx extensions (per-xlen on Zdinx/Zqinx). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect new instruction classes. (riscv_multi_subset_supports_ext): Reflect new instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZDINX and INSN_CLASS_ZQINX narrow instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new instruction classes, matching functions and the pinfo flag. --- bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 539 +++++++++++++++++++++++++++++++++-------- 4 files changed, 470 insertions(+), 108 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0b2021f5cc7..97e3a8ec7e7 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2356,6 +2356,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2489,6 +2493,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 291d07f6d8f..deaf7fd8e9b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2306,6 +2306,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2332,8 +2333,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + break; + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b115e338a05..9bbeead7b39 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,8 +368,10 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, @@ -467,6 +469,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fc8978cd71a..a0ae0646557 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx register pairs 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI ` (2 preceding siblings ...) 2022-07-10 6:36 ` [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI @ 2022-07-10 6:36 ` Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 4 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-10 6:36 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit adds several assembler/disassembler tests for Zdinx/Zqinx register pairs. They make sure that we don't assemble/disassemble invalid encodings. gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 +++++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 21 files changed, 1416 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..5c28ca7cdc9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn r OP_FP, 0x7, 0x01, x2, x4, x6 + # fadd.d x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x01, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..ce4a8eaa42a --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rne' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rne' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rne' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rne' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rne' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rne' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rne' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rne' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rne' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rne' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..2243d89a6d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rne + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rne + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rne + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rne + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rne + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rne + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rne + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rne + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rne + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rne + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rne + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rne + fsqrt.d a1, a2 + fsqrt.d a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rne + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rne + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rne + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rne + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rne + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rne + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rne + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rne + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rne + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rne + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rne + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rne + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rne + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rne + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rne + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rne + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rne + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rne + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rne + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..eb8aa24b8d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2060553[ ]+fcvt.w.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt.w.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2160553[ ]+fcvt.wu.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt.wu.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40160553[ ]+fcvt.s.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt.s.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..cef479a976e --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rne + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rne + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..c6ce9513175 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn r OP_FP, 0x7, 0x03, x4, x8, x12 + # fadd.q x5, x9, x13 (invalid) + .insn r OP_FP, 0x7, 0x03, x5, x9, x13 + # fadd.q x6, x10, x14 (invalid) + .insn r OP_FP, 0x7, 0x03, x6, x10, x14 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..61afcc84d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rne' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rne' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rne' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rne' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rne' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rne' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rne' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rne' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rne' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rne' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rne' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rne' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rne' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rne' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rne' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rne' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rne' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rne' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rne' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rne' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rne' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rne' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rne' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rne' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..9a1981f3bb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rne + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rne + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rne + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rne + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rne + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rne + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rne + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rne + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rne + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rne + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rne + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rne + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rne + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rne + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rne + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rne + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rne + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rne + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rne + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rne + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rne + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rne + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rne + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rne + fsqrt.q x5, x8 + fsqrt.q x5, x8, rne + fsqrt.q x6, x8 + fsqrt.q x6, x8, rne + fsqrt.q x4, x5 + fsqrt.q x4, x5, rne + fsqrt.q x4, x6 + fsqrt.q x4, x6, rne + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rne + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rne + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rne + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rne + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rne + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rne + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rne + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rne + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rne + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rne + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rne + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rne + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rne + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rne + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rne + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rne + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rne + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rne + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rne + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rne + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rne + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rne + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rne + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rne + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rne + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rne + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rne + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rne + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rne + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rne + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rne + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rne + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rne + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rne + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rne + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rne + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rne + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rne + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rne + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rne + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rne + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..619d0fa4fdb --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn r OP_FP, 0x7, 0x03, x2, x4, x6 + # fadd.q x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x03, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..5a48b7bd22f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rne' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rne' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rne' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rne' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rne' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rne' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rne' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rne' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rne' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rne' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..36680e0c47a --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rne + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rne + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rne + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rne + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rne + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rne + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rne + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rne + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rne + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rne + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rne + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rne + fsqrt.q a1, a2 + fsqrt.q a1, a2, rne + fsqrt.q a0, a1 + fsqrt.q a0, a1, rne + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rne + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rne + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rne + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rne + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rne + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rne + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rne + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rne + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rne + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rne + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rne + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rne + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rne + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rne + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rne + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rne + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rne + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rne + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rne + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rne + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rne + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rne + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rne + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rne + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rne + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rne + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rne + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rne + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rne + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rne + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rne + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..a8db277b8be --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60605d3[ ]+fcvt.w.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61605d3[ ]+fcvt.wu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62605d3[ ]+fcvt.l.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63605d3[ ]+fcvt.lu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403605d3[ ]+fcvt.s.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423605d3[ ]+fcvt.d.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..9d2de327e44 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rne + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rne + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, rne + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rne + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rne + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 0/4] RISC-V: Combined floating point enhancements 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI ` (3 preceding siblings ...) 2022-07-10 6:36 ` [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI @ 2022-07-24 18:58 ` Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI ` (5 more replies) 4 siblings, 6 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-24 18:58 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Before combining patchsets: <https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2) <https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2) Combined v1: <https://sourceware.org/pipermail/binutils/2022-June/121138.html> Combined v2: <https://sourceware.org/pipermail/binutils/2022-June/121441.html> Combined v3: <https://sourceware.org/pipermail/binutils/2022-July/121720.html> Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined> This is a rebased and fixed version for Zfinx-related issues. First, let me recap the changes. 1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/4) I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support patch. I also... - Made indentation / coding style consistent and clean - Started to use valid register number on Zqinx (as I explain below [PATCH 3-4/4]) - Started to use different register per operand 2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/4) On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not. On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. That means, single... fmv.d x10, x12 is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs): mv x10, x12 mv x11, x13 Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx extensions, it's safe to implement this pseudo-instructions. This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments. 3. Validate Register pairs on Zdinx/Zqinx (PATCH 3-4/4) On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would be that all registers holding a FP128 value will be required to have a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not). On RV32_Zdinx, this is valid. fadd.d x10, x12, x14 On the other hand, this is not valid (on RV32_Zdinx). fadd.d x11, x13, x15 Current Binutils can generate invalid instructions with odd register numbers (or register number x % 4 != 0). PATCH 3/4 makes those invalid. Testcases (PATCH 4/4) are separate only because it is quite large. [Changes: v3 -> v4] - Rebased - Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore) Clearly, I forgot to test the patchset. This time, I confirmed that it passes the test. [Changes: v2 -> v3] - Rebased - Postponed non-functional (coding style-related) changes for another patchset - Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests - Fixed `fcvt.q.l{,u}' instruction match values Tsukasa OI (4): RISC-V: Reorganize and enhance Zfinx tests RISC-V: Relax `fmv.[sdq]' requirements RISC-V: Validate Zdinx/Zqinx register pairs RISC-V: Add testcases for Z[dq]inx register pairs bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ gas/testsuite/gas/riscv/zdinx.d | 27 +- gas/testsuite/gas/riscv/zdinx.s | 46 +- gas/testsuite/gas/riscv/zfinx.d | 24 +- gas/testsuite/gas/riscv/zfinx.s | 42 +- .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ gas/testsuite/gas/riscv/zqinx.d | 84 +-- gas/testsuite/gas/riscv/zqinx.s | 87 +-- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 541 ++++++++++++++---- 31 files changed, 2097 insertions(+), 209 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: ea892bdc4b6da5782c6ea6273aff499fb5fd5e6f -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI @ 2022-07-24 18:58 ` Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI ` (4 subsequent siblings) 5 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-24 18:58 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils, jiawei This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixes coding style. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 23 +++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 +++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 83 ++++++++++++++++++------------- gas/testsuite/gas/riscv/zqinx.s | 86 ++++++++++++++++++++------------- 6 files changed, 204 insertions(+), 100 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..f0b2ca687ee 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -8,26 +8,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +52,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..18a4e17f930 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -8,24 +8,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..e11b4ea1361 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,37 +7,52 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..e4244a4277d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,53 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.lu a0, a2 + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI @ 2022-07-24 18:58 ` Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI ` (3 subsequent siblings) 5 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-24 18:58 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit relaxes requirements to `fmv.s' instructions from F to (F or Zfinx). The same applies to `fmv.d' and `fmv.q'. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add `fmv.s' instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add `fmv.d' instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add `fmv.q' instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to `fmv.[sdq]' instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index f0b2ca687ee..d7db4bfb18b 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -52,6 +52,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index be9a47fa404..3cff27e1458 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -47,6 +47,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 18a4e17f930..8a92fdd7fd3 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -51,6 +51,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 6687f3187ef..327d0228c17 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -45,6 +45,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index e11b4ea1361..e0725e848da 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -53,6 +53,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index e4244a4277d..84d045feb4d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -48,6 +48,7 @@ target: fle.q a0, a2, a4 fgt.q a0, a2, a4 fge.q a0, a2, a4 + fmv.q a0, a2 fneg.q a0, a2 fabs.q a0, a2 fclass.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2f9945aa930..fc8978cd71a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -666,7 +666,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -724,7 +724,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -781,7 +781,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI @ 2022-07-24 18:58 ` Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI ` (2 subsequent siblings) 5 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-24 18:58 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit adds floating point register number validation on Zdinx/Zqinx extensions by separating handling on D/Q and Zdinx/Zqinx extensions (per-xlen on Zdinx/Zqinx). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect new instruction classes. (riscv_multi_subset_supports_ext): Reflect new instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZDINX and INSN_CLASS_ZQINX narrow instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new instruction classes, matching functions and the pinfo flag. --- bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 539 +++++++++++++++++++++++++++++++++-------- 4 files changed, 470 insertions(+), 108 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0b2021f5cc7..97e3a8ec7e7 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2356,6 +2356,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2489,6 +2493,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 291d07f6d8f..deaf7fd8e9b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2306,6 +2306,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2332,8 +2333,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + break; + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b115e338a05..9bbeead7b39 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -368,8 +368,10 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, @@ -467,6 +469,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fc8978cd71a..a0ae0646557 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx register pairs 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI ` (2 preceding siblings ...) 2022-07-24 18:58 ` [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI @ 2022-07-24 18:58 ` Tsukasa OI 2022-07-30 3:21 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI 5 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-24 18:58 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit adds several assembler/disassembler tests for Zdinx/Zqinx register pairs. They make sure that we don't assemble/disassemble invalid encodings. gas/ChangeLog: * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 +++++++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++++++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 +++++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 21 files changed, 1416 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..5c28ca7cdc9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn r OP_FP, 0x7, 0x01, x2, x4, x6 + # fadd.d x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x01, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..ce4a8eaa42a --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rne' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rne' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rne' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rne' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rne' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rne' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rne' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rne' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rne' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rne' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..2243d89a6d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rne + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rne + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rne + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rne + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rne + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rne + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rne + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rne + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rne + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rne + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rne + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rne + fsqrt.d a1, a2 + fsqrt.d a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rne + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rne + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rne + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rne + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rne + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rne + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rne + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rne + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rne + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rne + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rne + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rne + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rne + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rne + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rne + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rne + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rne + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rne + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rne + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..eb8aa24b8d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2060553[ ]+fcvt.w.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt.w.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2160553[ ]+fcvt.wu.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt.wu.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40160553[ ]+fcvt.s.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt.s.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..cef479a976e --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rne + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rne + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..c6ce9513175 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn r OP_FP, 0x7, 0x03, x4, x8, x12 + # fadd.q x5, x9, x13 (invalid) + .insn r OP_FP, 0x7, 0x03, x5, x9, x13 + # fadd.q x6, x10, x14 (invalid) + .insn r OP_FP, 0x7, 0x03, x6, x10, x14 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..61afcc84d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rne' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rne' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rne' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rne' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rne' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rne' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rne' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rne' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rne' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rne' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rne' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rne' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rne' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rne' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rne' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rne' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rne' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rne' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rne' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rne' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rne' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rne' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rne' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rne' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..9a1981f3bb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rne + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rne + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rne + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rne + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rne + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rne + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rne + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rne + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rne + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rne + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rne + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rne + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rne + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rne + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rne + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rne + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rne + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rne + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rne + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rne + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rne + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rne + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rne + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rne + fsqrt.q x5, x8 + fsqrt.q x5, x8, rne + fsqrt.q x6, x8 + fsqrt.q x6, x8, rne + fsqrt.q x4, x5 + fsqrt.q x4, x5, rne + fsqrt.q x4, x6 + fsqrt.q x4, x6, rne + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rne + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rne + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rne + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rne + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rne + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rne + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rne + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rne + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rne + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rne + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rne + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rne + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rne + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rne + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rne + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rne + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rne + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rne + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rne + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rne + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rne + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rne + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rne + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rne + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rne + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rne + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rne + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rne + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rne + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rne + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rne + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rne + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rne + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rne + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rne + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rne + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rne + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rne + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rne + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rne + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rne + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..619d0fa4fdb --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn r OP_FP, 0x7, 0x03, x2, x4, x6 + # fadd.q x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x03, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..5a48b7bd22f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rne' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rne' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rne' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rne' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rne' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rne' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rne' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rne' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rne' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rne' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..36680e0c47a --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rne + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rne + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rne + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rne + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rne + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rne + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rne + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rne + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rne + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rne + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rne + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rne + fsqrt.q a1, a2 + fsqrt.q a1, a2, rne + fsqrt.q a0, a1 + fsqrt.q a0, a1, rne + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rne + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rne + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rne + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rne + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rne + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rne + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rne + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rne + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rne + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rne + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rne + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rne + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rne + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rne + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rne + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rne + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rne + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rne + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rne + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rne + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rne + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rne + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rne + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rne + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rne + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rne + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rne + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rne + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rne + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rne + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rne + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..d62c17ffe46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60605d3[ ]+fcvt.w.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61605d3[ ]+fcvt.wu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62605d3[ ]+fcvt.l.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63605d3[ ]+fcvt.lu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403605d3[ ]+fcvt.s.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423605d3[ ]+fcvt.d.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..abb6dbd9258 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rne + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, dyn + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, dyn + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, dyn + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, dyn + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rne + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v4 0/4] RISC-V: Combined floating point enhancements 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI ` (3 preceding siblings ...) 2022-07-24 18:58 ` [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI @ 2022-07-30 3:21 ` Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI 5 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-07-30 3:21 UTC (permalink / raw) To: Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Additional Report - Support on LLVM: Functional differences between my patchset and the latest LLVM is whether requirements to "fmv.[sdq]" instructions are relaxed. As I noted earlier, supporting "fmv.[sdq]" on Zfinx environment seems more natural. Register pairs of RV32_Zdinx (note that LLVM does not support Zqinx) are supported on LLVM >= 14. See GPRPF64 for register pairs on LLVM. In fact, all zdinx-32-regpair-fail.s testcases generated errors (total: 110) and zdinx-32-regpair.s only generated one compiler error ("fmv.d" is not supported on LLVM but this is not related to register pairs). Recap - Existing Reviews: Although that the patchset itself changes multiple times, its functionality is mostly reviewed. It's nearly 6 months ago so it's not a bad timing to remind you all. Relaxing fmv.[sdq] requirements (PATCH 2/4): - <https://sourceware.org/pipermail/binutils/2022-February/119677.html> Reviewed by Palmer Dabbelt Zfinx register pairs (PATCH 3/4): - <https://sourceware.org/pipermail/binutils/2022-February/119679.html> This is when I had two ideas to fix this issue but the version I implemented in combined patchset v4 seems fine to Palmer. Note that there's no "Reviewed-by" tag, though. I hope they are useful to review my changes. On 2022/07/25 3:58, Tsukasa OI wrote: > Before combining patchsets: > <https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2) > <https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2) > Combined v1: > <https://sourceware.org/pipermail/binutils/2022-June/121138.html> > Combined v2: > <https://sourceware.org/pipermail/binutils/2022-June/121441.html> > Combined v3: > <https://sourceware.org/pipermail/binutils/2022-July/121720.html> > > Tracker on GitHub: > <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined> > > This is a rebased and fixed version for Zfinx-related issues. > > First, let me recap the changes. > > > > > 1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/4) > > I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support > patch. I also... > > - Made indentation / coding style consistent and clean > - Started to use valid register number on Zqinx > (as I explain below [PATCH 3-4/4]) > - Started to use different register per operand > > > 2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/4) > > On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not. > On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. > > That means, single... > fmv.d x10, x12 > is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs): > mv x10, x12 > mv x11, x13 > > Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx > extensions, it's safe to implement this pseudo-instructions. > > This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments. > > > 3. Validate Register pairs on Zdinx/Zqinx (PATCH 3-4/4) > > On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even > (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would > be that all registers holding a FP128 value will be required to have a multiple > of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not). > > On RV32_Zdinx, this is valid. > fadd.d x10, x12, x14 > On the other hand, this is not valid (on RV32_Zdinx). > fadd.d x11, x13, x15 > > Current Binutils can generate invalid instructions with odd register numbers > (or register number x % 4 != 0). PATCH 3/4 makes those invalid. > > Testcases (PATCH 4/4) are separate only because it is quite large. > > > > > [Changes: v3 -> v4] > > - Rebased > - Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore) > Clearly, I forgot to test the patchset. > This time, I confirmed that it passes the test. > > > [Changes: v2 -> v3] > > - Rebased > - Postponed non-functional (coding style-related) changes > for another patchset > - Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests > - Fixed `fcvt.q.l{,u}' instruction match values > > > > > Tsukasa OI (4): > RISC-V: Reorganize and enhance Zfinx tests > RISC-V: Relax `fmv.[sdq]' requirements > RISC-V: Validate Zdinx/Zqinx register pairs > RISC-V: Add testcases for Z[dq]inx register pairs > > bfd/elfxx-riscv.c | 8 + > gas/config/tc-riscv.c | 21 +- > .../gas/riscv/zdinx-32-regpair-dis.d | 11 + > .../gas/riscv/zdinx-32-regpair-dis.s | 5 + > .../gas/riscv/zdinx-32-regpair-fail.d | 3 + > .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ > .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ > gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ > gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ > gas/testsuite/gas/riscv/zdinx.d | 27 +- > gas/testsuite/gas/riscv/zdinx.s | 46 +- > gas/testsuite/gas/riscv/zfinx.d | 24 +- > gas/testsuite/gas/riscv/zfinx.s | 42 +- > .../gas/riscv/zqinx-32-regpair-dis.d | 12 + > .../gas/riscv/zqinx-32-regpair-dis.s | 7 + > .../gas/riscv/zqinx-32-regpair-fail.d | 3 + > .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ > .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ > gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ > gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ > .../gas/riscv/zqinx-64-regpair-dis.d | 11 + > .../gas/riscv/zqinx-64-regpair-dis.s | 5 + > .../gas/riscv/zqinx-64-regpair-fail.d | 3 + > .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ > .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ > gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ > gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ > gas/testsuite/gas/riscv/zqinx.d | 84 +-- > gas/testsuite/gas/riscv/zqinx.s | 87 +-- > include/opcode/riscv.h | 10 +- > opcodes/riscv-opc.c | 541 ++++++++++++++---- > 31 files changed, 2097 insertions(+), 209 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d > create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s > > > base-commit: ea892bdc4b6da5782c6ea6273aff499fb5fd5e6f ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI ` (4 preceding siblings ...) 2022-07-30 3:21 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI @ 2022-09-04 7:06 ` Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI ` (2 more replies) 5 siblings, 3 replies; 27+ messages in thread From: Tsukasa OI @ 2022-09-04 7:06 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Hello, Combined v4: <https://sourceware.org/pipermail/binutils/2022-July/121981.html> Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined> This is a rebased and fixed version for Zfinx-related issues. **************************************************************************** I consider this the most important Binutils patchset submitted by me since the current GAS allows emitting invalid instructions. This is almost RESEND but with commit messages and commit squashing. **************************************************************************** Let me recap the changes (again). 1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/3) I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support patch. I also... - Made indentation / coding style consistent and clean - Started to use valid register number on Zqinx (as I explain below [PATCH 3/3]) - Started to use different register per operand 2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/3) On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not. On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. That means, single... fmv.d x10, x12 is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs): mv x10, x12 mv x11, x13 Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx extensions, it's safe to implement this pseudo-instructions. This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments. **************************************************************************** Note that this is consistent with Zhinx changes since fmv.h already requires ('Zfh' or 'Zhinx'), not 'Zfh' only. **************************************************************************** 3. Validate Register pairs on Zdinx/Zqinx (PATCH 3/3) On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would be that all registers holding a FP128 value will be required to have a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not). On RV32_Zdinx, this is valid. fadd.d x10, x12, x14 On the other hand, this is not valid (on RV32_Zdinx). fadd.d x11, x13, x15 Current Binutils can generate invalid instructions with odd register numbers (or register number x % 4 != 0). PATCH 3/3 makes those invalid. **************************************************************************** This patch fixes the problem which allows emitting invalid instructions. **************************************************************************** [Changes: v4 -> v5] - Rebased - Squashed (PATCH 3-4/4 to PATCH 3/3) - Commit messages are refined [Changes: v3 -> v4] - Rebased - Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore) Clearly, I forgot to test the patchset. This time, I confirmed that it passes the test. [Changes: v2 -> v3] - Rebased - Postponed non-functional (coding style-related) changes for another patchset - Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests - Fixed `fcvt.q.l{,u}' instruction match values Tsukasa OI (3): RISC-V: Reorganize and enhance Zfinx tests RISC-V: Relax fmv.[sdq] requirements RISC-V: Validate Zdinx/Zqinx register pairs bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ gas/testsuite/gas/riscv/zdinx.d | 27 +- gas/testsuite/gas/riscv/zdinx.s | 46 +- gas/testsuite/gas/riscv/zfinx.d | 24 +- gas/testsuite/gas/riscv/zfinx.s | 42 +- .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ gas/testsuite/gas/riscv/zqinx.d | 84 +-- gas/testsuite/gas/riscv/zqinx.s | 87 +-- include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 541 ++++++++++++++---- 31 files changed, 2097 insertions(+), 209 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s base-commit: 148b68a56c57d69bd97a5f40c34fc4700693596a -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI @ 2022-09-04 7:06 ` Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-09-04 7:06 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils, jiawei This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixing coding style while improving coverage. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 23 +++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 +++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 83 ++++++++++++++++++------------- gas/testsuite/gas/riscv/zqinx.s | 86 ++++++++++++++++++++------------- 6 files changed, 204 insertions(+), 100 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..f0b2ca687ee 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -8,26 +8,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +52,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..18a4e17f930 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -8,24 +8,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..e11b4ea1361 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,37 +7,52 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..e4244a4277d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,53 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.lu a0, a2 + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI @ 2022-09-04 7:06 ` Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-09-04 7:06 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit relaxes requirements to fmv.s instructions from 'F' to ('F' or 'Zfinx'). The same applies to fmv.d and fmv.q. Note that 'Zhinx' extension already contains fmv.h instruction (as well as 'Zfh'). gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add fmv.s instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add fmv.d instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add fmv.q instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to fmv.[sdq] instructions to support those in Zfinx/Zdinx/Zqinx. --- gas/testsuite/gas/riscv/zdinx.d | 1 + gas/testsuite/gas/riscv/zdinx.s | 1 + gas/testsuite/gas/riscv/zfinx.d | 1 + gas/testsuite/gas/riscv/zfinx.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 1 + gas/testsuite/gas/riscv/zqinx.s | 1 + opcodes/riscv-opc.c | 6 +++--- 7 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index f0b2ca687ee..d7db4bfb18b 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -52,6 +52,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index be9a47fa404..3cff27e1458 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -47,6 +47,7 @@ target: fle.d a0, a1, a2 fgt.d a0, a1, a2 fge.d a0, a1, a2 + fmv.d a0, a1 fneg.d a0, a1 fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index 18a4e17f930..8a92fdd7fd3 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -51,6 +51,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 +[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index 6687f3187ef..327d0228c17 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -45,6 +45,7 @@ target: fle.s a0, a1, a2 fgt.s a0, a1, a2 fge.s a0, a1, a2 + fmv.s a0, a1 fneg.s a0, a1 fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index e11b4ea1361..e0725e848da 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -53,6 +53,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 [ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 [ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index e4244a4277d..84d045feb4d 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -48,6 +48,7 @@ target: fle.q a0, a2, a4 fgt.q a0, a2, a4 fge.q a0, a2, a4 + fmv.q a0, a2 fneg.q a0, a2 fabs.q a0, a2 fclass.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 79be78eb367..fda2fb8d68a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -666,7 +666,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, @@ -724,7 +724,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, @@ -781,7 +781,7 @@ const struct riscv_opcode riscv_opcodes[] = {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, {"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements Tsukasa OI @ 2022-09-04 7:06 ` Tsukasa OI 2 siblings, 0 replies; 27+ messages in thread From: Tsukasa OI @ 2022-09-04 7:06 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This commit adds floating point register number validation on 'Zdinx'/'Zqinx' extensions by separating handling on 'D'/'Q' and 'Zdinx' /'Zqinx' extensions (per-xlen on 'Zdinx'/'Zqinx'). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect new instruction classes. (riscv_multi_subset_supports_ext): Reflect new instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZDINX and INSN_CLASS_ZQINX narrow instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new instruction classes, matching functions and the pinfo flag. --- bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 539 ++++++++++++++---- 25 files changed, 1886 insertions(+), 108 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8cb3c8d4930..b6c2eb9fe50 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2469,6 +2473,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 34ce68e8252..56b4242b101 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2306,6 +2306,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2332,8 +2333,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + break; + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..5c28ca7cdc9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn r OP_FP, 0x7, 0x01, x2, x4, x6 + # fadd.d x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x01, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..ce4a8eaa42a --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rne' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rne' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rne' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rne' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rne' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rne' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rne' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rne' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rne' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rne' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..2243d89a6d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rne + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rne + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rne + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rne + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rne + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rne + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rne + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rne + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rne + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rne + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rne + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rne + fsqrt.d a1, a2 + fsqrt.d a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rne + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rne + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rne + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rne + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rne + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rne + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rne + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rne + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rne + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rne + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rne + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rne + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rne + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rne + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rne + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rne + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rne + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rne + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rne + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..eb8aa24b8d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2060553[ ]+fcvt.w.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt.w.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2160553[ ]+fcvt.wu.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt.wu.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40160553[ ]+fcvt.s.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt.s.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..cef479a976e --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rne + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rne + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..c6ce9513175 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn r OP_FP, 0x7, 0x03, x4, x8, x12 + # fadd.q x5, x9, x13 (invalid) + .insn r OP_FP, 0x7, 0x03, x5, x9, x13 + # fadd.q x6, x10, x14 (invalid) + .insn r OP_FP, 0x7, 0x03, x6, x10, x14 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..61afcc84d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rne' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rne' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rne' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rne' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rne' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rne' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rne' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rne' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rne' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rne' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rne' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rne' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rne' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rne' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rne' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rne' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rne' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rne' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rne' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rne' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rne' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rne' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rne' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rne' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..9a1981f3bb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rne + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rne + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rne + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rne + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rne + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rne + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rne + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rne + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rne + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rne + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rne + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rne + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rne + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rne + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rne + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rne + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rne + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rne + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rne + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rne + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rne + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rne + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rne + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rne + fsqrt.q x5, x8 + fsqrt.q x5, x8, rne + fsqrt.q x6, x8 + fsqrt.q x6, x8, rne + fsqrt.q x4, x5 + fsqrt.q x4, x5, rne + fsqrt.q x4, x6 + fsqrt.q x4, x6, rne + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rne + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rne + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rne + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rne + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rne + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rne + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rne + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rne + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rne + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rne + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rne + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rne + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rne + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rne + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rne + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rne + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rne + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rne + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rne + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rne + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rne + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rne + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rne + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rne + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rne + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rne + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rne + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rne + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rne + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rne + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rne + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rne + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rne + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rne + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rne + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rne + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rne + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rne + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rne + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rne + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rne + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..619d0fa4fdb --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn r OP_FP, 0x7, 0x03, x2, x4, x6 + # fadd.q x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x03, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..5a48b7bd22f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rne' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rne' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rne' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rne' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rne' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rne' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rne' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rne' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rne' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rne' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..36680e0c47a --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rne + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rne + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rne + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rne + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rne + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rne + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rne + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rne + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rne + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rne + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rne + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rne + fsqrt.q a1, a2 + fsqrt.q a1, a2, rne + fsqrt.q a0, a1 + fsqrt.q a0, a1, rne + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rne + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rne + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rne + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rne + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rne + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rne + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rne + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rne + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rne + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rne + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rne + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rne + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rne + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rne + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rne + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rne + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rne + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rne + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rne + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rne + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rne + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rne + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rne + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rne + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rne + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rne + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rne + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rne + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rne + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rne + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rne + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..d62c17ffe46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60605d3[ ]+fcvt.w.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61605d3[ ]+fcvt.wu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62605d3[ ]+fcvt.l.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63605d3[ ]+fcvt.lu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403605d3[ ]+fcvt.s.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423605d3[ ]+fcvt.d.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..abb6dbd9258 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rne + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, dyn + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, dyn + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, dyn + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, dyn + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rne + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f1dabeaab8e..db881831ff9 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -369,8 +369,10 @@ enum riscv_insn_class INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, @@ -468,6 +470,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fda2fb8d68a..f2d8dacbf89 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1 ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2022-09-04 7:07 UTC | newest] Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-06-02 14:05 [PATCH 0/9] RISC-V: Combined floating point enhancements Tsukasa OI 2022-06-02 14:05 ` [PATCH 1/9] RISC-V: Add 'H' to canonical extension ordering Tsukasa OI 2022-06-02 14:40 ` Palmer Dabbelt 2022-06-05 3:57 ` Tsukasa OI 2022-06-02 14:05 ` [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI 2022-06-02 14:06 ` [PATCH 3/9] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI 2022-06-02 14:06 ` [PATCH 4/9] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI 2022-06-02 14:06 ` [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI 2022-06-02 14:06 ` [PATCH 6/9] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-06-02 14:06 ` [PATCH 7/9] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI 2022-06-02 14:06 ` [PATCH 8/9] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-06-02 14:06 ` [PATCH 9/9] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-07-10 6:36 ` [PATCH v3 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 1/4] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 2/4] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 3/4] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI 2022-07-24 18:58 ` [PATCH v4 4/4] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI 2022-07-30 3:21 ` [PATCH v4 0/4] RISC-V: Combined floating point enhancements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 0/3] RISC-V: Combined floating point (Zfinx-related) enhancements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 1/3] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 2/3] RISC-V: Relax fmv.[sdq] requirements Tsukasa OI 2022-09-04 7:06 ` [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).