Help needed for porting opcodes for CISC architecture

Help needed for porting opcodes for CISC architecture

[Usha Gupta]

Hi All ,

I am  new to CGEN and want to port binutils for a CISC  architecture
wherein the instruction length can vary from 1 byte to a maximum of
5-bytes.

I am having trouble porting opcodes using CGEN.

I have defined various hardware elements and instruction fields.

I am not sure what should be the values of

(default-insn-bitsize 8)
(base-insn-bitsize 16)
(default-insn-word-bitsize 16 )
(word-bitsize 16 )

As mentioned in the CGEN manual, I specified default-insn bitsize  as
8 (smallest instruction length) and rest of the values as 16 ( word
length is 2 bytes).

This works for 16-bit instructions where both the operands are
explicit in the instruction encoding.

Another important thing to mention here is that the machine does not
have a fixed length opcode.

Here are some of the instruction formats :

1-byte instruction:
1)      IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
the operand is fixed register, implied from the opcode)
2)      IIIddddd - 3 bits opcode, 5 bit displacement


2-byte instruction:
1)      IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register  operand
(source), 5-bit opcode, 3-bit register operand (destination)

How do I define  instructions of varying length?

Any help is appreciated.

Thanks and Regards,
Usha Gupta

Re: Help needed for porting opcodes for CISC architecture

[Frank Ch. Eigler]

Usha Gupta <usha.nitt@gmail.com> writes:

> [...]
> (default-insn-bitsize 8)
> (base-insn-bitsize 16)
> (default-insn-word-bitsize 16 )
> (word-bitsize 16 )

OK (though you might need to raise base-insn-bitsize).

> [...]
> Here are some of the instruction formats :
>
> 1-byte instruction:
> 1)      IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
> the operand is fixed register, implied from the opcode)
> 2)      IIIddddd - 3 bits opcode, 5 bit displacement
>
> 2-byte instruction:
> 1)      IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register  operand
> (source), 5-bit opcode, 3-bit register operand (destination)
>
> How do I define  instructions of varying length?

Presumably those IIIII's don't overlap - i.e., the hardware can tell
from the first byte that it's a 2-byte instruction (and more opcode
bits need to be fetched).  In cgen, instruction opcodes need not be
single fields nor contiguous; just specify one ifield per unique
opcode piece.

- FChE

Re: Help needed for porting opcodes for CISC architecture

[Usha Gupta]

Thanks Frank.

I have got instructions upto 4 bytes being correctly assembled.

I was initially using simplification macro "dnf " for defining
instruction fields which does not allows specifying word-length and
word-offset.
The problem is resolved by specifying instruction fields using
define-ifield where I could define the total length of the instruction
where this specific instruction field is used .

For 5-byte  insns, since opcode  doesn't fit in CGEN_INSN_INT which is
defined in include/opcode/cgen.h as unsigned int , I changed it to
"unsigned long long". Is there a cleaner way to achieve this?
The instructions seem to get assembled but the bytes are not arranged
in the correct order (as defined by the instruction fields used).

Say I have an 16-bit unsigned immediate xy and a 8-bit signed
immediate n and my instruction format looks like this
0--7     8---------15  16-------23    24--31  32---------39
IIIIIIII    yyyyyyyy   xxxxxxxx     IIIIIIII     nnnnnnnn

I have defined instruction fields as
f-op1- 0,8 (0-7 bits)
f-op2 - 24,8 (24-31 bits)
f-uimm16 - 8,16 (8-23 bits)
f-simm8 - 32,8 (32-39 bits)

On seeing  the disassembly, I find that both the opcodes are placed
contiguously (in 0-15 bits) and also the hi8 of 16-bit unsigned
immediate is filled with junk value.
Similar issue is seen when 16 bit immediate value is used in 24/32 bit
insns. Target is little-endian (in case that matters here).
Am I doing something wrong here?

> Presumably those IIIII's don't overlap - i.e., the hardware can tell
> from the first byte that it's a 2-byte instruction (and more opcode
> bits need to be fetched).  In cgen, instruction opcodes need not be
> single fields nor contiguous; just specify one ifield per unique
> opcode piece.

Following example shows instruction formats with overlap
1-byte instruction:
 IIIIIrrr - 5 bits opcode , 3 bits for register operand

2-byte instruction:
 IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register  operand (source),
5-bit opcode, 3-bit register operand (destination)

I could not find a common bit pattern to identify the insn length. Can
this be handled using CGEN?

Thanks in advance.

Regards,
Usha Gupta