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* STM32F107 on STM3210C-EVAL
@ 2011-03-22 19:15 Gian Maria
  2011-03-23 10:51 ` John Dallaway
  2011-03-28  9:55 ` qber_
  0 siblings, 2 replies; 9+ messages in thread
From: Gian Maria @ 2011-03-22 19:15 UTC (permalink / raw)
  To: ecos-devel

I'm porting eCos to STM3210C and I find a logical error on the
implementation of CYGPKG_HAL_CORTEXM_STM32.
CYGPKG_HAL_CORTEXM_STM32 must be the base of all STM32 uP and so is not
correct for me to use

    cdl_option CYGHWR_HAL_CORTEXM_STM32 {
        display          "STM32 variant in use"
        flavor           data
        default_value    {"F103ZE"}
        legal_values     {"F103RC" "F103VC" "F103ZC"
                          "F103RD" "F103VD" "F103ZD"
                          "F103RE" "F103VE" "F103ZE" }
        description      "The STM32 has several variants, the main
                          being in the size of on-chip FLASH and SRAM
                          and numbers of some peripherals. This option
                          allows the platform HAL to select the specific
                          microcontroller fitted."

That is inside "ecoscvs\ecos\packages\hal\cortexm\stm32\var\current\cdl",
because with my EVB for example 
the uP is a STM32F107VC. With this I can't set the right uP as default for
the template.
I'm right? I think the correct is to put the code inside

Can someone modify this so I can update my CVS and work with the right code?

Best regards Gisn.

1 - When I finish my piece of port, that is at the beginning and I'm
learning eCos who can upload?
2 - For every suggest Is this the right place?
3 - I have to post the full port or can post pieces of code as they are

^ permalink raw reply	[flat|nested] 9+ messages in thread
* RE: Re: STM32F107 on STM3210C-EVAL
@ 2011-03-28 11:23 qber_
  0 siblings, 0 replies; 9+ messages in thread
From: qber_ @ 2011-03-28 11:23 UTC (permalink / raw)
  To: ecos-devel, Gian Maria, jerzy dyrda

Hello again

W dniu 2011-03-28 12:47:07 użytkownik jerzy dyrda <> napisał:
> Hello all,
> On Monday 28 March 2011 11:51:45 wrote:
> (...)
> > There is only one thing left - the RCC differences. In RM there is a
> > seperate section about RCC config for CL. But at the first look it seems
> > that registers are compatible.
> RCC registers are extended to support 2 extra PPL's with appropriate divider and multiplier.
> Main differences is that source of PLL clock it isn't anymore taken directly from HSE or HSE/2 clock 
> but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR register has partially 
> different meaning. And another issue is external crystal. It value is 25MHz not 8 MHz like in 
> STM3210E what causes need of using second PLL to produce CPU 72MHz.
> HSE == 25MHz   /  PREDIV2 == 5 -> 5MHz   *  PLLMUL2 == 8 ->  
> 40MHz / PREDIV1 == 5 -> 8MHz * PLLMUL == 9 -> 72MHz = SYSCLK
> It's looks ugly but above method it's used in ST source code for STM3210C evaluation board.

It's not quite true. According to scheme and RM the clock can be takien from PLL2 or HSE directly. This is configured in RCC_CFGR2 bit 16
PREDIV1_SRC. Only the crystal have to be replaced on PCB.
> Best regards
> jerzy
Best regards

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2011-04-14 10:59 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-03-22 19:15 STM32F107 on STM3210C-EVAL Gian Maria
2011-03-23 10:51 ` John Dallaway
2011-03-26 11:07   ` Ilija Kocho
2011-03-28  9:55 ` qber_
2011-03-28 10:47   ` jerzy dyrda
2011-03-28 19:13     ` R: " Gian Maria
2011-03-28 11:34   ` Ilija Kocho
2011-04-14 10:59   ` mlazcoz
2011-03-28 11:23 qber_

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