[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:524d0f5f4b5127baad8269a2e8ddd1a44f5a2745

commit 524d0f5f4b5127baad8269a2e8ddd1a44f5a2745
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 19:55:27 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 70035b036c6..953c2e99983 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -7,10 +7,10 @@ floating point by loading the value directly to the vector register, and then
 doing the conversion instead of loading the value to a GPR and then doing a
 direct move:
 
-	* vector int
-	* vector unsigned int
-	* vector unsigned short
-	* vector unsigned char
+	vector int
+	vector unsigned int
+	vector unsigned short
+	vector unsigned char
 
 2023-04-26   Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:6702108df42f9135e32cdffdaae8055122b0bafc

commit 6702108df42f9135e32cdffdaae8055122b0bafc
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon May 1 13:24:12 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 85bfbce8419..7a3f8e4b578 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,33 @@
+==================== Branch work119, patch #130 ====================
+
+Split vec_extract from memory before reload for V16QI/V8HI/V4SI with constant elements.
+
+This patch goes through the support function rs6000_adjust_vec_address and the
+functions it calls to allow them to be called before register allocation.  The
+places that take a scratch register will allocate a new pseudo register if they
+are passed a SCRATCH register.
+
+It then changes the vec_extract support for V16QI/V8HI/V4SI with constant
+element numbers to be split before register allocation.
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
+	called before register allocation.
+	(adjust_vec_address_pcrel): Likewise.
+	(rs6000_adjust_vec_address): Likewise.
+	* config/rs6000/vsx.md (vsx_extract_<mode>_load): Split before register
+	allocation.
+	(vsx_extract_v4si_load_to_<su>di): Likewise.
+	(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): Likewise.
+	(*vsx_extract_v8hi_load_to_s<mode>): Likewise.
+	(vsx_extract_<mode>_var_load): Likewise.
+	(vsx_extract_v4si_var_load_to_<su>di): Likewise.
+	(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): Likewise.
+	(vsx_extract_v8hi_var_load_to_s<mode>): Likewise.
+
 ==================== Branch work119, patch #127 ====================
 
 Optimize variable element vec_extract to be converted to floating point

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:bebe586a5c497d085252e347bdaf659d484533ba

commit bebe586a5c497d085252e347bdaf659d484533ba
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Apr 29 00:10:54 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 115 +++++++++++++++++++------------------------------
 1 file changed, 44 insertions(+), 71 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index fbcd62cbbd3..85bfbce8419 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,11 +1,11 @@
-==================== Branch work119, patch #107 ====================
+==================== Branch work119, patch #127 ====================
 
 Optimize variable element vec_extract to be converted to floating point
 
-This patch allows vec_extract with a variable element of the following types to
-be converted to floating point by loading the value directly to the vector
-register, and then doing the conversion instead of loading the value to a GPR
-and then doing a direct move:
+This patch optimizes vec_extract with a variable element number of the following
+types to be converted to floating point by loading the value directly to the
+vector register, and then doing the conversion instead of loading the value to a
+GPR and then doing a direct move:
 
 vector int
 vector unsigned int
@@ -17,26 +17,23 @@ vector unsigned char
 gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
-	insn.
+	* insn.
 	* vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_uns<SFDF:mode>: New
 	insn.
 
 gcc/testsuite/
 
-	* gcc.target/powerpc/vec-extract-mem-char-3.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-int-6.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-int_7.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-short-5.c: New file.
-
 
-==================== Branch work119, patch #106 ====================
+==================== Branch work119, patch #126 ====================
 
-Optimize constant element vec_extract to be converted to floating point
+Allow constant element vec_extract to be converted to floating point
 
-This patch allows vec_extract with a constant element of the following types to
-be converted to floating point by loading the value directly to the vector
-register, and then doing the conversion instead of loading the value to a GPR
-and then doing a direct move:
+This patch allows vec_extract of the following types to be converted to
+floating point by loading the value directly to the vector register, and then
+doing the conversion instead of loading the value to a GPR and then doing a
+direct move:
 
 vector int
 vector unsigned int
@@ -49,7 +46,7 @@ gcc/
 
 	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
 	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
-	insn.
+	* insn.
 	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
 
 gcc/testsuite/
@@ -59,7 +56,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
 
-==================== Branch work119, patch #105 ====================
+==================== Branch work119, patch #125 ====================
 
 Allow variable element vec_extract to be sign or zero extended
 
@@ -80,28 +77,23 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
 
-
-==================== Branch work119, patch #104 ====================
+==================== Branch work119, patch #124 ====================
 
 Allow variable element vec_extract to be loaded into vector registers.
 
 This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
-variable element number to be loaded into vector registers directly.  It also
-will be split before register allocation.  In doing so, I restricted the
-optimization to only occur if the memory address did not use an Altivec style
-address with AND -16.
+variable element number to be loaded into vector registers directly.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
-	registers to be loaded.  Split before register allocation.  Restrict
-	vector addresses to not use Altivec addressing.
+	registers to be loaded.
 
-==================== Branch work119, patch #103 ====================
+==================== Branch work119, patch #123 ====================
 
-Allow consant element vec_extract to be zero or sign extended
+Optimize sign and zero extension of vec_extract from memory with constant element
 
 This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be zero extended.  It also allows vec_extract of V4SI
@@ -111,7 +103,7 @@ and V8HI vector types with constant element number to be sign extended.
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
 	(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
 	(vsx_extract_v8hi_load_to_s<mode>): New insn.
 
@@ -123,26 +115,27 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
 
-==================== Branch work119, patch #102 ====================
+==================== Branch work119, patch #122 ====================
 
 Allow consant element vec_extract to be loaded into vector registers.
 
 This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
-constant element number to be loaded into vector registers directly.  It also
-will be split before register allocation.  In doing so, I restricted the
-optimization to only occur if the memory address did not use an Altivec style
-address with AND -16.
+constant element number to be loaded into vector registers directly.
+
+This patch also adds support for optimzing 0 element number to not need a base
+register tempoary.  Likewise, if we have an offsettable address, we don't need
+to allocate a scratch register.
 
 2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
-	(vsx_extract_<mode>_load): Allow vector registers to be loaded.  Do insn
-	split before register allocation.  Restrict vector addresses to not use
-	Altivec addressing.
+	(vsx_extract_<mode>_load): Allow vector registers to be loaded.  Add
+	optimizations for loading up element 0 and/or with an offsettable
+	address.
 
-==================== Branch work119, patch #101 ====================
+==================== Branch work119, patch #121 ====================
 
 Optimize vec_extract of V4SF with variable element number being converted to DF
 
@@ -150,73 +143,53 @@ This patch adds a combiner insn to include the conversion of float to double
 within the memory address when vec_extract of V4SF with a variable element
 number is done.
 
-In addition, the patch allows the split of vec_extract of V4SF with a variable
-element number to occur before register allocation.  In doing so, I restricted
-the optimization to only occur if the memory address did not use an Altivec
-style address with AND -16.
+It also removes the '?' from the 'r' constraint so that if the SFmode is needed
+in a GPR, it doesn't have to load it to the vector unit and then store it.
 
 2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
-	register allocation.  Restrict memory addresses to not using Altivec
-	memory addresses.
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Remove '?' from 'r'
+	constraint.
 	(vsx_extract_v4sf_var_load_to_df): New insn.
 
 gcc/testsuite/
 
 	* gcc.target/powerpc/vec-extract-mem-float-2.c: New file.
 
-==================== Branch work119, patch #100 ====================
+==================== Branch work119, patch #120 ====================
 
 Optimize vec_extract of V4SF from memory with constant element numbers.
 
 This patch updates vec_extract of V4SF from memory with constant element
 numbers.
 
-This patch changes the splits so that they can be done before register
-allocation.
-
 This patch corrects the ISA for loading SF values to altivec registers to be
 power8 vector, and not power7.
 
 This patch adds a combiner patch to combine loading up a SF element and
 converting it to double.
 
-In order to do the splitting before register allocation, I modified the various
-vec_extract insns to allow the split to occur before register allocation.  This
-patch goes through the support function rs6000_adjust_vec_address and the
-functions it calls to allow them to be called before register allocation.  The
-places that take a scratch register will allocate a new pseudo register if they
-are passed a SCRATCH register.
-
-I also added a new predicate that checks if the operand is a normal memory
-address but not an Altivec vector addresses (i.e. with an AND -16).  These
-addresses are used in power8 as part of the vector swap optimization.  In the
-past, because we use the 'Q' constraint, ira/reload would handle the AND
-etc. so that the address was only a single register.
+It also removes the '?' from the 'r' constraint so that if the SFmode is needed
+in a GPR, it doesn't have to load it to the vector unit and then store it.
 
 2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/predicates.md (non_altivec_memory_operand): New
-	predicate.
-	* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
-	called before register allocation.
-	(adjust_vec_address_pcrel): Likewise.
-	(rs6000_adjust_vec_address): Likewise.
-	* gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow splitting
-	before register allocation.  Fix ISA for loading up SFmode values to
-	traditional Altivec registers.  Require that the memory being optimized
-	does not use Altivec memory addresses.
+	* gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Fix ISA for loading
+	up SFmode values with x-form addresses.  Remove ? from 'r' constraint.
 	(vsx_extract_v4sf_load_to_df): New insn.
 
 gc/testsuite/
 
 	* gcc.target/powerpc/vec-extract-mem-float-1.c: New file.
 
+==================== Branch work119, patche #110-113 were reverted ====================
+
+==================== Branch work119, patche #100-107 were reverted ====================
+
 ==================== Branch work119, patches #90-97 were reverted ====================
 
 ==================== Branch work119, patches #80-84 were reverted ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:711ab57d95d943a427ece0ee96e3c518ea8ccd23

commit 711ab57d95d943a427ece0ee96e3c518ea8ccd23
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 28 15:48:51 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 207 ++++++++++++++++++++++---------------------------
 1 file changed, 94 insertions(+), 113 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index fea7e2ed108..fbcd62cbbd3 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,16 +1,47 @@
-==================== Branch work119, patch #97 ====================
+==================== Branch work119, patch #107 ====================
 
-Allow constant element vec_extract to be converted to floating point
+Optimize variable element vec_extract to be converted to floating point
 
-This patch allows vec_extract of the following types to be converted to
-floating point by loading the value directly to the vector register, and then
-doing the conversion instead of loading the value to a GPR and then doing a
-direct move:
+This patch allows vec_extract with a variable element of the following types to
+be converted to floating point by loading the value directly to the vector
+register, and then doing the conversion instead of loading the value to a GPR
+and then doing a direct move:
 
-	vector int
-	vector unsigned int
-	vector unsigned short
-	vector unsigned char
+vector int
+vector unsigned int
+vector unsigned short
+vector unsigned char
+
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
+	insn.
+	* vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_uns<SFDF:mode>: New
+	insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-3.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-6.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int_7.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-5.c: New file.
+
+
+==================== Branch work119, patch #106 ====================
+
+Optimize constant element vec_extract to be converted to floating point
+
+This patch allows vec_extract with a constant element of the following types to
+be converted to floating point by loading the value directly to the vector
+register, and then doing the conversion instead of loading the value to a GPR
+and then doing a direct move:
+
+vector int
+vector unsigned int
+vector unsigned short
+vector unsigned char
 
 2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
@@ -18,7 +49,7 @@ gcc/
 
 	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
 	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
-	* insn.
+	insn.
 	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
 
 gcc/testsuite/
@@ -28,7 +59,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
 
-==================== Branch work119, patch #96 ====================
+==================== Branch work119, patch #105 ====================
 
 Allow variable element vec_extract to be sign or zero extended
 
@@ -49,22 +80,26 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
 
-==================== Branch work119, patch #95 ====================
+
+==================== Branch work119, patch #104 ====================
 
 Allow variable element vec_extract to be loaded into vector registers.
 
 This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded into vector registers directly.  It also
-will be split before register allocation.
+will be split before register allocation.  In doing so, I restricted the
+optimization to only occur if the memory address did not use an Altivec style
+address with AND -16.
 
 2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
-	registers to be loaded.  Split before register allocation.
+	registers to be loaded.  Split before register allocation.  Restrict
+	vector addresses to not use Altivec addressing.
 
-==================== Branch work119, patch #94 ====================
+==================== Branch work119, patch #103 ====================
 
 Allow consant element vec_extract to be zero or sign extended
 
@@ -72,11 +107,11 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be zero extended.  It also allows vec_extract of V4SI
 and V8HI vector types with constant element number to be sign extended.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
 	(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
 	(vsx_extract_v8hi_load_to_s<mode>): New insn.
 
@@ -88,23 +123,26 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
 
-==================== Branch work119, patch #93 ====================
+==================== Branch work119, patch #102 ====================
 
 Allow consant element vec_extract to be loaded into vector registers.
 
 This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be loaded into vector registers directly.  It also
-will be split before register allocation.
+will be split before register allocation.  In doing so, I restricted the
+optimization to only occur if the memory address did not use an Altivec style
+address with AND -16.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
 	(vsx_extract_<mode>_load): Allow vector registers to be loaded.  Do insn
-	split before register allocation.
+	split before register allocation.  Restrict vector addresses to not use
+	Altivec addressing.
 
-==================== Branch work119, patch #92 ====================
+==================== Branch work119, patch #101 ====================
 
 Optimize vec_extract of V4SF with variable element number being converted to DF
 
@@ -113,21 +151,24 @@ within the memory address when vec_extract of V4SF with a variable element
 number is done.
 
 In addition, the patch allows the split of vec_extract of V4SF with a variable
-element number to occur before register allocation.
+element number to occur before register allocation.  In doing so, I restricted
+the optimization to only occur if the memory address did not use an Altivec
+style address with AND -16.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
-	register allocation.
+	register allocation.  Restrict memory addresses to not using Altivec
+	memory addresses.
 	(vsx_extract_v4sf_var_load_to_df): New insn.
 
 gcc/testsuite/
 
 	* gcc.target/powerpc/vec-extract-mem-float-2.c: New file.
 
-==================== Branch work119, patch #91 ====================
+==================== Branch work119, patch #100 ====================
 
 Optimize vec_extract of V4SF from memory with constant element numbers.
 
@@ -143,108 +184,48 @@ power8 vector, and not power7.
 This patch adds a combiner patch to combine loading up a SF element and
 converting it to double.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow splitting
-	before register allocation.  Fix ISA for loading up SFmode values to
-	traditional Altivec registers.
-	(vsx_extract_v4sf_load_to_df): New insn.
-
-gc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-float-1.c: New file.
-
-==================== Branch work119, patch #90 ====================
-
-Allow vec_extract from memory support functions before reload
+In order to do the splitting before register allocation, I modified the various
+vec_extract insns to allow the split to occur before register allocation.  This
+patch goes through the support function rs6000_adjust_vec_address and the
+functions it calls to allow them to be called before register allocation.  The
+places that take a scratch register will allocate a new pseudo register if they
+are passed a SCRATCH register.
 
-In the succeeding patches, I will be modifying the various vec_extract insns to
-allow the split to occur before register allocation.  This patch goes through
-the support function rs6000_adjust_vec_address and the functions it calls to
-allow them to be called before register allocation.  The places that take a
-scratch register will allocate a new pseudo register if they are passed a
-SCRATCH register.
+I also added a new predicate that checks if the operand is a normal memory
+address but not an Altivec vector addresses (i.e. with an AND -16).  These
+addresses are used in power8 as part of the vector swap optimization.  In the
+past, because we use the 'Q' constraint, ira/reload would handle the AND
+etc. so that the address was only a single register.
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
+	* config/rs6000/predicates.md (non_altivec_memory_operand): New
+	predicate.
 	* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
 	called before register allocation.
 	(adjust_vec_address_pcrel): Likewise.
 	(rs6000_adjust_vec_address): Likewise.
+	* gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow splitting
+	before register allocation.  Fix ISA for loading up SFmode values to
+	traditional Altivec registers.  Require that the memory being optimized
+	does not use Altivec memory addresses.
+	(vsx_extract_v4sf_load_to_df): New insn.
 
-==================== Branch work119, patch #84 was reverted ====================
-
-==================== Branch work119, patch #83 was reverted ====================
-
-==================== Branch work119, patch #82 was reverted ====================
-
-==================== Branch work119, patch #81 was reverted ====================
-
-==================== Branch work119, patch #80 was reverted ====================
-
-==================== Branch work119, patch #72 was reverted ====================
-
-==================== Branch work119, patch #71 was reverted ====================
-
-==================== Branch work119, patch #70 was reverted ====================
-
-==================== Branch work119, patch #69 was reverted ====================
-
-==================== Branch work119, patch #68 was reverted ====================
-
-==================== Branch work119, patch #67 was reverted ====================
-
-==================== Branch work119, patch #66 was reverted ====================
-
-==================== Branch work119, patch #65 was reverted ====================
-
-==================== Branch work119, patch #64 was reverted ====================
-
-==================== Branch work119, patch #63 was reverted ====================
-
-==================== Branch work119, patch #62 was reverted ====================
-
-==================== Branch work119, patch #61 was reverted ====================
-
-==================== Branch work119, patch #60 was reverted ====================
-
-==================== Branch work119, patch #52 was reverted ====================
-
-==================== Branch work119, patch #51 was reverted ====================
-
-==================== Branch work119, patch #50 was reverted ====================
-
-==================== Branch work119, patch #49 was reverted ====================
-
-==================== Branch work119, patch #48 was reverted ====================
-
-==================== Branch work119, patch #47 was reverted ====================
-
-==================== Branch work119, patch #46 was reverted ====================
-
-==================== Branch work119, patch #45 was reverted ====================
-
-==================== Branch work119, patch #44 was reverted ====================
-
-==================== Branch work119, patch #43 was reverted ====================
-
-==================== Branch work119, patch #42 was reverted ====================
+gc/testsuite/
 
-==================== Branch work119, patch #41 was reverted ====================
+	* gcc.target/powerpc/vec-extract-mem-float-1.c: New file.
 
-==================== Branch work119, patch #40 was reverted ====================
+==================== Branch work119, patches #90-97 were reverted ====================
 
-==================== Branch work119, patch #33 was reverted ====================
+==================== Branch work119, patches #80-84 were reverted ====================
 
-==================== Branch work119, patch #32 was reverted ====================
+==================== Branch work119, patches #70-60 were reverted ====================
 
-==================== Branch work119, patch #31 was reverted ====================
+==================== Branch work119, patches #50-40 were reverted ====================
 
-==================== Branch work119, patch #30 was reverted ====================
+==================== Branch work119, patches #30-33 were reverted ====================
 
 ==================== Branch work119, patch #23 ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:0f49ae2d0de3e8c53a0fb27afdac5f5f0593ccba

commit 0f49ae2d0de3e8c53a0fb27afdac5f5f0593ccba
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 28 02:37:26 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 514c593ada8..fea7e2ed108 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -12,7 +12,7 @@ direct move:
 	vector unsigned short
 	vector unsigned char
 
-2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:254a02cd8df1afb9393c2526473d9254debdebcd

commit 254a02cd8df1afb9393c2526473d9254debdebcd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 27 23:44:41 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b82c649fdf6..514c593ada8 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,33 @@
+==================== Branch work119, patch #97 ====================
+
+Allow constant element vec_extract to be converted to floating point
+
+This patch allows vec_extract of the following types to be converted to
+floating point by loading the value directly to the vector register, and then
+doing the conversion instead of loading the value to a GPR and then doing a
+direct move:
+
+	vector int
+	vector unsigned int
+	vector unsigned short
+	vector unsigned char
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
+	* insn.
+	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
+
 ==================== Branch work119, patch #96 ====================
 
 Allow variable element vec_extract to be sign or zero extended
@@ -19,7 +49,6 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
 
-
 ==================== Branch work119, patch #95 ====================
 
 Allow variable element vec_extract to be loaded into vector registers.

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:eea429174b24081377a2331a4aea963211f83996

commit eea429174b24081377a2331a4aea963211f83996
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 27 23:37:40 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 159 ++++++++++++++++++++++++++++---------------------
 1 file changed, 91 insertions(+), 68 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 953c2e99983..b82c649fdf6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,35 +1,4 @@
-==================== Branch work119, patch #84 ====================
-
-Allow constant element vec_extract to be converted to floating point
-
-This patch allows vec_extract of the following types to be converted to
-floating point by loading the value directly to the vector register, and then
-doing the conversion instead of loading the value to a GPR and then doing a
-direct move:
-
-	vector int
-	vector unsigned int
-	vector unsigned short
-	vector unsigned char
-
-2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
-	* insn.
-	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
-
-
-==================== Branch work119, patch #83 ====================
+==================== Branch work119, patch #96 ====================
 
 Allow variable element vec_extract to be sign or zero extended
 
@@ -37,7 +6,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded with sign or zero extension, and GCC will
 not generate a separate zero/sign extension instruction.
 
-2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -51,7 +20,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
 
 
-==================== Branch work119, patch #82 ====================
+==================== Branch work119, patch #95 ====================
 
 Allow variable element vec_extract to be loaded into vector registers.
 
@@ -59,14 +28,14 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded into vector registers directly.  It also
 will be split before register allocation.
 
-2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
 	registers to be loaded.  Split before register allocation.
 
-==================== Branch work119, patch #81 ====================
+==================== Branch work119, patch #94 ====================
 
 Allow consant element vec_extract to be zero or sign extended
 
@@ -74,7 +43,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be zero extended.  It also allows vec_extract of V4SI
 and V8HI vector types with constant element number to be sign extended.
 
-2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -90,7 +59,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
 
-==================== Branch work119, patch #80 ====================
+==================== Branch work119, patch #93 ====================
 
 Allow consant element vec_extract to be loaded into vector registers.
 
@@ -98,19 +67,95 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be loaded into vector registers directly.  It also
 will be split before register allocation.
 
-This patch also adds support to rs6000_adjust_vec_address to allow it to be run
-before register allocation.
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
-2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+gcc/
+
+	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
+	(vsx_extract_<mode>_load): Allow vector registers to be loaded.  Do insn
+	split before register allocation.
+
+==================== Branch work119, patch #92 ====================
+
+Optimize vec_extract of V4SF with variable element number being converted to DF
+
+This patch adds a combiner insn to include the conversion of float to double
+within the memory address when vec_extract of V4SF with a variable element
+number is done.
+
+In addition, the patch allows the split of vec_extract of V4SF with a variable
+element number to occur before register allocation.
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
 	register allocation.
+	(vsx_extract_v4sf_var_load_to_df): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-float-2.c: New file.
+
+==================== Branch work119, patch #91 ====================
+
+Optimize vec_extract of V4SF from memory with constant element numbers.
+
+This patch updates vec_extract of V4SF from memory with constant element
+numbers.
+
+This patch changes the splits so that they can be done before register
+allocation.
+
+This patch corrects the ISA for loading SF values to altivec registers to be
+power8 vector, and not power7.
+
+This patch adds a combiner patch to combine loading up a SF element and
+converting it to double.
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* gcc/config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow splitting
+	before register allocation.  Fix ISA for loading up SFmode values to
+	traditional Altivec registers.
+	(vsx_extract_v4sf_load_to_df): New insn.
+
+gc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-float-1.c: New file.
+
+==================== Branch work119, patch #90 ====================
+
+Allow vec_extract from memory support functions before reload
+
+In the succeeding patches, I will be modifying the various vec_extract insns to
+allow the split to occur before register allocation.  This patch goes through
+the support function rs6000_adjust_vec_address and the functions it calls to
+allow them to be called before register allocation.  The places that take a
+scratch register will allocate a new pseudo register if they are passed a
+SCRATCH register.
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (get_vector_offset): Allow function to be
+	called before register allocation.
 	(adjust_vec_address_pcrel): Likewise.
 	(rs6000_adjust_vec_address): Likewise.
-	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
-	(vsx_extract_<mode>_load): Allow vector registers to be loaded.
+
+==================== Branch work119, patch #84 was reverted ====================
+
+==================== Branch work119, patch #83 was reverted ====================
+
+==================== Branch work119, patch #82 was reverted ====================
+
+==================== Branch work119, patch #81 was reverted ====================
+
+==================== Branch work119, patch #80 was reverted ====================
 
 ==================== Branch work119, patch #72 was reverted ====================
 
@@ -134,31 +179,9 @@ gcc/
 
 ==================== Branch work119, patch #62 was reverted ====================
 
-==================== Branch work119, patch #61 ====================
-
-Combine vec_extract of V4SF with DF convert with variable element.
-
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is variable combined with a conversion to DFmode.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load_to_df): New insn.
-
-==================== Branch work119, patch #60 ====================
-
-Combine vec_extract of V4SF with DF convert with constant element number.
-
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is constant combined with a conversion to DFmode.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
+==================== Branch work119, patch #61 was reverted ====================
 
-	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
+==================== Branch work119, patch #60 was reverted ====================
 
 ==================== Branch work119, patch #52 was reverted ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:639a9f1ab0f7f2d37064f59c015b0cc047f472aa

commit 639a9f1ab0f7f2d37064f59c015b0cc047f472aa
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 19:44:44 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3cac2be603b..70035b036c6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,34 @@
+==================== Branch work119, patch #84 ====================
+
+Allow constant element vec_extract to be converted to floating point
+
+This patch allows vec_extract of the following types to be converted to
+floating point by loading the value directly to the vector register, and then
+doing the conversion instead of loading the value to a GPR and then doing a
+direct move:
+
+	* vector int
+	* vector unsigned int
+	* vector unsigned short
+	* vector unsigned char
+
+2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
+	* insn.
+	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
+
+
 ==================== Branch work119, patch #83 ====================
 
 Allow variable element vec_extract to be sign or zero extended

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:8c8f054fcc34959bf1ef33808c68598730567b59

commit 8c8f054fcc34959bf1ef33808c68598730567b59
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 12:21:10 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 51 +++++++++++++++++++++++++++++++-------------------
 1 file changed, 32 insertions(+), 19 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 16c9a116edc..3cac2be603b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -237,25 +237,33 @@ gcc/testsuite/
 
 ==================== Branch work119, patch #1 ====================
 
-Make load/cmp fusion know about prefixed loads.
+PR target/105325: Make load/cmp fusion know about prefixed loads.
 
-I posted a version of patch on March 21st and a second version on March 24th.
-This patch makes some code changes suggested in the genfusion.pl code from the
-last 2 patch submissions.  The fusion.md that is produced by genfusion.pl is
-the same in all 3 versions.
+I posted a version of patch on March 21st, a second version on March 24th, and
+the third version on March 28th.
 
-I changed the genfusion.pl to match the suggestion for code layout.  I also
-used the correct comment for each of the instructions (in the 2nd patch, the
-when I rewrote the comments about ld and lwa being DS format instructions, I
-had put the ld comment in the section handling lwa, and vice versa).
+The V4 patch just adds a new condition to the new test case.  Previously, I was
+using 'powerpc_prefixed_addr' to determine whether the GCC compiler would
+automatically generate prefixed addresses.  The V4 version also adds a check
+for 'power10_ok'.  Power10_ok is needed in case the compiler could generate
+prefixed addresses, but the assembler does not support prefixed instructions.
 
-I also removed lp64 from the new test.  When I first added the prefixed code,
-it was only done for 64-bit, but now it is allowed for 32-bit.  However, the
-case that shows up (lwa) would not hit in 32-bit, since it only generates lwz
-and not lwa.  It also would not generate ld.  But the test does pass when it is
-built with -m32.
+The V3 patch makes some code changes suggested in the genfusion.pl code from
+the last 2 patch submissions.  The fusion.md that is produced by genfusion.pl
+is the same in all 3 versions.
 
-The issue with the bug is the power10 load GPR + cmpi -1/0/1 fusion
+In V3, I changed the genfusion.pl to match the suggestion for code layout.  I
+also used the correct comment for each of the instructions (in the 2nd patch,
+the when I rewrote the comments about ld and lwa being DS format instructions,
+I had put the ld comment in the section handling lwa, and vice versa).
+
+In V3, I also removed lp64 from the new test.  When I first added the prefixed
+code, it was only done for 64-bit, but now it is allowed for 32-bit.  However,
+the case that shows up (lwa) would not hit in 32-bit, since it only generates
+lwz and not lwa.  It also would not generate ld.  But the test does pass when
+it is built with -m32.
+
+The issue with the original bug is the power10 load GPR + cmpi -1/0/1 fusion
 optimization generates illegal assembler code.
 
 Ultimately the code was dying because the fusion load + compare -1/0/1 patterns
@@ -274,10 +282,15 @@ operand[1] is a prefixed instruction.
 
 I have tested this code on a power9 little endian system (with long double
 being IEEE 128-bit and IBM 128-bit), a power10 little endian system, and a
-power8 big endian system, testing both 32-bit and 64-bit code generation.  Can
-I put this code into the master branch, and after a waiting period, apply it to
-the GCC 12 and GCC 11 branches (the bug does show up in those branches, and the
-patch applies without change).
+power8 big endian system, testing both 32-bit and 64-bit code generation.
+
+For the V4 changes I also built the compiler on a big endian system with an
+older assembler, and I verified that the pr105325.C test was listed as
+unsupported.
+
+Can I put this code into the master branch, and after a waiting period, apply
+it to the GCC 12 and GCC 11 branches (the bug does show up in those branches,
+and the patch applies without change).
 
 2023-04-26   Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:f64caf896d2a371ef77510d4837e3be99925b76a

commit f64caf896d2a371ef77510d4837e3be99925b76a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 11:47:13 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8254b9027f2..16c9a116edc 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -6,7 +6,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded with sign or zero extension, and GCC will
 not generate a separate zero/sign extension instruction.
 
-2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -28,7 +28,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded into vector registers directly.  It also
 will be split before register allocation.
 
-2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -43,7 +43,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be zero extended.  It also allows vec_extract of V4SI
 and V8HI vector types with constant element number to be sign extended.
 
-2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:df88c72ec0e4326cceefec88a1b7115ed444a184

commit df88c72ec0e4326cceefec88a1b7115ed444a184
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 26 01:14:08 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3109354c454..8254b9027f2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -279,7 +279,7 @@ I put this code into the master branch, and after a waiting period, apply it to
 the GCC 12 and GCC 11 branches (the bug does show up in those branches, and the
 patch applies without change).
 
-2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-26   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:54a3423c6134b2354e2c9b888167f84c6a48de66

commit 54a3423c6134b2354e2c9b888167f84c6a48de66
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 25 11:56:53 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3334848781f..3109354c454 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -6,7 +6,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded with sign or zero extension, and GCC will
 not generate a separate zero/sign extension instruction.
 
-2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -28,7 +28,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 variable element number to be loaded into vector registers directly.  It also
 will be split before register allocation.
 
-2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -43,7 +43,7 @@ This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
 constant element number to be zero extended.  It also allows vec_extract of V4SI
 and V8HI vector types with constant element number to be sign extended.
 
-2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-25   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:ade6286b050123ef8fcd9ff15e435bed8bd77e38

commit ade6286b050123ef8fcd9ff15e435bed8bd77e38
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 22:55:16 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1fe1b591c74..3334848781f 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,40 @@
+==================== Branch work119, patch #83 ====================
+
+Allow variable element vec_extract to be sign or zero extended
+
+This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
+variable element number to be loaded with sign or zero extension, and GCC will
+not generate a separate zero/sign extension instruction.
+
+2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
+	(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
+	(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
+
+
+==================== Branch work119, patch #82 ====================
+
+Allow variable element vec_extract to be loaded into vector registers.
+
+This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
+variable element number to be loaded into vector registers directly.  It also
+will be split before register allocation.
+
+2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
+	registers to be loaded.  Split before register allocation.
+
 ==================== Branch work119, patch #81 ====================
 
 Allow consant element vec_extract to be zero or sign extended

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:62b7f25d96b490e5abf15c54e93bee3c1f87b65c

commit 62b7f25d96b490e5abf15c54e93bee3c1f87b65c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 22:04:50 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 155c0dcc4a8..1fe1b591c74 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -12,7 +12,7 @@ gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
 	(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
-	(vsx_extract_v8hi_load_to_z<mode>): New insn.
+	(vsx_extract_v8hi_load_to_s<mode>): New insn.
 
 gcc/testsuite/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:e65998ab6c7cdb8a509a3a72553f207587023e32

commit e65998ab6c7cdb8a509a3a72553f207587023e32
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 22:03:27 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 5210646122b..155c0dcc4a8 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work119, patch #81 was reverted ====================
+==================== Branch work119, patch #81 ====================
 
 Allow consant element vec_extract to be zero or sign extended
 
@@ -22,7 +22,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
 
-==================== Branch work119, patch #80 was reverted ====================
+==================== Branch work119, patch #80 ====================
 
 Allow consant element vec_extract to be loaded into vector registers.

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:9c4f9bcb321c704b7a24ec1f101f3e2df2a5a0ce

commit 9c4f9bcb321c704b7a24ec1f101f3e2df2a5a0ce
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 15:00:58 2023 -0400

    Update ChangeLog.meissner.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 144 +++++++++----------------------------------------
 1 file changed, 25 insertions(+), 119 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b16a81f8d58..82745912b34 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,151 +1,57 @@
-==================== Branch work119, patch #49 ====================
+==================== Branch work119, patch #51 ====================
 
-Fold sign or zero extension into vsx_extract from memory with variable element.
-
-This patch folds conversion to floating point of vsx_extract from memory of V4SI
-elements where the element number is constant.  This code optimizes things so it
-will load the integer with LFIWAX or LFIWZX directly into a vector register
-rather than loading it into a GPR and doing a direct move operation.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
-	insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
-
-==================== Branch work119, patch #48 ====================
+Combine vec_extract of V4SF with DF convert.
 
-Fold sign or zero convert into variable vsx_extract from memory.
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
 
-This patch folds sign or zero convert operations into vsx_extract from memory
-where the element number is constant.
+In addition, I changed the vec_extract of V4SFmode where the element number is
+constant without conversion to do the split before register allocation.
 
 2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
-	(vsx_extract_<mode>_var_load_to_sdi): New insn.
-	(vsx_extract_v8hi_var_load_to_<su>si): New insn.
+	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
+	register allocation.
+	(vsx_extract_v4sf_to_df_load): New insn.
 
 gcc/testsuite/
 
-	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
-
-==================== Branch work119, patch #47 ====================
-
-Allow vec_extract with variable element number to load vector registers.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
-	of integer types with a variable element number to load into vector
-	registers.  Allow splitting before register allocation.
-
-==================== Branch work119, patch #46 ====================
+	* gcc.target/powerpc/vec-extract-mem-float-1.c: New test.
 
-Combine variable element vec_extract of V4SF with DF convert.
+==================== Branch work119, patch #50 ====================
 
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is variable combined with a conversion to DFmode.
+Allow vec_extract support functions to be called before reload.
 
 2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load_to_df): New insn.
-
-==================== Branch work119, patch #45 ====================
-
-Fold conversion to float into V4SI vsx_extract from memory.
+	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+	register allocation.
+	(adjust_vec_address_pcrel): Likewise.
+	(rs6000_adjust_vec_address): Likewise.
 
-This patch folds conversion to floating point of vsx_extract from memory of V4SI
-elements where the element number is constant.  This code optimizes things so it
-will load the integer with LFIWAX or LFIWZX directly into a vector register
-rather than loading it into a GPR and doing a direct move operation.
+==================== Branch work119, patch #49 was reverted ====================
 
-2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+==================== Branch work119, patch #48 was reverted ====================
 
-gcc/
-
-	* config/rs6000/vsx.md (SIGN_ZERO_EXTEND): New mode attribute.
-	(vsx_extract_v4si_load_to_<uns><mode>): New insn.
+==================== Branch work119, patch #47 was reverted ====================
 
-gcc/testsuite/
+==================== Branch work119, patch #46 was reverted ====================
 
-	* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
+==================== Branch work119, patch #45 was reverted ====================
 
 ==================== Branch work119, patch #44 was reverted ====================
 
-==================== Branch work119, patch #43 ====================
+==================== Branch work119, patch #43 was reverted ====================
 
-Fold sign or zero convert into vsx_extract from memory.
+==================== Branch work119, patch #42 was reverted ====================
 
-This patch folds sign or zero convert operations into vsx_extract from memory
-where the element number is constant.
+==================== Branch work119, patch #41 was reverted ====================
 
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (VSX_EXTRACT_ISIGN): New mode attribute.
-	(vsx_extract_<mode>_load_to_udi): New insn.
-	(vsx_extract_<mode>_load_to_sdi): New insn.
-	(vsx_extract_v8hi_load_to_<su>si): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
-
-==================== Branch work119, patch #42 ====================
-
-Allow vec_extract to load vector registers.
-
-2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
-	(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
-	constant element number to load into vector registers.  Allow splitting
-	before register allocation.
-
-==================== Branch work119, patch #41 ====================
-
-Combine vec_extract of V4SF with DF convert.
-
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is constant combined with a conversion to DFmode.
-
-2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
-
-==================== Branch work119, patch #40 ====================
-
-Allow vec_extract support functions to be called before reload.
-
-2023-04-19   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
-	register allocation.
-	(adjust_vec_address_pcrel): Likewise.
-	(rs6000_adjust_vec_address): Likewise.
+==================== Branch work119, patch #40 was reverted ====================
 
 ==================== Branch work119, patch #33 was reverted ====================