From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez
Date: Fri, 21 Apr 2023 13:40:39 -0600 [thread overview]
Message-ID: <0360d93f-838f-ccd3-c29a-da2348ea7679@gmail.com> (raw)
In-Reply-To: <20230210224150.2801962-7-philipp.tomsich@vrull.eu>
On 2/10/23 15:41, Philipp Tomsich wrote:
> Users might use explicit arithmetic operations to create a mask and
> then and it, in a sequence like
> cond = (bits >> SHIFT) & 1;
> mask = ~(cond - 1);
> val &= mask;
> which will present as a single-bit sign-extract.
>
> Dependening on what combination of XVentanaCondOps and Zbs are
> available, this will map to the following sequences:
> - bexti + czero, if both Zbs and XVentanaCondOps are present
> - andi + czero, if only XVentanaCondOps is available and the
> sign-extract is operating on bits 10:0 (bit 11
> can't be reached, as the immediate is
> sign-extended)
> - slli + srli + and, otherwise.
>
> gcc/ChangeLog:
>
> * config/riscv/zicond.md: Recognize SIGN_EXTRACT of a
> single-bit followed by AND for Zicond.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zicond-le-01.c: New test.
Conceptually OK. In fact using bext to drive if conversions is
something I think we've got in our queue of things to investigate here.
So you may have just made Raphael's work easier ;-)
As with the other patches we just need to adjust to using the
if-then-else form. You've got a mention of XVentanaCondOps in the
comments, you might want to change that to zicond.
jeff
next prev parent reply other threads:[~2023-04-21 19:40 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 22:41 [RFC PATCH v1 00/10] RISC-V: Support the Zicond (conditional-operations) extension Philipp Tomsich
2023-02-10 22:41 ` [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Philipp Tomsich
2023-02-10 23:18 ` Andrew Pinski
2023-02-10 22:41 ` [RFC PATCH v1 02/10] RISC-V: Recognize Zicond (conditional operations) extension Philipp Tomsich
2023-04-20 17:44 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion Philipp Tomsich
2023-04-20 17:53 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 04/10] RISC-V: Support immediates in Zicond Philipp Tomsich
2023-04-20 18:00 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Philipp Tomsich
2023-04-21 19:31 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Philipp Tomsich
2023-04-21 19:40 ` Jeff Law [this message]
2023-02-10 22:41 ` [RFC PATCH v1 07/10] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2023-04-21 19:56 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2023-02-10 23:07 ` Andrew Pinski
2023-02-13 17:32 ` Richard Sandiford
2023-02-13 18:43 ` Jeff Law
2023-02-13 18:53 ` Andrew Pinski
2023-02-13 7:31 ` Jeff Law
2023-02-28 16:42 ` Maciej W. Rozycki
2023-03-11 15:50 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 09/10] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2023-04-21 19:57 ` Jeff Law
2023-04-25 9:53 ` Kito Cheng
2023-04-25 10:15 ` Philipp Tomsich
2023-04-25 10:43 ` Kito Cheng
2023-04-26 2:28 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 10/10] RISC-V: Support XVentanaCondOps extension Philipp Tomsich
2023-04-21 19:58 ` Jeff Law
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