Re: [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez

[Jeff Law <jeffreyalaw@gmail.com>]

On 2/10/23 15:41, Philipp Tomsich wrote:
> When if-conversion in noce_try_store_flag_mask starts the sequence off
> with an order-operator, our patterns for czero.eqz/nez will receive
> the result of the order-operator as a register argument; consequently,
> they can't know that the result will be either 1 or 0.
> 
> To convey this information (and make czero.eqz/nez applicable), we
> wrap the result of the order-operator in a eq/ne against (const_int 0).
> This commit adds the split pattern to handle these cases.
> 
> During if-conversion, if noce_try_store_flag_mask succeeds, we may see
>      if (cur < next) {
> 	next = 0;
>      }
> transformed into
>     27: r82:SI=ltu(r76:DI,r75:DI)
>        REG_DEAD r76:DI
>     28: r81:SI=r82:SI^0x1
>        REG_DEAD r82:SI
>     29: r80:DI=zero_extend(r81:SI)
>        REG_DEAD r81:SI
> 
> This currently escapes the combiner, as RISC-V does not have a pattern
> to apply the 'slt' instruction to 'geu' verbs.  By adding a pattern in
> this commit, we match such cases.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/predicates.md (anyge_operator): Define.
> 	(anygt_operator): Same.
> 	(anyle_operator): Same.
> 	(anylt_operator): Same.
> 	* config/riscv/riscv.md: Helpers for ge(u) & le(u).
> 	* config/riscv/zicond.md: Add split to wrap an an
> 	order-operator suitably for generating czero.eqz/nez
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zicond-le-02.c: New test.
> 	* gcc.target/riscv/zicond-lt-03.c: New test.
Conceptually OK.  As has been noted, we need to switch to the 
if-then_else form rather than (and (neg)).    OK with that change.

jeff