From: Andrew Pinski <pinskia@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns
Date: Fri, 10 Feb 2023 15:18:22 -0800 [thread overview]
Message-ID: <CA+=Sn1kL_X+GsrDonLBXRpYN8B_imj89viwEKse_OkuqXxBd5g@mail.gmail.com> (raw)
In-Reply-To: <20230210224150.2801962-2-philipp.tomsich@vrull.eu>
On Fri, Feb 10, 2023 at 2:43 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> On RISC-V, conditional-zero (i.e., move a register value or zero to a
> destination register) instructions are part if the Zicond extension.
> To support architectures that have similar constructs, we define a
> canonical RTL representation that can be used in if-conversion.
This is seems like worse canonical form than say:
(define_insn ""
[(set (match_operand:m 0 ...)
(if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0))
(match_operand:m 2 ...)
(const_int 0)
))]
"..."
"...")
(define_insn ""
[(set (match_operand:m 0 ...)
(if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0))
(const_int 0)
(match_operand:m 2 ...)
))]
"..."
"...")
Why can't you use the above form instead? This is the standard way of
expressing condition moves of 0.
This matches even what aarch64 form is already:
(define_insn "*cmov<mode>_insn"
[(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r")
(if_then_else:ALLI
(match_operator 1 "aarch64_comparison_operator"
[(match_operand 2 "cc_register" "") (const_int 0)])
(match_operand:ALLI 3 "aarch64_reg_zero_or_m1_or_1"
"rZ,rZ,UsM,rZ,Ui1,UsM,Ui1")
(match_operand:ALLI 4 "aarch64_reg_zero_or_m1_or_1"
"rZ,UsM,rZ,Ui1,rZ,UsM,Ui1")))]
"!((operands[3] == const1_rtx && operands[4] == constm1_rtx)
|| (operands[3] == constm1_rtx && operands[4] == const1_rtx))"
;; Final two alternatives should be unreachable, but included for completeness
"..."
[(set_attr "type" "csel, csel, csel, csel, csel, mov_imm, mov_imm")]
)
(Which is more complex as it can handle even more than just the simple
case you provide).
Thanks,
Andrew Pinski
> +(define_insn ""
> + [(set (match_operand:@var{m} 0 @dots{})
> + (and:@var{m}
> + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{})
> + (const_int 0)))
> + (match_operand:@var{m} 2 @dots{})))]
> + "@dots{}"
> + "@dots{}")
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> gcc/doc/md.texi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 7235d34c4b3..579462ea67f 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -8347,6 +8347,23 @@ operand of @code{mult} is also a shift, then that is extended also.
> This transformation is only applied when it can be proven that the
> original operation had sufficient precision to prevent overflow.
>
> +@cindex @code{conditional-zero}, canonicalization of
> +@item
> +A machine that has an instruction that performs a conditional-zero
> +operation (i.e., an instruction that moves a register value or puts 0
> +into the destination register) should specify the pattern for that
> +instruction as:
> +@smallexample
> +(define_insn ""
> + [(set (match_operand:@var{m} 0 @dots{})
> + (and:@var{m}
> + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{})
> + (const_int 0)))
> + (match_operand:@var{m} 2 @dots{})))]
> + "@dots{}"
> + "@dots{}")
> +@end smallexample
> +
> @end itemize
>
> Further canonicalization rules are defined in the function
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-02-10 23:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 22:41 [RFC PATCH v1 00/10] RISC-V: Support the Zicond (conditional-operations) extension Philipp Tomsich
2023-02-10 22:41 ` [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Philipp Tomsich
2023-02-10 23:18 ` Andrew Pinski [this message]
2023-02-10 22:41 ` [RFC PATCH v1 02/10] RISC-V: Recognize Zicond (conditional operations) extension Philipp Tomsich
2023-04-20 17:44 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion Philipp Tomsich
2023-04-20 17:53 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 04/10] RISC-V: Support immediates in Zicond Philipp Tomsich
2023-04-20 18:00 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Philipp Tomsich
2023-04-21 19:31 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Philipp Tomsich
2023-04-21 19:40 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 07/10] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2023-04-21 19:56 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2023-02-10 23:07 ` Andrew Pinski
2023-02-13 17:32 ` Richard Sandiford
2023-02-13 18:43 ` Jeff Law
2023-02-13 18:53 ` Andrew Pinski
2023-02-13 7:31 ` Jeff Law
2023-02-28 16:42 ` Maciej W. Rozycki
2023-03-11 15:50 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 09/10] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2023-04-21 19:57 ` Jeff Law
2023-04-25 9:53 ` Kito Cheng
2023-04-25 10:15 ` Philipp Tomsich
2023-04-25 10:43 ` Kito Cheng
2023-04-26 2:28 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 10/10] RISC-V: Support XVentanaCondOps extension Philipp Tomsich
2023-04-21 19:58 ` Jeff Law
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