From: Jeff Law <jeffreyalaw@gmail.com>
To: Andrew Pinski via Gcc-patches <gcc-patches@gcc.gnu.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Andrew Pinski <pinskia@gmail.com>,
Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Vineet Gupta <vineetg@rivosinc.com>,
richard.sandiford@arm.com
Subject: Re: [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions
Date: Mon, 13 Feb 2023 11:43:54 -0700 [thread overview]
Message-ID: <bb141348-b029-df52-28c5-fe6e9ac831d1@gmail.com> (raw)
In-Reply-To: <mptmt5hwjx9.fsf@arm.com>
On 2/13/23 10:32, Richard Sandiford via Gcc-patches wrote:
> Andrew Pinski via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>> On Fri, Feb 10, 2023 at 2:47 PM Philipp Tomsich
>> <philipp.tomsich@vrull.eu> wrote:
>>>
>>> Some architectures, as it the case on RISC-V with the proposed
>>> ZiCondOps and the vendor-defined XVentanaCondOps, define a
>>> conditional-zero instruction that is equivalent to:
>>> - the positive form: rd = (rc != 0) ? rs : 0
>>> - the negated form: rd = (rc == 0) ? rs : 0
>>>
>>> While noce_try_store_flag_mask will somewhat work for this case, it
>>> will generate a number of atomic RTX that will misdirect the cost
>>> calculation and may be too long (i.e., 4 RTX and more) to successfully
>>> merge at combine-time.
>>
>> Can you expand on this? Especially when there are patterns that use
>> (if_then_else) already.
>>
>>>
>>> Instead, we add two new transforms that attempt to build up what we
>>> define as the canonical form of a conditional-zero expression:
>>>
>>> (set (match_operand 0 "register_operand" "=r")
>>> (and (neg (eq_or_ne (match_operand 1 "register_operand" "r")
>>> (const_int 0)))
>>> (match_operand 2 "register_operand" "r")))
>>
>> Again why are you not using:
>> (set (reg) (if_then_else (eq_ne (reg) (const_int 0)) (reg) (const_int 0)))
>> Form instead of the really bad "canonical" form of the above?
>
> I don't think one form is inherently better than the other if we think
> about just this one case. But I agree that the if_then_else form is
> currently the canonical form for the operation, and extends more
> naturally to the general case. AArch64 already matches specifically
> for it (with xzr providing the zero value).
The more I think about it, the more I prefer the if-then-else form. My
biggest hesitation with getting behind one form or the other is a lack
of knowledge about which is likely better interpreted by simplify-rtx
and friends -- though it may not matter much in practice.
Jeff
next prev parent reply other threads:[~2023-02-13 18:43 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 22:41 [RFC PATCH v1 00/10] RISC-V: Support the Zicond (conditional-operations) extension Philipp Tomsich
2023-02-10 22:41 ` [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Philipp Tomsich
2023-02-10 23:18 ` Andrew Pinski
2023-02-10 22:41 ` [RFC PATCH v1 02/10] RISC-V: Recognize Zicond (conditional operations) extension Philipp Tomsich
2023-04-20 17:44 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion Philipp Tomsich
2023-04-20 17:53 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 04/10] RISC-V: Support immediates in Zicond Philipp Tomsich
2023-04-20 18:00 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Philipp Tomsich
2023-04-21 19:31 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Philipp Tomsich
2023-04-21 19:40 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 07/10] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2023-04-21 19:56 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2023-02-10 23:07 ` Andrew Pinski
2023-02-13 17:32 ` Richard Sandiford
2023-02-13 18:43 ` Jeff Law [this message]
2023-02-13 18:53 ` Andrew Pinski
2023-02-13 7:31 ` Jeff Law
2023-02-28 16:42 ` Maciej W. Rozycki
2023-03-11 15:50 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 09/10] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2023-04-21 19:57 ` Jeff Law
2023-04-25 9:53 ` Kito Cheng
2023-04-25 10:15 ` Philipp Tomsich
2023-04-25 10:43 ` Kito Cheng
2023-04-26 2:28 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 10/10] RISC-V: Support XVentanaCondOps extension Philipp Tomsich
2023-04-21 19:58 ` Jeff Law
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