From: Jeff Law <jeffreyalaw@gmail.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>,
gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions
Date: Sat, 11 Mar 2023 08:50:33 -0700 [thread overview]
Message-ID: <81fe4dec-9dca-0041-13d2-5acc39ecab53@gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2302281637440.40278@angie.orcam.me.uk>
On 2/28/23 09:42, Maciej W. Rozycki wrote:
> On Mon, 13 Feb 2023, Jeff Law via Gcc-patches wrote:
>
>> 3. The canaonical conditional-zero-or-value assumes the target can do a
>> generic SEQ/SNE of two register values. As you know, on RISC-V we have
>> SEQZ/SNEZ. So we've added another fallback path to handle that case in
>> noce_emit_condzero. You subtract the two values, then you can do an SEQZ/SNEZ
>> on the result.
>
> NB these machine operations are identical to MIPSr6 SELEQZ and SELNEZ
> instructions (cf. ISA_HAS_SEL), so why can't we just duplicate what the
> MIPS backend does? Or did the MIPS backend do something wrong here?
That's the form that Andrew (and subsequently I) both suggested using.
Switching to that form may in turn make some of these other issues go away.
jeff
next prev parent reply other threads:[~2023-03-11 15:50 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 22:41 [RFC PATCH v1 00/10] RISC-V: Support the Zicond (conditional-operations) extension Philipp Tomsich
2023-02-10 22:41 ` [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Philipp Tomsich
2023-02-10 23:18 ` Andrew Pinski
2023-02-10 22:41 ` [RFC PATCH v1 02/10] RISC-V: Recognize Zicond (conditional operations) extension Philipp Tomsich
2023-04-20 17:44 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion Philipp Tomsich
2023-04-20 17:53 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 04/10] RISC-V: Support immediates in Zicond Philipp Tomsich
2023-04-20 18:00 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Philipp Tomsich
2023-04-21 19:31 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Philipp Tomsich
2023-04-21 19:40 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 07/10] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2023-04-21 19:56 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2023-02-10 23:07 ` Andrew Pinski
2023-02-13 17:32 ` Richard Sandiford
2023-02-13 18:43 ` Jeff Law
2023-02-13 18:53 ` Andrew Pinski
2023-02-13 7:31 ` Jeff Law
2023-02-28 16:42 ` Maciej W. Rozycki
2023-03-11 15:50 ` Jeff Law [this message]
2023-02-10 22:41 ` [RFC PATCH v1 09/10] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2023-04-21 19:57 ` Jeff Law
2023-04-25 9:53 ` Kito Cheng
2023-04-25 10:15 ` Philipp Tomsich
2023-04-25 10:43 ` Kito Cheng
2023-04-26 2:28 ` Jeff Law
2023-02-10 22:41 ` [RFC PATCH v1 10/10] RISC-V: Support XVentanaCondOps extension Philipp Tomsich
2023-04-21 19:58 ` Jeff Law
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