Re: [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion

[Jeff Law <jeffreyalaw@gmail.com>]

On 2/10/23 15:41, Philipp Tomsich wrote:
> Adds a pattern to map the output of noce_try_store_flag_mask
> if-conversion in the combiner onto vt.maskc<n>; the input patterns
> supported are similar to the following:
>    (set (reg/v/f:DI 75 [ <retval> ])
>         (and:DI (neg:DI (ne:DI (reg:DI 82)
> 		       (const_int 0 [0])))
> 	       (reg/v/f:DI 75 [ <retval> ])))
> 
> To ensure that the combine-pass doesn't get confused about
> profitability, we recognize the idiom as requiring a single
> instruction when the Zicond extension is present.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_rtx_costs): Recongnize the idiom
> 	for conditional-zero as a single instruction for TARGET_ZICOND
> 	* config/riscv/riscv.md: Include zicond.md.
> 	* config/riscv/zicond.md: New file.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zicond-ne-03.c: New test.
> 	* gcc.target/riscv/zicond-ne-04.c: New test.
So as we've discussed earlier on the list.  Conceptually I think we've 
agreed that an if-then-else style of conditional zero is probably a 
better model.

So that will have some impact on this patch since it digs into the RTL 
looking for the (and (neg ...)) form.   But I don't think it changes 
anything conceptually in this patch, just the implementation details.

So I'm OK with this patch once it's updated for the updated form we want 
to be using.

jeff