[PATCH 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

[PATCH 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

The current description of RISCV_CORE() does not match the
implementation. This commit provides a fix for that.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Fix comment.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index ecb5e213d98..60bcadbb034 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -21,15 +21,13 @@
 
    Before using #include to read this file, define a macro:
 
-      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
+      RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO)
 
    The CORE_NAME is the name of the core, represented as a string.
-   The ARCH is the default arch of the core, represented as a string,
-   can be NULL if no default arch.
-   The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.
-   The TUNE_INFO is the detail cost model for this core, represented as an
-   identifier, reference to riscv-tunes.def.  */
+   The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i"
+   or "rv64gc_zifencei").
+   The TUNE_INFO is a string that references the detail tuning information
+   for this core (refer to riscv_tune_info_table for possible values).  */
 
 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
-- 
2.35.3

[PATCH 2/2] riscv-cores.def: Add Allwinner D1 core

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This adds Allwinner's D1 to the list of known cores.
The Allwinner includes a single-core XuanTie C906 and is available
for quite some time. Note, that the tuning struct for the C906
is already part of GCC.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 60bcadbb034..dd97ece376f 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
+RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
+
 #undef RISCV_CORE
-- 
2.35.3

Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core

[Christoph Müllner]

On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This adds Allwinner's D1 to the list of known cores.
> The Allwinner includes a single-core XuanTie C906 and is available
> for quite some time. Note, that the tuning struct for the C906
> is already part of GCC.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-cores.def | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> index 60bcadbb034..dd97ece376f 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
>  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
>  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
>
> +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")


I just realized that this lacks a test case (other -mcpu=... entries have one).
And the core string is wrong (s/thead-c906/allwinner-d1).
I will send a v2.

> +
>  #undef RISCV_CORE
> --
> 2.35.3
>

Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core

[Philipp Tomsich]

On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This adds Allwinner's D1 to the list of known cores.
> > The Allwinner includes a single-core XuanTie C906 and is available
> > for quite some time. Note, that the tuning struct for the C906
> > is already part of GCC.
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >  gcc/config/riscv/riscv-cores.def | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > index 60bcadbb034..dd97ece376f 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++ b/gcc/config/riscv/riscv-cores.def
> > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> >
> > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
>
>
> I just realized that this lacks a test case (other -mcpu=... entries have one).
> And the core string is wrong (s/thead-c906/allwinner-d1).
> I will send a v2.

Is the D1 different from the C906? I thought the D1 was using the C906 core?

Philipp.

Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core

[Christoph Müllner]

On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> <christoph.muellner@vrull.eu> wrote:
> >
> > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> > <christoph.muellner@vrull.eu> wrote:
> > >
> > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > >
> > > This adds Allwinner's D1 to the list of known cores.
> > > The Allwinner includes a single-core XuanTie C906 and is available
> > > for quite some time. Note, that the tuning struct for the C906
> > > is already part of GCC.
> > >
> > > gcc/ChangeLog:
> > >
> > >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> > >
> > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >  gcc/config/riscv/riscv-cores.def | 2 ++
> > >  1 file changed, 2 insertions(+)
> > >
> > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > > index 60bcadbb034..dd97ece376f 100644
> > > --- a/gcc/config/riscv/riscv-cores.def
> > > +++ b/gcc/config/riscv/riscv-cores.def
> > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> > >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> > >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> > >
> > > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
> >
> >
> > I just realized that this lacks a test case (other -mcpu=... entries have one).
> > And the core string is wrong (s/thead-c906/allwinner-d1).
> > I will send a v2.
>
> Is the D1 different from the C906? I thought the D1 was using the C906 core?

Yes, that's the case.
I'll stick with "thead-c906" as core name for the v2.
Thanks!

Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core

[Philipp Tomsich]

Please update the commit message to reflect this.

On Wed, 15 Jun 2022 at 10:56, Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> > <christoph.muellner@vrull.eu> wrote:
> > >
> > > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> > > <christoph.muellner@vrull.eu> wrote:
> > > >
> > > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > > >
> > > > This adds Allwinner's D1 to the list of known cores.
> > > > The Allwinner includes a single-core XuanTie C906 and is available
> > > > for quite some time. Note, that the tuning struct for the C906
> > > > is already part of GCC.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> > > >
> > > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > > ---
> > > >  gcc/config/riscv/riscv-cores.def | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > >
> > > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > > > index 60bcadbb034..dd97ece376f 100644
> > > > --- a/gcc/config/riscv/riscv-cores.def
> > > > +++ b/gcc/config/riscv/riscv-cores.def
> > > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> > > >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> > > >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> > > >
> > > > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
> > >
> > >
> > > I just realized that this lacks a test case (other -mcpu=... entries have one).
> > > And the core string is wrong (s/thead-c906/allwinner-d1).
> > > I will send a v2.
> >
> > Is the D1 different from the C906? I thought the D1 was using the C906 core?
>
> Yes, that's the case.
> I'll stick with "thead-c906" as core name for the v2.
> Thanks!