From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Kito Cheng <kito.cheng@gmail.com>,
Jeff Law <jlaw@ventanamicro.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Date: Sat, 12 Nov 2022 22:29:40 +0100 [thread overview]
Message-ID: <20221112212943.3068249-5-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu>
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 7930ef1d837..3e9d5833a4b 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -73,3 +73,49 @@
"TARGET_XVENTANACONDOPS"
[(set (match_dup 5) (match_dup 1))
(set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0)))
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
+
--
2.34.1
next prev parent reply other threads:[~2022-11-12 21:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-12 21:29 [PATCH 0/7] RISC-V: Backend support for XVentanaCondOps/ZiCondops Philipp Tomsich
2022-11-12 21:29 ` [PATCH 1/7] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-17 22:46 ` Jeff Law
2022-11-12 21:29 ` [PATCH 2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-17 22:49 ` Jeff Law
2022-11-12 21:29 ` [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-17 23:12 ` Jeff Law
2022-11-12 21:29 ` Philipp Tomsich [this message]
2022-11-17 23:41 ` [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Jeff Law
2022-11-17 23:56 ` Palmer Dabbelt
2022-11-18 0:10 ` Philipp Tomsich
2022-11-18 14:34 ` Jeff Law
2022-11-18 14:41 ` Philipp Tomsich
2022-11-18 0:08 ` Philipp Tomsich
2022-11-12 21:29 ` [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-17 23:17 ` Jeff Law
2022-11-12 21:29 ` [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-17 23:36 ` Jeff Law
2022-11-12 21:29 ` [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2022-11-12 21:47 ` Andrew Pinski
2022-11-12 22:01 ` Philipp Tomsich
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