From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Kito Cheng <kito.cheng@gmail.com>,
Jeff Law <jlaw@ventanamicro.com>
Subject: Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Date: Thu, 17 Nov 2022 16:41:26 -0700 [thread overview]
Message-ID: <ee69fdc1-f75f-e073-3216-9f974850be5b@gmail.com> (raw)
In-Reply-To: <20221112212943.3068249-5-philipp.tomsich@vrull.eu>
On 11/12/22 14:29, Philipp Tomsich wrote:
> Users might use explicit arithmetic operations to create a mask and
> then and it, in a sequence like
> cond = (bits >> SHIFT) & 1;
> mask = ~(cond - 1);
> val &= mask;
> which will present as a single-bit sign-extract.
>
> Dependening on what combination of XVentanaCondOps and Zbs are
> available, this will map to the following sequences:
> - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
> - andi + vt.maskc, if only XVentanaCondOps is available and the
> sign-extract is operating on bits 10:0 (bit
> 11 can't be reached, as the immediate is
> sign-extended)
> - slli + srli + and, otherwise.
>
> gcc/ChangeLog:
>
> * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
> of a single-bit followed by AND for XVentanaCondOps.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
> index 7930ef1d837..3e9d5833a4b 100644
> --- a/gcc/config/riscv/xventanacondops.md
> +++ b/gcc/config/riscv/xventanacondops.md
> @@ -73,3 +73,49 @@
> "TARGET_XVENTANACONDOPS"
> [(set (match_dup 5) (match_dup 1))
> (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0)))
> +
> +;; Users might use explicit arithmetic operations to create a mask and
> +;; then and it, in a sequence like
Nit. Seems like a word is missing. "make and then and it"??
Do we really care about TARGET_XVENTANACONDOPS && ! TARGET_ZBS?
If there's a good reason to care about the !TARGET_ZBS case, then OK
with the nit fixed. If we agree that the !TARGET_ZBS case isn't all
that important, then obviously OK with that pattern removed too.
I'm about out of oomph today. I may take a look at 7/7 tonight though.
Given it hits target independent code we probably want to get resolution
on that patch sooner rather than later.
jeff
next prev parent reply other threads:[~2022-11-17 23:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-12 21:29 [PATCH 0/7] RISC-V: Backend support for XVentanaCondOps/ZiCondops Philipp Tomsich
2022-11-12 21:29 ` [PATCH 1/7] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-17 22:46 ` Jeff Law
2022-11-12 21:29 ` [PATCH 2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-17 22:49 ` Jeff Law
2022-11-12 21:29 ` [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-17 23:12 ` Jeff Law
2022-11-12 21:29 ` [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Philipp Tomsich
2022-11-17 23:41 ` Jeff Law [this message]
2022-11-17 23:56 ` Palmer Dabbelt
2022-11-18 0:10 ` Philipp Tomsich
2022-11-18 14:34 ` Jeff Law
2022-11-18 14:41 ` Philipp Tomsich
2022-11-18 0:08 ` Philipp Tomsich
2022-11-12 21:29 ` [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-17 23:17 ` Jeff Law
2022-11-12 21:29 ` [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-17 23:36 ` Jeff Law
2022-11-12 21:29 ` [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2022-11-12 21:47 ` Andrew Pinski
2022-11-12 22:01 ` Philipp Tomsich
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