From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Kito Cheng <kito.cheng@gmail.com>,
Jeff Law <jlaw@ventanamicro.com>
Subject: Re: [PATCH 1/7] RISC-V: Recognize xventanacondops extension
Date: Thu, 17 Nov 2022 15:46:34 -0700 [thread overview]
Message-ID: <d8ce579d-40d8-00ec-6a13-1dde98c3eb34@gmail.com> (raw)
In-Reply-To: <20221112212943.3068249-2-philipp.tomsich@vrull.eu>
On 11/12/22 14:29, Philipp Tomsich wrote:
> This adds the xventanacondops extension to the option parsing and as a
> default for the ventana-vt1 core:
>
> gcc/Changelog:
>
> * common/config/riscv/riscv-common.cc: Recognize
> "xventanacondops" as part of an architecture string.
> * config/riscv/riscv-cores.def (RISCV_CORE): Enable
> "xventanacondops" by default for "ventana-vt1".
> * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
> (TARGET_XVENTANACONDOPS): Define.
> * config/riscv/riscv.opt: Add "riscv_xventanacondops".
OK once we've cleared the non-technical hurdles to committing vendor
specific extensions.
Jeff
next prev parent reply other threads:[~2022-11-17 22:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-12 21:29 [PATCH 0/7] RISC-V: Backend support for XVentanaCondOps/ZiCondops Philipp Tomsich
2022-11-12 21:29 ` [PATCH 1/7] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-17 22:46 ` Jeff Law [this message]
2022-11-12 21:29 ` [PATCH 2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-17 22:49 ` Jeff Law
2022-11-12 21:29 ` [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-17 23:12 ` Jeff Law
2022-11-12 21:29 ` [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Philipp Tomsich
2022-11-17 23:41 ` Jeff Law
2022-11-17 23:56 ` Palmer Dabbelt
2022-11-18 0:10 ` Philipp Tomsich
2022-11-18 14:34 ` Jeff Law
2022-11-18 14:41 ` Philipp Tomsich
2022-11-18 0:08 ` Philipp Tomsich
2022-11-12 21:29 ` [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-17 23:17 ` Jeff Law
2022-11-12 21:29 ` [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-17 23:36 ` Jeff Law
2022-11-12 21:29 ` [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2022-11-12 21:47 ` Andrew Pinski
2022-11-12 22:01 ` Philipp Tomsich
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