From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Kito Cheng <kito.cheng@gmail.com>,
Jeff Law <jlaw@ventanamicro.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH 0/7] RISC-V: Backend support for XVentanaCondOps/ZiCondops
Date: Sat, 12 Nov 2022 22:29:36 +0100 [thread overview]
Message-ID: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> (raw)
Both the XVentanaCondOps (a vendor-defined extension from Ventana
Microsystems) and the proposed ZiCondOps extensions define a
conditional-zero(-or-value) instruction, which is similar to the
following C construct:
rd = rc ? rs : 0
This functionality can be tied back into if-convertsion and also match
some typical programming idioms. This series includes backend support
for XVentanaCondops and infrastructure to handle conditional-zero
constructions in if-conversion.
Tested against SPEC CPU 2017.
Philipp Tomsich (7):
RISC-V: Recognize xventanacondops extension
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
RISC-V: Recognize bexti in negated if-conversion
RISC-V: Support immediates in XVentanaCondOps
ifcvt: add if-conversion to conditional-zero instructions
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/predicates.md | 12 +
gcc/config/riscv/riscv-opts.h | 3 +
gcc/config/riscv/riscv.cc | 14 ++
gcc/config/riscv/riscv.md | 27 +++
gcc/config/riscv/riscv.opt | 3 +
gcc/config/riscv/xventanacondops.md | 150 ++++++++++++
gcc/ifcvt.cc | 214 ++++++++++++++++++
.../gcc.target/riscv/xventanacondops-and-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-and-02.c | 15 ++
.../gcc.target/riscv/xventanacondops-eq-01.c | 11 +
.../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++
.../riscv/xventanacondops-ifconv-imm.c | 19 ++
.../gcc.target/riscv/xventanacondops-le-01.c | 17 ++
.../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-lt-03.c | 17 ++
.../gcc.target/riscv/xventanacondops-ne-01.c | 11 +
.../gcc.target/riscv/xventanacondops-ne-03.c | 15 ++
.../gcc.target/riscv/xventanacondops-ne-04.c | 15 ++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++
20 files changed, 605 insertions(+)
create mode 100644 gcc/config/riscv/xventanacondops.md
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
--
2.34.1
next reply other threads:[~2022-11-12 21:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-12 21:29 Philipp Tomsich [this message]
2022-11-12 21:29 ` [PATCH 1/7] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-17 22:46 ` Jeff Law
2022-11-12 21:29 ` [PATCH 2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-17 22:49 ` Jeff Law
2022-11-12 21:29 ` [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-17 23:12 ` Jeff Law
2022-11-12 21:29 ` [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Philipp Tomsich
2022-11-17 23:41 ` Jeff Law
2022-11-17 23:56 ` Palmer Dabbelt
2022-11-18 0:10 ` Philipp Tomsich
2022-11-18 14:34 ` Jeff Law
2022-11-18 14:41 ` Philipp Tomsich
2022-11-18 0:08 ` Philipp Tomsich
2022-11-12 21:29 ` [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-17 23:17 ` Jeff Law
2022-11-12 21:29 ` [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-17 23:36 ` Jeff Law
2022-11-12 21:29 ` [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
2022-11-12 21:47 ` Andrew Pinski
2022-11-12 22:01 ` Philipp Tomsich
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