* [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
@ 2023-08-03 9:27 juzhe.zhong
2023-08-03 13:49 ` Jeff Law
0 siblings, 1 reply; 15+ messages in thread
From: juzhe.zhong @ 2023-08-03 9:27 UTC (permalink / raw)
To: gcc-patches; +Cc: Kito.cheng, kito.cheng, Robin Dapp, zengxiao, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 16504 bytes --]
https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d7666195e9db65581364ad5e5df
This patch causes so many fails in the regression:
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O1 scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-79.c -Os scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*mf2,\\s*tu,\\s*mu 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vle64\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 8
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c -O1 scan-assembler-times \\.L[0-9]+\\:\\s+add\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[a-x0-9]+\\s+vle8\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf2,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c -Os scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vle64\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-80.c -Os scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*mf2,\\s*tu,\\s*mu 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]:+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c -Os scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-72.c -Os scan-assembler-times vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e32,\\s*mf2,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-72.c -Os scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c -Os scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c -Os scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c -O2 scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c -O1 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c -O1 scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c -Os scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvl-6.c -O1 scan-assembler-times \\.L[0-9]+\\:\\s+vle32\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 2
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c (internal compiler error: internal consistency failure)
FAIL: gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 5
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times j\\s+\\.L[0-9]+\\s+\\.L[0-9]+:\\s+vlm\\.v 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*m8,\\s*t[au],\\s*m[au] 3
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c -Os scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c -O2 scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/autovec/conversions/vzext-run.c (internal compiler error: internal consistency failure)
FAIL: gcc.target/riscv/rvv/autovec/conversions/vzext-run.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 7
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvl-7.c -Os scan-assembler-times vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vle16\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 12
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvl-8.c -O1 scan-assembler-times \\.L[0-9]+\\:\\s+vle32\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-40.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e8,\\s*mf8,\\s*tu,\\s*m[au]\\s+vle8\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/vsetvl/vsetvl-8.c -Os scan-assembler-times vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e32,\\s*m1,\\s*tu,\\s*m[au] 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c -O1 scan-assembler-times \\.L[0-9]+\\:\\s+add\\s+\\s*[a-x0-9]+,\\s*[a-x0-9]+,\\s*[a-x0-9]+\\s+vle8\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O1 scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vle8\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 14
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+\\: 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c -Os scan-assembler-times \\.L[0-9]+\\:\\s+vle32\\.v\\s+v[0-9]+,\\s*0\\s*\\([a-x0-9]+\\) 10
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+\\: 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[0-9]+ 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-78.c -Os scan-assembler-times vsetivli\\s+zero,\\s*4,\\s*e32,\\s*mf2,\\s*tu,\\s*mu 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-78.c -Os scan-assembler-times vsetivli 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+\\.L[0-9]+\\: 1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]\\s+j\\s+\\.L[
juzhe.zhong@rivai.ai
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 9:27 [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 juzhe.zhong
@ 2023-08-03 13:49 ` Jeff Law
2023-08-03 13:56 ` Kito Cheng
0 siblings, 1 reply; 15+ messages in thread
From: Jeff Law @ 2023-08-03 13:49 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, kito.cheng, Robin Dapp, zengxiao
On 8/3/23 03:27, juzhe.zhong@rivai.ai wrote:
> https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d7666195e9db65581364ad5e5df <https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d7666195e9db65581364ad5e5df>
>
> This patch causes so many fails in the regression:
Mine. I'll take care of it. Probably something slipping through the
expander that shouldn't. I've been primarily focused on the execute.exp
part of the suite to find code correctness issues with the original patch.
jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 13:49 ` Jeff Law
@ 2023-08-03 13:56 ` Kito Cheng
2023-08-03 14:08 ` Jeff Law
0 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2023-08-03 13:56 UTC (permalink / raw)
To: Jeff Law
Cc: 钟居哲, gcc-patches, kito.cheng, Robin Dapp, zengxiao
[-- Attachment #1: Type: text/plain, Size: 771 bytes --]
I am working on that, it seems the cost of vsetvli instruction become 0 due
to this change, then loop invariant motion won't hoist vsetvli longer.
Jeff Law <jeffreyalaw@gmail.com> 於 2023年8月3日 週四 21:49 寫道：
>
>
> On 8/3/23 03:27, juzhe.zhong@rivai.ai wrote:
> >
> https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d7666195e9db65581364ad5e5df
> <
> https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d7666195e9db65581364ad5e5df
> >
> >
> > This patch causes so many fails in the regression:
> Mine. I'll take care of it. Probably something slipping through the
> expander that shouldn't. I've been primarily focused on the execute.exp
> part of the suite to find code correctness issues with the original patch.
>
> jeff
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 13:56 ` Kito Cheng
@ 2023-08-03 14:08 ` Jeff Law
2023-08-03 14:31 ` Kito Cheng
0 siblings, 1 reply; 15+ messages in thread
From: Jeff Law @ 2023-08-03 14:08 UTC (permalink / raw)
To: Kito Cheng
Cc: 钟居哲, gcc-patches, kito.cheng, Robin Dapp, zengxiao
On 8/3/23 07:56, Kito Cheng wrote:
> I am working on that, it seems the cost of vsetvli instruction become 0
> due to this change, then loop invariant motion won't hoist vsetvli longer.
I haven't looked yet (generating baseline rvv.exp data right now). But
before I went to bed last night I was worried that a change snuck
through that shouldn't have (changing the toplevel INSN/SET cost
handling -- that wasn't supposed to be in the commit). I was too tired
to verify and correct without possibly mucking it up further.
That'll be the first thing to look at. THe costing change was supposed
only affect if-then-else constructs, not sets in general.
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 14:08 ` Jeff Law
@ 2023-08-03 14:31 ` Kito Cheng
2023-08-03 14:41 ` Jeff Law
0 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2023-08-03 14:31 UTC (permalink / raw)
To: Jeff Law
Cc: Robin Dapp, gcc-patches, kito.cheng, zengxiao, 钟居哲
> > I am working on that, it seems the cost of vsetvli instruction become 0
> > due to this change, then loop invariant motion won't hoist vsetvli longer.
> I haven't looked yet (generating baseline rvv.exp data right now). But
> before I went to bed last night I was worried that a change snuck
> through that shouldn't have (changing the toplevel INSN/SET cost
> handling -- that wasn't supposed to be in the commit). I was too tired
> to verify and correct without possibly mucking it up further.
>
> That'll be the first thing to look at. THe costing change was supposed
> only affect if-then-else constructs, not sets in general.
If so, I think the most simple fix is adding more checks on the set
cost - only check the SET_SRC is if-then-else?
Let me run the regression to see if that works - although the current
vsetvli cost is too high (4x~5x), but I think it should be fixed later
with a more complete expermantal.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 14:31 ` Kito Cheng
@ 2023-08-03 14:41 ` Jeff Law
2023-08-03 14:56 ` Kito Cheng
0 siblings, 1 reply; 15+ messages in thread
From: Jeff Law @ 2023-08-03 14:41 UTC (permalink / raw)
To: Kito Cheng
Cc: Robin Dapp, gcc-patches, kito.cheng, zengxiao, 钟居哲
On 8/3/23 08:31, Kito Cheng wrote:
>>> I am working on that, it seems the cost of vsetvli instruction become 0
>>> due to this change, then loop invariant motion won't hoist vsetvli longer.
>> I haven't looked yet (generating baseline rvv.exp data right now). But
>> before I went to bed last night I was worried that a change snuck
>> through that shouldn't have (changing the toplevel INSN/SET cost
>> handling -- that wasn't supposed to be in the commit). I was too tired
>> to verify and correct without possibly mucking it up further.
>>
>> That'll be the first thing to look at. THe costing change was supposed
>> only affect if-then-else constructs, not sets in general.
>
>
> If so, I think the most simple fix is adding more checks on the set
> cost - only check the SET_SRC is if-then-else?
No, the simple fix is to just remove the errant part of the commit :-0
My tests aren't done, but that does seem to dramatically help. Given it
wasn't supposed to go in as-is and it's causing major problems, I'll
probably just rip it out even though my testing isn't done.
>
> Let me run the regression to see if that works - although the current
> vsetvli cost is too high (4x~5x), but I think it should be fixed later
> with a more complete expermantal.
Exactly. I think we need to do a full audit of the costing paths. I've
been slowly devising a way to do that and I'll probably give it to
Raphael or Jivan once I've fleshed it out a bit more in my head.
The goal is to make sure the costs are sensible and consistent across
the different interfaces. A cost failure is actually a bit hard to find
because all that happens is you get the wrong set of transformations --
but the code still works correctly, it's just not as efficient as it
should be. It doesn't have to be perfect, but we've clearly got a problem.
WRT vsetvli costing. That may ultimately be something that's uarch
dependent. We're working on the assumption that vsetvlis are common in
the code stream and they need to be very efficient from the hardware
standpoint (think as cheap or cheaper than any simple ALU instruction).
I probably can't say what we're doing, but I bet it wouldn't be a
surprise to others doing a high performance V implementation.
jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 14:41 ` Jeff Law
@ 2023-08-03 14:56 ` Kito Cheng
2023-08-03 15:09 ` Jeff Law
0 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2023-08-03 14:56 UTC (permalink / raw)
To: Jeff Law
Cc: Robin Dapp, gcc-patches, kito.cheng, zengxiao, 钟居哲
> >> That'll be the first thing to look at. THe costing change was supposed
> >> only affect if-then-else constructs, not sets in general.
> >
> >
> > If so, I think the most simple fix is adding more checks on the set
> > cost - only check the SET_SRC is if-then-else?
> No, the simple fix is to just remove the errant part of the commit :-0
> My tests aren't done, but that does seem to dramatically help. Given it
> wasn't supposed to go in as-is and it's causing major problems, I'll
> probably just rip it out even though my testing isn't done.
OK, so I'm going to retreat from there, I've another lld issue that
needs to be fixed before the LLVM 17 release :)
>
> >
> > Let me run the regression to see if that works - although the current
> > vsetvli cost is too high (4x~5x), but I think it should be fixed later
> > with a more complete expermantal.
> Exactly. I think we need to do a full audit of the costing paths. I've
> been slowly devising a way to do that and I'll probably give it to
> Raphael or Jivan once I've fleshed it out a bit more in my head.
>
> The goal is to make sure the costs are sensible and consistent across
> the different interfaces. A cost failure is actually a bit hard to find
> because all that happens is you get the wrong set of transformations --
> but the code still works correctly, it's just not as efficient as it
> should be. It doesn't have to be perfect, but we've clearly got a problem.
>
> WRT vsetvli costing. That may ultimately be something that's uarch
> dependent. We're working on the assumption that vsetvlis are common in
> the code stream and they need to be very efficient from the hardware
> standpoint (think as cheap or cheaper than any simple ALU instruction).
> I probably can't say what we're doing, but I bet it wouldn't be a
> surprise to others doing a high performance V implementation.
Yeah, it should be cheap, but might be expensive on some HW implementation,
anyway our cost model really needs to be tidy up at some point...:P
> jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-08-03 14:56 ` Kito Cheng
@ 2023-08-03 15:09 ` Jeff Law
0 siblings, 0 replies; 15+ messages in thread
From: Jeff Law @ 2023-08-03 15:09 UTC (permalink / raw)
To: Kito Cheng
Cc: Robin Dapp, gcc-patches, kito.cheng, zengxiao, 钟居哲
On 8/3/23 08:56, Kito Cheng wrote:
>>>> That'll be the first thing to look at. THe costing change was supposed
>>>> only affect if-then-else constructs, not sets in general.
>>>
>>>
>>> If so, I think the most simple fix is adding more checks on the set
>>> cost - only check the SET_SRC is if-then-else?
>> No, the simple fix is to just remove the errant part of the commit :-0
>> My tests aren't done, but that does seem to dramatically help. Given it
>> wasn't supposed to go in as-is and it's causing major problems, I'll
>> probably just rip it out even though my testing isn't done.
>
> OK, so I'm going to retreat from there, I've another lld issue that
> needs to be fixed before the LLVM 17 release :)
Reversion of errant hunk has been pushed. Sorry for the problems folks.
Had I known it was going to have this kind of fallout, I would have
slammed a coke and fixed it last night before doing to sleep :-0
And yes, focusing on the lld issue seems wise given what I'm hearing in
the LLVM meeting.
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-29 9:14 ` Xiao Zeng
@ 2023-08-03 4:59 ` Jeff Law
0 siblings, 0 replies; 15+ messages in thread
From: Jeff Law @ 2023-08-03 4:59 UTC (permalink / raw)
To: Xiao Zeng, gcc-patches
Cc: research_trasio, kito.cheng, zhengyu, eri-sw-toolchain
On 7/29/23 03:14, Xiao Zeng wrote:
>
> 1 Thank you for Jeff's code review comments. I have made the modifications
> and submitted the V2-patch[3/5].
Yea. I'm adjusting my tree based on those updates. For testing I've
actually got my compiler generating zicond by default and qemu allowing
zicond by default. I can then run the execute.exp tests which validate
code correctness to a reasonable degree.
>
> 2 For the calculation method of cost, I hope to submit a separate patch[cost]
> after the V2-patch[3/5] merged into master, which will focus on explaining
> the reasons for calculating cost in the same way as in patch[4/5].
I think the costing problem is going to require its own little
subproject. GCC's approach to costing is a bit crazy with multiple APIs
that behave differently and in some cases do some rather surprising
things. It's a long standing design flaw.
The point being that I think we'll probably move forward with the
functional bits, perhaps initially without the basic functionality
tests. That allows folks to start utilizing the core functionality
while we audit and likely adjust the risc-v cost hook implementation.
>
> 4. In V2-patch[3/5], Zicond's cost calculation is not involved, therefore, all test
> cases are skipped with "- O0" and "- Os". I will remove the "- Os" constraint from
> the test case in patch[cost].
We may need to avoid for -Og as well. I've got that change here
locally, but I wanted to go back and review that as well.
jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
` (2 preceding siblings ...)
2023-07-28 20:59 ` Jeff Law
@ 2023-08-02 6:34 ` Jeff Law
3 siblings, 0 replies; 15+ messages in thread
From: Jeff Law @ 2023-08-02 6:34 UTC (permalink / raw)
To: Xiao Zeng, gcc-patches
Cc: research_trasio, kito.cheng, zhengyu, eri-sw-toolchain
[-- Attachment #1: Type: text/plain, Size: 495 bytes --]
On 7/19/23 04:11, Xiao Zeng wrote:
> This patch completes the recognition of Zicond when the select pattern
> with condition eq or neq to 0 (using equality as an example), namely:
[ ... ]
I've committed the attached patch which implements a simple cost model
for using Zicond to implement conditional moves.
I've changed it to give the proper cost (COSTS_N_INSNS (1) and removed
the extraneous GET_CODE (object) tests adjusted the ChangeLog a bit and
pushed it to the trunk.
Thanks!
Jeff
[-- Attachment #2: P --]
[-- Type: text/plain, Size: 1852 bytes --]
commit 5b501863ac7da57858fdd464dfb7a776143f22a2
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date: Wed Aug 2 00:17:12 2023 -0600
[PATCH 3/5] [RISC-V] Cost model for Zicond.
This patch implements a reasonable cost model for using Zicond to
implement conditional moves. Essentially the Zicond insns are always
COSTS_N_INSNS (1).
Note there is still a problem with the costing model in general that
results in failure to if-convert as often as we should. In simplest
terms the insn costing model sums the cost of the SET_SRC and the
cost of the SET_DEST. Thus the conditional move is considered twice
as costly as it should be. That will have to be addressed separately.
gcc/
* config/riscv/riscv.cc (riscv_rtx_costs): Add costing for
using Zicond to implement some conditional moves.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8c474503080..785e09c76ce 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2518,6 +2518,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
+ else if (TARGET_ZICOND
+ && outer_code == SET
+ && ((GET_CODE (XEXP (x, 1)) == REG
+ && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
+ || (GET_CODE (XEXP (x, 2)) == REG
+ && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 2))))
+ || (GET_CODE (XEXP (x, 1)) == REG
+ && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0)))
+ || (GET_CODE (XEXP (x, 1)) == REG
+ && rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0)))))
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
{
if (equality_operator (XEXP (x, 0), mode)
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32 ` Jeff Law
2023-07-25 17:55 ` Andreas Schwab
@ 2023-07-28 20:59 ` Jeff Law
2023-07-29 9:14 ` Xiao Zeng
2023-08-02 6:34 ` Jeff Law
3 siblings, 1 reply; 15+ messages in thread
From: Jeff Law @ 2023-07-28 20:59 UTC (permalink / raw)
To: Xiao Zeng, gcc-patches
Cc: research_trasio, kito.cheng, zhengyu, eri-sw-toolchain
On 7/19/23 04:11, Xiao Zeng wrote:
> + else if (TARGET_ZICOND
> + && (code == EQ || code == NE)
> + && GET_MODE_CLASS (mode) == MODE_INT)
> + {
> + need_eq_ne_p = true;
> + /* 0 + imm */
> + if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
> + && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
> + {
> + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + alt = force_reg (mode, alt);
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + cons, alt)));
> + return true;
> + }
> + /* imm + imm */
> + else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
> + && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
> + {
> + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + alt = force_reg (mode, alt);
> + rtx temp1 = gen_reg_rtx (mode);
> + rtx temp2 = GEN_INT(-1 * INTVAL (cons));
> + riscv_emit_binary(PLUS, temp1, alt, temp2);
So in this sequence you're just computing a constant since both ALT and
CONS are constants. It's better to just form the constant directly,
then force that into a register because it'll make the costing more
correct, particularly if the resulting constant needs more than one
instruction to synthesize.
And a nit. There should always be a space between a function name and
its argument list.
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + const0_rtx, alt)));
> + riscv_emit_binary(PLUS, dest, dest, cons);
> + return true;
I don't see how this can be correct from a code generation standpoint.
You compute ALT-CONS into TEMP1 earlier. But you never use TEMP1 after
that. I think you meant to use TEMP1 instead of ALT as the false arm if
the IF-THEN-ELSE you constructed.
In general you should be using CONST0_RTX (mode) rather than const0_rtx.
> + }
> + /* imm + reg */
> + else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
> + && GET_CODE (alt) == REG)
> + {
> + /* Optimize for register value of 0. */
> + if (op0 == alt && op1 == const0_rtx)
> + {
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + cons = force_reg (mode, cons);
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + cons, alt)));
> + return true;
> + }
> + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + rtx temp1 = gen_reg_rtx (mode);
> + rtx temp2 = GEN_INT(-1 * INTVAL (cons));
> + riscv_emit_binary(PLUS, temp1, alt, temp2);
Here you have to be careful if CONS is -2048. You negate it resulting
in +2048 which can't be used in an addi. This will cause the entire
sequence to fail due to an unrecognized insn. It would be better to
handle that scenario directly so the generated sequence is still valid.
By generating recognizable code in that case we let the costing model
determine if the conditional move sequence is better than the branching
sequence.
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + const0_rtx, alt)));
I think we have the same problem with the use of ALT here rather than
TEMP1 that we had in the previous case.
> + /* reg + imm */
> + else if (GET_CODE (cons) == REG
> + && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
> + {
> + /* Optimize for register value of 0. */
> + if (op0 == cons && op1 == const0_rtx)
> + {
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + alt = force_reg (mode, alt);
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + cons, alt)));
> + return true;
> + }
> + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
> + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + rtx temp1 = gen_reg_rtx (mode);
> + rtx temp2 = GEN_INT(-1 * INTVAL (alt));
> + riscv_emit_binary(PLUS, temp1, cons, temp2);
> + emit_insn (gen_rtx_SET (dest,
> + gen_rtx_IF_THEN_ELSE (mode, cond,
> + temp1, const0_rtx)));
> + riscv_emit_binary(PLUS, dest, dest, alt);
> + return true;
This has basically the same issues as the imm + reg case.
> + }
> + /* reg + reg */
> + else if (GET_CODE (cons) == REG && GET_CODE (alt) == REG)
> + {
> + rtx reg1 = gen_reg_rtx (mode);
> + rtx reg2 = gen_reg_rtx (mode);
> + riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
> + rtx cond1 = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
> + rtx cond2 = gen_rtx_fmt_ee (code == NE ? EQ : NE,
> + GET_MODE (op0), op0, op1);
> + emit_insn (gen_rtx_SET (reg2,
> + gen_rtx_IF_THEN_ELSE (mode, cond2,
> + const0_rtx, cons)));
> + emit_insn (gen_rtx_SET (reg1,
> + gen_rtx_IF_THEN_ELSE (mode, cond1,
> + const0_rtx, alt)));
> + riscv_emit_binary(IOR, dest, reg1, reg2);
> + return true;
This probably should detect the case where alt or cons is the same as
op0. Otherwise I would expect the costing model to reject some cases
that are actually profitable.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6b8c2e8e268..b4147c7a79c 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2484,7 +2484,7 @@
> (if_then_else:GPR (match_operand 1 "comparison_operator")
> (match_operand:GPR 2 "reg_or_0_operand")
> (match_operand:GPR 3 "sfb_alu_operand")))
> - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV"
> + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
Note the predicate for operand2 will reject all constants except 0.
Anyway, I'm still cleaning this up and adding the bits from Ventana
which handle the relational conditions as well as FP conditionals.
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-25 17:55 ` Andreas Schwab
@ 2023-07-28 15:09 ` Jeff Law
0 siblings, 0 replies; 15+ messages in thread
From: Jeff Law @ 2023-07-28 15:09 UTC (permalink / raw)
To: Andreas Schwab, Xiao Zeng
Cc: gcc-patches, research_trasio, kito.cheng, zhengyu, eri-sw-toolchain
On 7/25/23 11:55, Andreas Schwab wrote:
> On Jul 19 2023, Xiao Zeng wrote:
>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 38d8eb2fcf5..7e6b24bd232 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
>> *total = COSTS_N_INSNS (1);
>> return true;
>> }
>> + else if (TARGET_ZICOND && outer_code == SET &&
>> + ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
>> + (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
>> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>> + XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
>> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>> + XEXP (x, 2) == XEXP (XEXP (x, 0), 0))))
>
> Line breaks before the operator, not after.
Also note that && GET_CODE (XEXP (x, 2)) && that appears twice.
That just verifies the code isn't RTX_UNKNOWN which I suspect isn't what
the author intended. It probably needs to be adjusted for SUBREGs and
the pointer equality issues with REGs after reload.
I'll take care of these goofs since the costing ought to be able to move
forward independently of the improvements Xiao made to generating
conditional move sequences.
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32 ` Jeff Law
@ 2023-07-25 17:55 ` Andreas Schwab
2023-07-28 15:09 ` Jeff Law
2023-07-28 20:59 ` Jeff Law
2023-08-02 6:34 ` Jeff Law
3 siblings, 1 reply; 15+ messages in thread
From: Andreas Schwab @ 2023-07-25 17:55 UTC (permalink / raw)
To: Xiao Zeng
Cc: gcc-patches, jeffreyalaw, research_trasio, kito.cheng, zhengyu,
eri-sw-toolchain
On Jul 19 2023, Xiao Zeng wrote:
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 38d8eb2fcf5..7e6b24bd232 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
> *total = COSTS_N_INSNS (1);
> return true;
> }
> + else if (TARGET_ZICOND && outer_code == SET &&
> + ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 2) == XEXP (XEXP (x, 0), 0))))
Line breaks before the operator, not after.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
@ 2023-07-25 17:32 ` Jeff Law
2023-07-25 17:55 ` Andreas Schwab
` (2 subsequent siblings)
3 siblings, 0 replies; 15+ messages in thread
From: Jeff Law @ 2023-07-25 17:32 UTC (permalink / raw)
To: Xiao Zeng, gcc-patches
Cc: research_trasio, kito.cheng, zhengyu, eri-sw-toolchain
On 7/19/23 04:11, Xiao Zeng wrote:
> This patch completes the recognition of Zicond when the select pattern
> with condition eq or neq to 0 (using equality as an example), namely:
>
> 1 rd = (rs2 == 0) ? non-imm : 0
> 2 rd = (rs2 == 0) ? non-imm : non-imm
> 3 rd = (rs2 == 0) ? reg : non-imm
> 4 rd = (rs2 == 0) ? reg : reg
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): IF_THEN_ELSE costs in Zicond.
> (riscv_expand_conditional_move): Recognize Zicond.
> * config/riscv/riscv.md: Zicond patterns.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test.
> * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test.
> * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test.
> * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test.
> ---
> gcc/config/riscv/riscv.cc | 125 ++++++++++++++++++
> gcc/config/riscv/riscv.md | 2 +-
> .../zicond-primitiveSemantics_return_0_imm.c | 65 +++++++++
> ...zicond-primitiveSemantics_return_imm_imm.c | 73 ++++++++++
> ...zicond-primitiveSemantics_return_imm_reg.c | 65 +++++++++
> ...zicond-primitiveSemantics_return_reg_reg.c | 65 +++++++++
> 6 files changed, 394 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 38d8eb2fcf5..7e6b24bd232 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
> *total = COSTS_N_INSNS (1);
> return true;
> }
> + else if (TARGET_ZICOND && outer_code == SET &&
> + ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 2) == XEXP (XEXP (x, 0), 0))))
> + {
> + *total = 0;
> + return true;
> + }
So why *total = 0. I would have expected *total = COSTS_N_INSNS (1).
I'm not entirely sure the changes to riscv_expand_conditional_move are
desirable -- these are likely better done in the generic if-conversion
pass.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6b8c2e8e268..b4147c7a79c 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2484,7 +2484,7 @@
> (if_then_else:GPR (match_operand 1 "comparison_operator")
> (match_operand:GPR 2 "reg_or_0_operand")
> (match_operand:GPR 3 "sfb_alu_operand")))]
> - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV"
> + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
> {
> if (riscv_expand_conditional_move (operands[0], operands[1],
> operands[2], operands[3]))
We had to do more than just slap on a TARGET_ZICOND. I'm a bit
surprised this worked as-is. Though we also have bits to handle
conditions other than eq/ne by first emitting an sCC style insn which
might be adding complication or cases you hadn't encountered.
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
@ 2023-07-19 10:11 ` Xiao Zeng
2023-07-25 17:32 ` Jeff Law
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Xiao Zeng @ 2023-07-19 10:11 UTC (permalink / raw)
To: gcc-patches
Cc: jeffreyalaw, research_trasio, kito.cheng, zhengyu,
eri-sw-toolchain, Xiao Zeng
This patch completes the recognition of Zicond when the select pattern
with condition eq or neq to 0 (using equality as an example), namely:
1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): IF_THEN_ELSE costs in Zicond.
(riscv_expand_conditional_move): Recognize Zicond.
* config/riscv/riscv.md: Zicond patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test.
---
gcc/config/riscv/riscv.cc | 125 ++++++++++++++++++
gcc/config/riscv/riscv.md | 2 +-
.../zicond-primitiveSemantics_return_0_imm.c | 65 +++++++++
...zicond-primitiveSemantics_return_imm_imm.c | 73 ++++++++++
...zicond-primitiveSemantics_return_imm_reg.c | 65 +++++++++
...zicond-primitiveSemantics_return_reg_reg.c | 65 +++++++++
6 files changed, 394 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38d8eb2fcf5..7e6b24bd232 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
+ else if (TARGET_ZICOND && outer_code == SET &&
+ ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
+ (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
+ (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
+ XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
+ (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
+ XEXP (x, 2) == XEXP (XEXP (x, 0), 0))))
+ {
+ *total = 0;
+ return true;
+ }
else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
{
if (equality_operator (XEXP (x, 0), mode)
@@ -3501,6 +3512,120 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
cond, cons, alt)));
return true;
}
+ else if (TARGET_ZICOND
+ && (code == EQ || code == NE)
+ && GET_MODE_CLASS (mode) == MODE_INT)
+ {
+ need_eq_ne_p = true;
+ /* 0 + imm */
+ if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
+ && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+ {
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ alt = force_reg (mode, alt);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, alt)));
+ return true;
+ }
+ /* imm + imm */
+ else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+ && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+ {
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ alt = force_reg (mode, alt);
+ rtx temp1 = gen_reg_rtx (mode);
+ rtx temp2 = GEN_INT(-1 * INTVAL (cons));
+ riscv_emit_binary(PLUS, temp1, alt, temp2);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ const0_rtx, alt)));
+ riscv_emit_binary(PLUS, dest, dest, cons);
+ return true;
+ }
+ /* imm + reg */
+ else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+ && GET_CODE (alt) == REG)
+ {
+ /* Optimize for register value of 0. */
+ if (op0 == alt && op1 == const0_rtx)
+ {
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ cons = force_reg (mode, cons);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, alt)));
+ return true;
+ }
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ rtx temp1 = gen_reg_rtx (mode);
+ rtx temp2 = GEN_INT(-1 * INTVAL (cons));
+ riscv_emit_binary(PLUS, temp1, alt, temp2);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ const0_rtx, alt)));
+ riscv_emit_binary(PLUS, dest, dest, cons);
+ return true;
+ }
+ /* imm + 0 */
+ else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+ && GET_CODE (alt) == CONST_INT && alt == const0_rtx)
+ {
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ cons = force_reg (mode, cons);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, alt)));
+ return true;
+ }
+ /* reg + imm */
+ else if (GET_CODE (cons) == REG
+ && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+ {
+ /* Optimize for register value of 0. */
+ if (op0 == cons && op1 == const0_rtx)
+ {
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ alt = force_reg (mode, alt);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, alt)));
+ return true;
+ }
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ rtx temp1 = gen_reg_rtx (mode);
+ rtx temp2 = GEN_INT(-1 * INTVAL (alt));
+ riscv_emit_binary(PLUS, temp1, cons, temp2);
+ emit_insn (gen_rtx_SET (dest,
+ gen_rtx_IF_THEN_ELSE (mode, cond,
+ temp1, const0_rtx)));
+ riscv_emit_binary(PLUS, dest, dest, alt);
+ return true;
+ }
+ /* reg + reg */
+ else if (GET_CODE (cons) == REG && GET_CODE (alt) == REG)
+ {
+ rtx reg1 = gen_reg_rtx (mode);
+ rtx reg2 = gen_reg_rtx (mode);
+ riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+ rtx cond1 = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ rtx cond2 = gen_rtx_fmt_ee (code == NE ? EQ : NE,
+ GET_MODE (op0), op0, op1);
+ emit_insn (gen_rtx_SET (reg2,
+ gen_rtx_IF_THEN_ELSE (mode, cond2,
+ const0_rtx, cons)));
+ emit_insn (gen_rtx_SET (reg1,
+ gen_rtx_IF_THEN_ELSE (mode, cond1,
+ const0_rtx, alt)));
+ riscv_emit_binary(IOR, dest, reg1, reg2);
+ return true;
+ }
+ }
return false;
}
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6b8c2e8e268..b4147c7a79c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2484,7 +2484,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator")
(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
{
if (riscv_expand_conditional_move (operands[0], operands[1],
operands[2], operands[3]))
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
new file mode 100644
index 00000000000..4948558a187
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
@@ -0,0 +1,65 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+long primitiveSemantics_return_0_imm_00(long a, long b) {
+ return a == 0 ? 0 : 3;
+}
+
+long primitiveSemantics_return_0_imm_01(long a, long b) {
+ return a != 0 ? 0 : 3;
+}
+
+long primitiveSemantics_return_0_imm_02(long a, long b) {
+ return a == 0 ? 3 : 0;
+}
+
+long primitiveSemantics_return_0_imm_03(long a, long b) {
+ return a != 0 ? 3 : 0;
+}
+
+long primitiveSemantics_return_0_imm_04(long a, long b) {
+ if (a)
+ b = 0;
+ else
+ b = 3;
+ return b;
+}
+
+long primitiveSemantics_return_0_imm_05(long a, long b) {
+ if (!a)
+ b = 0;
+ else
+ b = 3;
+ return b;
+}
+
+int primitiveSemantics_return_0_imm_06(int a, int b) { return a == 0 ? 0 : 3; }
+
+int primitiveSemantics_return_0_imm_07(int a, int b) { return a != 0 ? 0 : 3; }
+
+int primitiveSemantics_return_0_imm_08(int a, int b) { return a == 0 ? 3 : 0; }
+
+int primitiveSemantics_return_0_imm_09(int a, int b) { return a != 0 ? 3 : 0; }
+
+int primitiveSemantics_return_0_imm_10(int a, int b) {
+ if (a)
+ b = 0;
+ else
+ b = 3;
+ return b;
+}
+
+int primitiveSemantics_return_0_imm_11(int a, int b) {
+ if (!a)
+ b = 0;
+ else
+ b = 3;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */
+/* { dg-final { scan-assembler-times "czero.nez" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
new file mode 100644
index 00000000000..ebdca521373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */
+
+long primitiveSemantics_return_imm_imm_00(long a, long b) {
+ return a == 0 ? 4 : 6;
+}
+
+long primitiveSemantics_return_imm_imm_01(long a, long b) {
+ return a != 0 ? 4 : 6;
+}
+
+long primitiveSemantics_return_imm_imm_02(long a, long b) {
+ return a == 0 ? 6 : 4;
+}
+
+long primitiveSemantics_return_imm_imm_03(long a, long b) {
+ return a != 0 ? 6 : 4;
+}
+
+long primitiveSemantics_return_imm_imm_04(long a, long b) {
+ if (a)
+ b = 4;
+ else
+ b = 6;
+ return b;
+}
+
+long primitiveSemantics_return_imm_imm_05(long a, long b) {
+ if (!a)
+ b = 4;
+ else
+ b = 6;
+ return b;
+}
+
+int primitiveSemantics_return_imm_imm_06(int a, int b) {
+ return a == 0 ? 4 : 6;
+}
+
+int primitiveSemantics_return_imm_imm_07(int a, int b) {
+ return a != 0 ? 4 : 6;
+}
+
+int primitiveSemantics_return_imm_imm_08(int a, int b) {
+ return a == 0 ? 6 : 4;
+}
+
+int primitiveSemantics_return_imm_imm_09(int a, int b) {
+ return a != 0 ? 6 : 4;
+}
+
+int primitiveSemantics_return_imm_imm_10(int a, int b) {
+ if (a)
+ b = 4;
+ else
+ b = 6;
+ return b;
+}
+
+int primitiveSemantics_return_imm_imm_11(int a, int b) {
+ if (!a)
+ b = 4;
+ else
+ b = 6;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */
+/* { dg-final { scan-assembler-times "czero.nez" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
new file mode 100644
index 00000000000..12c351dbc16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
@@ -0,0 +1,65 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */
+
+long primitiveSemantics_return_imm_reg_00(long a, long b) {
+ return a == 0 ? 1 : b;
+}
+
+long primitiveSemantics_return_imm_reg_01(long a, long b) {
+ return a != 0 ? 1 : b;
+}
+
+long primitiveSemantics_return_imm_reg_02(long a, long b) {
+ return a == 0 ? b : 1;
+}
+
+long primitiveSemantics_return_imm_reg_03(long a, long b) {
+ return a != 0 ? b : 1;
+}
+
+long primitiveSemantics_return_imm_reg_04(long a, long b) {
+ if (a)
+ b = 1;
+ return b;
+}
+
+long primitiveSemantics_return_imm_reg_05(long a, long b) {
+ if (!a)
+ b = 1;
+ return b;
+}
+
+int primitiveSemantics_return_imm_reg_06(int a, int b) {
+ return a == 0 ? 1 : b;
+}
+
+int primitiveSemantics_return_imm_reg_07(int a, int b) {
+ return a != 0 ? 1 : b;
+}
+
+int primitiveSemantics_return_imm_reg_08(int a, int b) {
+ return a == 0 ? b : 1;
+}
+
+int primitiveSemantics_return_imm_reg_09(int a, int b) {
+ return a != 0 ? b : 1;
+}
+
+int primitiveSemantics_return_imm_reg_10(int a, int b) {
+ if (a)
+ b = 1;
+ return b;
+}
+
+int primitiveSemantics_return_imm_reg_11(int a, int b) {
+ if (!a)
+ b = 1;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */
+/* { dg-final { scan-assembler-times "czero.nez" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c
new file mode 100644
index 00000000000..4708afa645b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c
@@ -0,0 +1,65 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os"} } */
+
+long primitiveSemantics_return_reg_reg_00(long a, long b, long c) {
+ return a == 0 ? c : b;
+}
+
+long primitiveSemantics_return_reg_reg_01(long a, long b, long c) {
+ return a != 0 ? c : b;
+}
+
+long primitiveSemantics_return_reg_reg_02(long a, long b, long c) {
+ return a == 0 ? b : c;
+}
+
+long primitiveSemantics_return_reg_reg_03(long a, long b, long c) {
+ return a != 0 ? b : c;
+}
+
+long primitiveSemantics_return_reg_reg_04(long a, long b, long c) {
+ if (a)
+ b = c;
+ return b;
+}
+
+long primitiveSemantics_return_reg_reg_05(long a, long b, long c) {
+ if (!a)
+ b = c;
+ return b;
+}
+
+int primitiveSemantics_return_reg_reg_06(int a, int b, int c) {
+ return a == 0 ? c : b;
+}
+
+int primitiveSemantics_return_reg_reg_07(int a, int b, int c) {
+ return a != 0 ? c : b;
+}
+
+int primitiveSemantics_return_reg_reg_08(int a, int b, int c) {
+ return a == 0 ? b : c;
+}
+
+int primitiveSemantics_return_reg_reg_09(int a, int b, int c) {
+ return a != 0 ? b : c;
+}
+
+int primitiveSemantics_return_reg_reg_10(int a, int b, int c) {
+ if (a)
+ b = c;
+ return b;
+}
+
+int primitiveSemantics_return_reg_reg_11(int a, int b, int c) {
+ if (!a)
+ b = c;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "czero.eqz" 12 } } */
+/* { dg-final { scan-assembler-times "czero.nez" 12 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
--
2.17.1
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-08-03 15:09 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-03 9:27 [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 juzhe.zhong
2023-08-03 13:49 ` Jeff Law
2023-08-03 13:56 ` Kito Cheng
2023-08-03 14:08 ` Jeff Law
2023-08-03 14:31 ` Kito Cheng
2023-08-03 14:41 ` Jeff Law
2023-08-03 14:56 ` Kito Cheng
2023-08-03 15:09 ` Jeff Law
-- strict thread matches above, loose matches on Subject: below --
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32 ` Jeff Law
2023-07-25 17:55 ` Andreas Schwab
2023-07-28 15:09 ` Jeff Law
2023-07-28 20:59 ` Jeff Law
2023-07-29 9:14 ` Xiao Zeng
2023-08-03 4:59 ` Jeff Law
2023-08-02 6:34 ` Jeff Law
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