* [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. @ 2023-07-14 2:02 Die Li 2023-07-14 2:34 ` Palmer Dabbelt 0 siblings, 1 reply; 7+ messages in thread From: Die Li @ 2023-07-14 2:02 UTC (permalink / raw) To: gcc-patches; +Cc: kito.cheng, palmer, jeffeyalaw, lidie When generating the gen_and<mode>3 function based on the and<mode>3 template, it produces the expression emit_insn (gen_rtx_SET (operand0, gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the portion I removed in this patch. Therefore, the redundant portion can be deleted. Signed-off-by: Die Li <lidie@eswincomputing.com> gcc/ChangeLog: * config/riscv/riscv.md: Remove redundant portion in and<mode>3. --- gcc/config/riscv/riscv.md | 5 ----- 1 file changed, 5 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7988026d129..c4f8eb9488e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1491,11 +1491,6 @@ DONE; } } - else - { - emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2])); - DONE; - } }) (define_insn "*and<mode>3" -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:02 [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3 Die Li @ 2023-07-14 2:34 ` Palmer Dabbelt 2023-07-14 2:41 ` Kito Cheng 0 siblings, 1 reply; 7+ messages in thread From: Palmer Dabbelt @ 2023-07-14 2:34 UTC (permalink / raw) To: lidie; +Cc: gcc-patches, Kito Cheng, jeffeyalaw, lidie On Thu, 13 Jul 2023 19:02:05 PDT (-0700), lidie@eswincomputing.com wrote: > When generating the gen_and<mode>3 function based on the and<mode>3 > template, it produces the expression emit_insn (gen_rtx_SET (operand0, > gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the > portion I removed in this patch. Therefore, the redundant portion can be > deleted. > > Signed-off-by: Die Li <lidie@eswincomputing.com> > > gcc/ChangeLog: > > * config/riscv/riscv.md: Remove redundant portion in and<mode>3. > --- > gcc/config/riscv/riscv.md | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 7988026d129..c4f8eb9488e 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1491,11 +1491,6 @@ > DONE; > } > } > - else > - { > - emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2])); > - DONE; > - } > }) > > (define_insn "*and<mode>3" Unless I'm missing something, this will just result in no emitted instructions for this "and" pattern? That seems wrong, it would at least have to put the source into the dest -- but "arith_operand_or_mode_mask" can contain values that don't just result in an extension (like arbitrary register values, for example), so I think we need the "and" operation. Does this pass the regression suite? Either way, if this branch of the conditional can't trigger we should tighten the constraint (or at a bare minimum add a comment as to why). ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:34 ` Palmer Dabbelt @ 2023-07-14 2:41 ` Kito Cheng 2023-07-14 2:44 ` Palmer Dabbelt 2023-07-14 2:52 ` Jeff Law 0 siblings, 2 replies; 7+ messages in thread From: Kito Cheng @ 2023-07-14 2:41 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: lidie, gcc-patches, jeffeyalaw Expanding without DONE or FAIL will leave the pattern as well, so this patch is fine IMO, so this patch LGTM, but anyway I will test this and commit if passed :) On Fri, Jul 14, 2023 at 10:34 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Thu, 13 Jul 2023 19:02:05 PDT (-0700), lidie@eswincomputing.com wrote: > > When generating the gen_and<mode>3 function based on the and<mode>3 > > template, it produces the expression emit_insn (gen_rtx_SET (operand0, > > gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the > > portion I removed in this patch. Therefore, the redundant portion can be > > deleted. > > > > Signed-off-by: Die Li <lidie@eswincomputing.com> > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.md: Remove redundant portion in and<mode>3. > > --- > > gcc/config/riscv/riscv.md | 5 ----- > > 1 file changed, 5 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index 7988026d129..c4f8eb9488e 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -1491,11 +1491,6 @@ > > DONE; > > } > > } > > - else > > - { > > - emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2])); > > - DONE; > > - } > > }) > > > > (define_insn "*and<mode>3" > > Unless I'm missing something, this will just result in no emitted > instructions for this "and" pattern? That seems wrong, it would at > least have to put the source into the dest -- but > "arith_operand_or_mode_mask" can contain values that don't just result > in an extension (like arbitrary register values, for example), so I > think we need the "and" operation. > > Does this pass the regression suite? > > Either way, if this branch of the conditional can't trigger we should > tighten the constraint (or at a bare minimum add a comment as to why). ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:41 ` Kito Cheng @ 2023-07-14 2:44 ` Palmer Dabbelt 2023-07-14 2:50 ` Jeff Law 2023-07-14 2:52 ` Jeff Law 1 sibling, 1 reply; 7+ messages in thread From: Palmer Dabbelt @ 2023-07-14 2:44 UTC (permalink / raw) To: gcc-patches; +Cc: lidie, gcc-patches, jeffeyalaw On Thu, 13 Jul 2023 19:41:08 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > Expanding without DONE or FAIL will leave the pattern as well, so this > patch is fine IMO, so this patch LGTM, but anyway I will test this and > commit if passed :) Ah, thanks, I guess I didn't know that. This is probably fine then, but we might have some code floating around we could toss... > On Fri, Jul 14, 2023 at 10:34 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: >> >> On Thu, 13 Jul 2023 19:02:05 PDT (-0700), lidie@eswincomputing.com wrote: >> > When generating the gen_and<mode>3 function based on the and<mode>3 >> > template, it produces the expression emit_insn (gen_rtx_SET (operand0, >> > gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the >> > portion I removed in this patch. Therefore, the redundant portion can be >> > deleted. >> > >> > Signed-off-by: Die Li <lidie@eswincomputing.com> >> > >> > gcc/ChangeLog: >> > >> > * config/riscv/riscv.md: Remove redundant portion in and<mode>3. >> > --- >> > gcc/config/riscv/riscv.md | 5 ----- >> > 1 file changed, 5 deletions(-) >> > >> > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >> > index 7988026d129..c4f8eb9488e 100644 >> > --- a/gcc/config/riscv/riscv.md >> > +++ b/gcc/config/riscv/riscv.md >> > @@ -1491,11 +1491,6 @@ >> > DONE; >> > } >> > } >> > - else >> > - { >> > - emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2])); >> > - DONE; >> > - } >> > }) >> > >> > (define_insn "*and<mode>3" >> >> Unless I'm missing something, this will just result in no emitted >> instructions for this "and" pattern? That seems wrong, it would at >> least have to put the source into the dest -- but >> "arith_operand_or_mode_mask" can contain values that don't just result >> in an extension (like arbitrary register values, for example), so I >> think we need the "and" operation. >> >> Does this pass the regression suite? >> >> Either way, if this branch of the conditional can't trigger we should >> tighten the constraint (or at a bare minimum add a comment as to why). ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:44 ` Palmer Dabbelt @ 2023-07-14 2:50 ` Jeff Law 0 siblings, 0 replies; 7+ messages in thread From: Jeff Law @ 2023-07-14 2:50 UTC (permalink / raw) To: Palmer Dabbelt, gcc-patches; +Cc: lidie, jeffeyalaw On 7/13/23 20:44, Palmer Dabbelt wrote: > On Thu, 13 Jul 2023 19:41:08 PDT (-0700), gcc-patches@gcc.gnu.org wrote: >> Expanding without DONE or FAIL will leave the pattern as well, so this >> patch is fine IMO, so this patch LGTM, but anyway I will test this and >> commit if passed :) > > Ah, thanks, I guess I didn't know that. This is probably fine then, but > we might have some code floating around we could toss... Yea, if you fall off the end the original pattern stays in place. It's always been that way. And yes, we may have a bit of redundant code and more importantly useless RTL generation. jeff ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:41 ` Kito Cheng 2023-07-14 2:44 ` Palmer Dabbelt @ 2023-07-14 2:52 ` Jeff Law 2023-07-14 12:32 ` Kito Cheng 1 sibling, 1 reply; 7+ messages in thread From: Jeff Law @ 2023-07-14 2:52 UTC (permalink / raw) To: Kito Cheng, Palmer Dabbelt; +Cc: lidie, gcc-patches, jeffeyalaw On 7/13/23 20:41, Kito Cheng via Gcc-patches wrote: > Expanding without DONE or FAIL will leave the pattern as well, so this > patch is fine IMO, so this patch LGTM, but anyway I will test this and > commit if passed :) THanks. I looked fine to me, but I wasn't going to have the time to commit/push it tonight. jeff ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3. 2023-07-14 2:52 ` Jeff Law @ 2023-07-14 12:32 ` Kito Cheng 0 siblings, 0 replies; 7+ messages in thread From: Kito Cheng @ 2023-07-14 12:32 UTC (permalink / raw) To: Jeff Law; +Cc: Palmer Dabbelt, Die Li, GCC Patches, jeffeyalaw [-- Attachment #1: Type: text/plain, Size: 465 bytes --] Committed :) Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2023年7月14日 週五 10:52 寫道: > > > On 7/13/23 20:41, Kito Cheng via Gcc-patches wrote: > > Expanding without DONE or FAIL will leave the pattern as well, so this > > patch is fine IMO, so this patch LGTM, but anyway I will test this and > > commit if passed :) > THanks. I looked fine to me, but I wasn't going to have the time to > commit/push it tonight. > > jeff > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-07-14 12:32 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-07-14 2:02 [PATCH] RISC-V: Remove the redundant expressions in the and<mode>3 Die Li 2023-07-14 2:34 ` Palmer Dabbelt 2023-07-14 2:41 ` Kito Cheng 2023-07-14 2:44 ` Palmer Dabbelt 2023-07-14 2:50 ` Jeff Law 2023-07-14 2:52 ` Jeff Law 2023-07-14 12:32 ` Kito Cheng
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