* [PATCH] RISC-V: Fix typo.
@ 2022-10-24 14:24 juzhe.zhong
2022-10-26 8:34 ` Kito Cheng
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2022-10-24 14:24 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo.
---
gcc/config/riscv/riscv-modes.def | 46 ++++++++++++++++----------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 95f69e87e23..ea88442e117 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -71,29 +71,29 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
/*
| Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 |
- | | LMUL | SEW/LMUL | LMUL | SEW/LMUL |
- | VNx1QI | MF4 | 32 | MF8 | 64 |
- | VNx2QI | MF2 | 16 | MF4 | 32 |
- | VNx4QI | M1 | 8 | MF2 | 16 |
- | VNx8QI | M2 | 4 | M1 | 8 |
- | VNx16QI | M4 | 2 | M2 | 4 |
- | VNx32QI | M8 | 1 | M4 | 2 |
- | VNx64QI | N/A | N/A | M8 | 1 |
- | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 |
- | VNx2(HI|HF) | M1 | 16 | MF2 | 32 |
- | VNx4(HI|HF) | M2 | 8 | M1 | 16 |
- | VNx8(HI|HF) | M4 | 4 | M2 | 8 |
- | VNx16(HI|HF)| M8 | 2 | M4 | 4 |
- | VNx32(HI|HF)| N/A | N/A | M8 | 2 |
- | VNx1(SI|SF) | M1 | 32 | MF2 | 64 |
- | VNx2(SI|SF) | M2 | 16 | M1 | 32 |
- | VNx4(SI|SF) | M4 | 8 | M2 | 16 |
- | VNx8(SI|SF) | M8 | 4 | M4 | 8 |
- | VNx16(SI|SF)| N/A | N/A | M8 | 4 |
- | VNx1(DI|DF) | N/A | N/A | M1 | 64 |
- | VNx2(DI|DF) | N/A | N/A | M2 | 32 |
- | VNx4(DI|DF) | N/A | N/A | M4 | 16 |
- | VNx8(DI|DF) | N/A | N/A | M8 | 8 |
+ | | LMUL | SEW/LMUL | LMUL | SEW/LMUL |
+ | VNx1QI | MF4 | 32 | MF8 | 64 |
+ | VNx2QI | MF2 | 16 | MF4 | 32 |
+ | VNx4QI | M1 | 8 | MF2 | 16 |
+ | VNx8QI | M2 | 4 | M1 | 8 |
+ | VNx16QI | M4 | 2 | M2 | 4 |
+ | VNx32QI | M8 | 1 | M4 | 2 |
+ | VNx64QI | N/A | N/A | M8 | 1 |
+ | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 |
+ | VNx2(HI|HF) | M1 | 16 | MF2 | 32 |
+ | VNx4(HI|HF) | M2 | 8 | M1 | 16 |
+ | VNx8(HI|HF) | M4 | 4 | M2 | 8 |
+ | VNx16(HI|HF)| M8 | 2 | M4 | 4 |
+ | VNx32(HI|HF)| N/A | N/A | M8 | 2 |
+ | VNx1(SI|SF) | M1 | 32 | MF2 | 64 |
+ | VNx2(SI|SF) | M2 | 16 | M1 | 32 |
+ | VNx4(SI|SF) | M4 | 8 | M2 | 16 |
+ | VNx8(SI|SF) | M8 | 4 | M4 | 8 |
+ | VNx16(SI|SF)| N/A | N/A | M8 | 4 |
+ | VNx1(DI|DF) | N/A | N/A | M1 | 64 |
+ | VNx2(DI|DF) | N/A | N/A | M2 | 32 |
+ | VNx4(DI|DF) | N/A | N/A | M4 | 16 |
+ | VNx8(DI|DF) | N/A | N/A | M8 | 8 |
*/
/* Define RVV modes whose sizes are multiples of 64-bit chunks. */
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Fix typo.
2022-10-24 14:24 [PATCH] RISC-V: Fix typo juzhe.zhong
@ 2022-10-26 8:34 ` Kito Cheng
0 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2022-10-26 8:34 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches
Committed with title tweak , thanks
On Mon, Oct 24, 2022 at 10:24 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo.
>
> ---
> gcc/config/riscv/riscv-modes.def | 46 ++++++++++++++++----------------
> 1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
> index 95f69e87e23..ea88442e117 100644
> --- a/gcc/config/riscv/riscv-modes.def
> +++ b/gcc/config/riscv/riscv-modes.def
> @@ -71,29 +71,29 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
>
> /*
> | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 |
> - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL |
> - | VNx1QI | MF4 | 32 | MF8 | 64 |
> - | VNx2QI | MF2 | 16 | MF4 | 32 |
> - | VNx4QI | M1 | 8 | MF2 | 16 |
> - | VNx8QI | M2 | 4 | M1 | 8 |
> - | VNx16QI | M4 | 2 | M2 | 4 |
> - | VNx32QI | M8 | 1 | M4 | 2 |
> - | VNx64QI | N/A | N/A | M8 | 1 |
> - | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 |
> - | VNx2(HI|HF) | M1 | 16 | MF2 | 32 |
> - | VNx4(HI|HF) | M2 | 8 | M1 | 16 |
> - | VNx8(HI|HF) | M4 | 4 | M2 | 8 |
> - | VNx16(HI|HF)| M8 | 2 | M4 | 4 |
> - | VNx32(HI|HF)| N/A | N/A | M8 | 2 |
> - | VNx1(SI|SF) | M1 | 32 | MF2 | 64 |
> - | VNx2(SI|SF) | M2 | 16 | M1 | 32 |
> - | VNx4(SI|SF) | M4 | 8 | M2 | 16 |
> - | VNx8(SI|SF) | M8 | 4 | M4 | 8 |
> - | VNx16(SI|SF)| N/A | N/A | M8 | 4 |
> - | VNx1(DI|DF) | N/A | N/A | M1 | 64 |
> - | VNx2(DI|DF) | N/A | N/A | M2 | 32 |
> - | VNx4(DI|DF) | N/A | N/A | M4 | 16 |
> - | VNx8(DI|DF) | N/A | N/A | M8 | 8 |
> + | | LMUL | SEW/LMUL | LMUL | SEW/LMUL |
> + | VNx1QI | MF4 | 32 | MF8 | 64 |
> + | VNx2QI | MF2 | 16 | MF4 | 32 |
> + | VNx4QI | M1 | 8 | MF2 | 16 |
> + | VNx8QI | M2 | 4 | M1 | 8 |
> + | VNx16QI | M4 | 2 | M2 | 4 |
> + | VNx32QI | M8 | 1 | M4 | 2 |
> + | VNx64QI | N/A | N/A | M8 | 1 |
> + | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 |
> + | VNx2(HI|HF) | M1 | 16 | MF2 | 32 |
> + | VNx4(HI|HF) | M2 | 8 | M1 | 16 |
> + | VNx8(HI|HF) | M4 | 4 | M2 | 8 |
> + | VNx16(HI|HF)| M8 | 2 | M4 | 4 |
> + | VNx32(HI|HF)| N/A | N/A | M8 | 2 |
> + | VNx1(SI|SF) | M1 | 32 | MF2 | 64 |
> + | VNx2(SI|SF) | M2 | 16 | M1 | 32 |
> + | VNx4(SI|SF) | M4 | 8 | M2 | 16 |
> + | VNx8(SI|SF) | M8 | 4 | M4 | 8 |
> + | VNx16(SI|SF)| N/A | N/A | M8 | 4 |
> + | VNx1(DI|DF) | N/A | N/A | M1 | 64 |
> + | VNx2(DI|DF) | N/A | N/A | M2 | 32 |
> + | VNx4(DI|DF) | N/A | N/A | M4 | 16 |
> + | VNx8(DI|DF) | N/A | N/A | M8 | 8 |
> */
>
> /* Define RVV modes whose sizes are multiples of 64-bit chunks. */
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Fix typo
2023-04-04 7:49 Li Xu
@ 2023-04-05 1:14 ` Jeff Law
0 siblings, 0 replies; 6+ messages in thread
From: Jeff Law @ 2023-04-05 1:14 UTC (permalink / raw)
To: Li Xu, gcc-patches; +Cc: kito.cheng, palmer
On 4/4/23 01:49, Li Xu wrote:
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.def: Fix typo.
> * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
> * config/riscv/vector-iterators.md: Ditto.
Thanks. Installed on the trunk.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] RISC-V: Fix typo
@ 2023-04-04 7:49 Li Xu
2023-04-05 1:14 ` Jeff Law
0 siblings, 1 reply; 6+ messages in thread
From: Li Xu @ 2023-04-04 7:49 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Li Xu
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def: Fix typo.
* config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
* config/riscv/vector-iterators.md: Ditto.
---
gcc/config/riscv/riscv-vector-builtins.def | 3 +--
gcc/config/riscv/riscv.cc | 4 ++--
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 2d527f76f0a..563ad355342 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -65,8 +65,7 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_BASE_TYPE(NAME, TYPE)
#endif
-/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types.
- The 'NAME' will be concatenated into intrinsic function name. */
+/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */
#ifndef DEF_RVV_TYPE_INDEX
#define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, \
EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..5f542932d13 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7048,8 +7048,8 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
int *offset)
{
/* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
- 1. TARGET_MIN_VLEN == 32, olynomial invariant 1 == (VLENB / 4) - 1.
- 2. TARGET_MIN_VLEN > 32, olynomial invariant 1 == (VLENB / 8) - 1.
+ 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
+ 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
*/
gcc_assert (i == 1);
*factor = riscv_bytes_per_vector_chunk;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 34e486e48ca..194e9b8f57f 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -727,7 +727,7 @@
(VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi")
(VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi")
(VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si")
- (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2SI")
+ (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si")
(VNx1SI "vnx2di") (VNx2SI "vnx2di") (VNx4SI "vnx2di")
(VNx8SI "vnx2di") (VNx16SI "vnx2di")
(VNx1SF "vnx1df") (VNx2SF "vnx1df")
@@ -738,7 +738,7 @@
(VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi")
(VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi")
(VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si")
- (VNx8HI "vnx1si") (VNx16HI "vnx1SI")
+ (VNx8HI "vnx1si") (VNx16HI "vnx1si")
])
(define_mode_attr VDEMOTE [
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Fix typo
2023-04-03 1:19 Li Xu
@ 2023-04-03 4:00 ` Jeff Law
0 siblings, 0 replies; 6+ messages in thread
From: Jeff Law @ 2023-04-03 4:00 UTC (permalink / raw)
To: Li Xu, gcc-patches; +Cc: kito.cheng, palmer
On 4/2/23 19:19, Li Xu wrote:
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
> (vfloat32m8_t): Likewise
THanks. Pushed to the trunk.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] RISC-V: Fix typo
@ 2023-04-03 1:19 Li Xu
2023-04-03 4:00 ` Jeff Law
0 siblings, 1 reply; 6+ messages in thread
From: Li Xu @ 2023-04-03 1:19 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Li Xu
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
(vfloat32m8_t): Likewise
---
gcc/config/riscv/riscv-vector-builtins.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index d4a74befd8a..2d527f76f0a 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -234,7 +234,7 @@ DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI,
_u32m8, _u32, _e32m8)
/* SEW = 64:
- Disable when TARGET_MIN_VLEN > 32. */
+ Enable when TARGET_MIN_VLEN > 32. */
DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
_i64, _e64m1)
DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1,
@@ -278,7 +278,7 @@ DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
_f32m8, _f32, _e32m8)
/* SEW = 64:
- Disable when TARGET_VECTOR_FP64. */
+ Enable when TARGET_VECTOR_FP64. */
DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
_f64, _e64m1)
DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-10-24 14:24 [PATCH] RISC-V: Fix typo juzhe.zhong
2022-10-26 8:34 ` Kito Cheng
2023-04-03 1:19 Li Xu
2023-04-03 4:00 ` Jeff Law
2023-04-04 7:49 Li Xu
2023-04-05 1:14 ` Jeff Law
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