* [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
@ 2023-04-19 3:21 pan2.li
2023-04-19 8:49 ` Li, Pan2
2023-04-19 11:23 ` [PATCH v2] " pan2.li
0 siblings, 2 replies; 18+ messages in thread
From: pan2.li @ 2023-04-19 3:21 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, yanzhang.wang, pan2.li
From: Pan Li <pan2.li@intel.com>
This patch try to adjust the RISC-V Vector RTL for the
generic shortcut optimization for RVV integer compare.
It includes compare operator eq, ne, ltu, lt, leu, le,
gtu, gt, geu and ge.
Assume we have below test code.
vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) {
return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl);
}
Before this patch:
vsetvli zero,a2,e8,m8,ta,ma
vl8re8.v v24,0(a1)
vmslt.vv v8,v24,v24
vsetvli a5,zero,e8,m8,ta,ma
vsm.v v8,0(a0)
ret
After this patch:
vsetvli zero,a2,e8,mf8,ta,ma
vmclr.m v24
vsetvli zero,a5,e8,mf8,ta,ma
vsm.v v24,0(a0)
ret
However, there some cases in the test files cannot be optimized right
now. We will file separated patches to try to make it happen.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_pred_op):
* config/riscv/riscv-vector-builtins-bases.cc:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-v.cc | 15 +-
.../riscv/riscv-vector-builtins-bases.cc | 6 +-
gcc/config/riscv/vector.md | 14 +-
.../rvv/base/integer_compare_insn_shortcut.c | 291 ++++++++++++++++++
4 files changed, 319 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 392f5d02e17..c3881920812 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -71,12 +71,23 @@ public:
add_input_operand (RVV_VUNDEF (mode), mode);
}
void add_policy_operand (enum tail_policy vta, enum mask_policy vma)
+ {
+ add_tail_policy_operand (vta);
+ add_mask_policy_operand (vma);
+ }
+
+ void add_tail_policy_operand (enum tail_policy vta)
{
rtx tail_policy_rtx = gen_int_mode (vta, Pmode);
- rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (tail_policy_rtx, Pmode);
+ }
+
+ void add_mask_policy_operand (enum mask_policy vma)
+ {
+ rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (mask_policy_rtx, Pmode);
}
+
void add_avl_type_operand (avl_type type)
{
add_input_operand (gen_int_mode (type, Pmode), Pmode);
@@ -206,6 +217,8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
+ else
+ e.add_tail_policy_operand (get_prefer_tail_policy ());
if (vlmax_p)
e.add_avl_type_operand (avl_type::VLMAX);
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 52467bbc961..7c6064a5a24 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -756,7 +756,7 @@ template<rtx_code CODE>
class mask_logic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
@@ -768,7 +768,7 @@ template<rtx_code CODE>
class mask_nlogic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
@@ -780,7 +780,7 @@ template<rtx_code CODE>
class mask_notlogic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0ecca98f20c..6819363b9ff 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
@@ -4113,7 +4114,8 @@ (define_expand "@pred_ge<mode>_scalar"
if (satisfies_constraint_Wc1 (operands[1]))
emit_insn (
gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
- CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
+ CONSTM1_RTX (<VM>mode), operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
else
{
/* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
@@ -4158,7 +4160,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[6], operands[7], operands[8]));
emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
undef, operands[0], operands[0],
- operands[6], operands[8]));
+ operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
}
else
{
@@ -4173,7 +4176,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[5], operands[6], operands[7], operands[8]));
emit_insn (
gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
- operands[1], reg, operands[6], operands[8]));
+ operands[1], reg, operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
}
else
{
@@ -5196,6 +5200,7 @@ (define_insn "@pred_<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_bitwise:VB
@@ -5216,6 +5221,7 @@ (define_insn "@pred_n<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
@@ -5237,6 +5243,7 @@ (define_insn "@pred_<optab>not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(and_ior:VB
@@ -5258,6 +5265,7 @@ (define_insn "@pred_not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
+ (match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
new file mode 100644
index 00000000000..495a0f11440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -0,0 +1,291 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmseq_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmseq_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmseq_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmseq_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmseq_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmseq_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsne_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsne_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsne_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsne_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsne_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsne_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsne_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmslt_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmslt_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmslt_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmslt_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmslt_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmslt_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsltu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsltu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsltu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsltu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsltu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsltu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsltu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsle_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsle_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsle_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsle_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsle_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsle_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsle_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsleu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsleu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsleu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsleu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsleu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsleu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsleu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgt_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgt_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgt_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgt_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgt_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgt_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgt_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgtu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgtu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgtu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgtu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgtu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgtu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgtu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsge_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsge_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsge_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsge_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsge_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsge_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsge_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgeu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgeu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgeu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgeu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgeu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgeu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 35 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 3:21 [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization pan2.li
@ 2023-04-19 8:49 ` Li, Pan2
2023-04-19 9:34 ` Kito Cheng
2023-04-19 11:23 ` [PATCH v2] " pan2.li
1 sibling, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-19 8:49 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, Wang, Yanzhang
Passed the X86 bootstrap and regression tests.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Wednesday, April 19, 2023 11:21 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>; Li, Pan2 <pan2.li@intel.com>
Subject: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
From: Pan Li <pan2.li@intel.com>
This patch try to adjust the RISC-V Vector RTL for the generic shortcut optimization for RVV integer compare.
It includes compare operator eq, ne, ltu, lt, leu, le, gtu, gt, geu and ge.
Assume we have below test code.
vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) {
return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); }
Before this patch:
vsetvli zero,a2,e8,m8,ta,ma
vl8re8.v v24,0(a1)
vmslt.vv v8,v24,v24
vsetvli a5,zero,e8,m8,ta,ma
vsm.v v8,0(a0)
ret
After this patch:
vsetvli zero,a2,e8,mf8,ta,ma
vmclr.m v24
vsetvli zero,a5,e8,mf8,ta,ma
vsm.v v24,0(a0)
ret
However, there some cases in the test files cannot be optimized right now. We will file separated patches to try to make it happen.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_pred_op):
* config/riscv/riscv-vector-builtins-bases.cc:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-v.cc | 15 +-
.../riscv/riscv-vector-builtins-bases.cc | 6 +-
gcc/config/riscv/vector.md | 14 +-
.../rvv/base/integer_compare_insn_shortcut.c | 291 ++++++++++++++++++
4 files changed, 319 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 392f5d02e17..c3881920812 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -71,12 +71,23 @@ public:
add_input_operand (RVV_VUNDEF (mode), mode);
}
void add_policy_operand (enum tail_policy vta, enum mask_policy vma)
+ {
+ add_tail_policy_operand (vta);
+ add_mask_policy_operand (vma);
+ }
+
+ void add_tail_policy_operand (enum tail_policy vta)
{
rtx tail_policy_rtx = gen_int_mode (vta, Pmode);
- rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (tail_policy_rtx, Pmode);
+ }
+
+ void add_mask_policy_operand (enum mask_policy vma) {
+ rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (mask_policy_rtx, Pmode);
}
+
void add_avl_type_operand (avl_type type)
{
add_input_operand (gen_int_mode (type, Pmode), Pmode); @@ -206,6 +217,8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
+ else
+ e.add_tail_policy_operand (get_prefer_tail_policy ());
if (vlmax_p)
e.add_avl_type_operand (avl_type::VLMAX); diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 52467bbc961..7c6064a5a24 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -756,7 +756,7 @@ template<rtx_code CODE> class mask_logic : public function_base {
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override @@ -768,7 +768,7 @@ template<rtx_code CODE> class mask_nlogic : public function_base {
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override @@ -780,7 +780,7 @@ template<rtx_code CODE> class mask_notlogic : public function_base {
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0ecca98f20c..6819363b9ff 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
@@ -4113,7 +4114,8 @@ (define_expand "@pred_ge<mode>_scalar"
if (satisfies_constraint_Wc1 (operands[1]))
emit_insn (
gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
- CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
+ CONSTM1_RTX (<VM>mode), operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
else
{
/* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
@@ -4158,7 +4160,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[6], operands[7], operands[8]));
emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
undef, operands[0], operands[0],
- operands[6], operands[8]));
+ operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
}
else
{
@@ -4173,7 +4176,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[5], operands[6], operands[7], operands[8]));
emit_insn (
gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
- operands[1], reg, operands[6], operands[8]));
+ operands[1], reg, operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (),
+Pmode)));
}
else
{
@@ -5196,6 +5200,7 @@ (define_insn "@pred_<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_bitwise:VB
@@ -5216,6 +5221,7 @@ (define_insn "@pred_n<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
@@ -5237,6 +5243,7 @@ (define_insn "@pred_<optab>not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(and_ior:VB
@@ -5258,6 +5265,7 @@ (define_insn "@pred_not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
+ (match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
new file mode 100644
index 00000000000..495a0f11440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_short
+++ cut.c
@@ -0,0 +1,291 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmseq_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmseq_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmseq_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmseq_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmseq_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmseq_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmseq_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmseq_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmseq_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmseq_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmseq_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmseq_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsne_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmsne_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsne_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmsne_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsne_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmsne_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsne_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmsne_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsne_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsne_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsne_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsne_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsne_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsne_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmslt_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmslt_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmslt_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmslt_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmslt_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmslt_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmslt_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmslt_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmslt_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmslt_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmslt_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmslt_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsltu_case_0(vuint8m8_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsltu_case_1(vuint8m4_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsltu_case_2(vuint8m2_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsltu_case_3(vuint8m1_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsltu_case_4(vuint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsltu_case_5(vuint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsltu_case_6(vuint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsltu_vv_u8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsle_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmsle_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsle_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmsle_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsle_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmsle_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsle_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmsle_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsle_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsle_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsle_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsle_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsle_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsle_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsleu_case_0(vuint8m8_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsleu_case_1(vuint8m4_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsleu_case_2(vuint8m2_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsleu_case_3(vuint8m1_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsleu_case_4(vuint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsleu_case_5(vuint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsleu_case_6(vuint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsleu_vv_u8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsgt_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmsgt_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsgt_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmsgt_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsgt_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmsgt_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsgt_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmsgt_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsgt_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsgt_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsgt_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsgt_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsgt_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsgt_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsgtu_case_0(vuint8m8_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsgtu_case_1(vuint8m4_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsgtu_case_2(vuint8m2_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsgtu_case_3(vuint8m1_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsgtu_case_4(vuint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsgtu_case_5(vuint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsgtu_case_6(vuint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsgtu_vv_u8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsge_case_0(vint8m8_t v1, size_t vl)
+{
+ return __riscv_vmsge_vv_i8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsge_case_1(vint8m4_t v1, size_t vl)
+{
+ return __riscv_vmsge_vv_i8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsge_case_2(vint8m2_t v1, size_t vl)
+{
+ return __riscv_vmsge_vv_i8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsge_case_3(vint8m1_t v1, size_t vl)
+{
+ return __riscv_vmsge_vv_i8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsge_case_4(vint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsge_vv_i8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsge_case_5(vint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsge_vv_i8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsge_case_6(vint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsge_vv_i8mf8_b64(v1, v1, vl); }
+
+vbool1_t test_shortcut_for_riscv_vmsgeu_case_0(vuint8m8_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8m8_b1(v1, v1, vl); }
+
+vbool2_t test_shortcut_for_riscv_vmsgeu_case_1(vuint8m4_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8m4_b2(v1, v1, vl); }
+
+vbool4_t test_shortcut_for_riscv_vmsgeu_case_2(vuint8m2_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8m2_b4(v1, v1, vl); }
+
+vbool8_t test_shortcut_for_riscv_vmsgeu_case_3(vuint8m1_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8m1_b8(v1, v1, vl); }
+
+vbool16_t test_shortcut_for_riscv_vmsgeu_case_4(vuint8mf2_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8mf2_b16(v1, v1, vl); }
+
+vbool32_t test_shortcut_for_riscv_vmsgeu_case_5(vuint8mf4_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8mf4_b32(v1, v1, vl); }
+
+vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t
+vl) {
+ return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl); }
+
+/* { dg-final { scan-assembler-times
+{vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times
+{vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times
+{vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times
+{vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times
+{vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 35 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 8:49 ` Li, Pan2
@ 2023-04-19 9:34 ` Kito Cheng
2023-04-19 9:41 ` juzhe.zhong
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-19 9:34 UTC (permalink / raw)
To: Li, Pan2; +Cc: gcc-patches, juzhe.zhong, kito.cheng, Wang, Yanzhang
Hi Pan:
> rtx expand (function_expander &e) const override diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
> [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
> (match_operand 5 "const_int_operand" " i, i, i, i, i")
> + (match_operand 6 "const_int_operand" " i, i, i, i, i")
I didn't get why having one more tail policy operand for this pattern
could help?
Do you mind explaining more detail about this?
Thanks :)
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 9:34 ` Kito Cheng
@ 2023-04-19 9:41 ` juzhe.zhong
2023-04-19 9:45 ` Kito Cheng
0 siblings, 1 reply; 18+ messages in thread
From: juzhe.zhong @ 2023-04-19 9:41 UTC (permalink / raw)
To: kito.cheng, pan2.li; +Cc: gcc-patches, Kito.cheng, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 1420 bytes --]
Since vms<cmp> pattern has one more tail policy + avl_type operand,
wheras pred_mov<mode> (vmset.m/vmclr.m) only has avl_type operand.
GCC recognize (lt:(reg v) (reg v)) and lower it into (const_vector:0),
then map into pred_mov pattern (when both pred_mov and vms<cmp> pattern has tail policy + avl_type operand).
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-04-19 17:34
To: Li, Pan2
CC: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Hi Pan:
> rtx expand (function_expander &e) const override diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
> [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
> (match_operand 5 "const_int_operand" " i, i, i, i, i")
> + (match_operand 6 "const_int_operand" " i, i, i, i, i")
I didn't get why having one more tail policy operand for this pattern
could help?
Do you mind explaining more detail about this?
Thanks :)
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 9:41 ` juzhe.zhong
@ 2023-04-19 9:45 ` Kito Cheng
2023-04-19 10:33 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-19 9:45 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Kito.cheng, yanzhang.wang
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_pred_op):
> * config/riscv/riscv-vector-builtins-bases.cc:
> * config/riscv/vector.md:
And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 9:45 ` Kito Cheng
@ 2023-04-19 10:33 ` Li, Pan2
2023-04-19 11:26 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-19 10:33 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang
Sure thing.
For Changlog, I consider it was generated automatically in previous. LOL.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, April 19, 2023 5:46 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_pred_op):
> * config/riscv/riscv-vector-builtins-bases.cc:
> * config/riscv/vector.md:
And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 10:33 ` Li, Pan2
@ 2023-04-19 11:26 ` Li, Pan2
2023-04-21 9:46 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-19 11:26 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang
Update the Patch v2 for more detail information for clarification. Please help to review continuously.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
Pan
-----Original Message-----
From: Li, Pan2
Sent: Wednesday, April 19, 2023 6:33 PM
To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Sure thing.
For Changlog, I consider it was generated automatically in previous. LOL.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, April 19, 2023 5:46 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_pred_op):
> * config/riscv/riscv-vector-builtins-bases.cc:
> * config/riscv/vector.md:
And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 11:26 ` Li, Pan2
@ 2023-04-21 9:46 ` Li, Pan2
2023-04-21 10:16 ` Kito Cheng
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-21 9:46 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang
Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
Pan
-----Original Message-----
From: Li, Pan2
Sent: Wednesday, April 19, 2023 7:27 PM
To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai' <juzhe.zhong@rivai.ai>
Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng' <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Update the Patch v2 for more detail information for clarification. Please help to review continuously.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
Pan
-----Original Message-----
From: Li, Pan2
Sent: Wednesday, April 19, 2023 6:33 PM
To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Sure thing.
For Changlog, I consider it was generated automatically in previous. LOL.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, April 19, 2023 5:46 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_pred_op):
> * config/riscv/riscv-vector-builtins-bases.cc:
> * config/riscv/vector.md:
And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-21 9:46 ` Li, Pan2
@ 2023-04-21 10:16 ` Kito Cheng
2023-04-21 11:16 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-21 10:16 UTC (permalink / raw)
To: Li, Pan2; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
I got a bunch of new fails including ICE for gcc testsuite, and some
cases are hanging there, could you take a look?
$ riscv64-unknown-linux-gnu-gcc
gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
-mabi=ilp32
during RTL pass: expand
/scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
In function 'f':
/scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
internal compiler error: in maybe_gen_insn, at optabs.cc:8102
8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
| ^~~~
0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 7:27 PM
> To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai' <juzhe.zhong@rivai.ai>
> Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng' <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
>
> Update the Patch v2 for more detail information for clarification. Please help to review continuously.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 6:33 PM
> To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
>
> Sure thing.
>
> For Changlog, I consider it was generated automatically in previous. LOL.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Wednesday, April 19, 2023 5:46 PM
> To: juzhe.zhong@rivai.ai
> Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
>
> HI JuZhe:
>
> Thanks for explaining!
>
>
> Hi Pan:
>
> I think that would be helpful if JuZhe's explaining that could be written into the commit log.
>
>
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-v.cc (emit_pred_op):
> > * config/riscv/riscv-vector-builtins-bases.cc:
> > * config/riscv/vector.md:
>
> And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-21 10:16 ` Kito Cheng
@ 2023-04-21 11:16 ` Li, Pan2
2023-04-21 13:01 ` Kito Cheng
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-21 11:16 UTC (permalink / raw)
To: Kito Cheng; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
Thanks kito, will try to reproduce this issue and keep you posted.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Friday, April 21, 2023 6:17 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
$ riscv64-unknown-linux-gnu-gcc
gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
-mabi=ilp32
during RTL pass: expand
/scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
In function 'f':
/scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
internal compiler error: in maybe_gen_insn, at optabs.cc:8102
8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
| ^~~~
0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 7:27 PM
> To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> <juzhe.zhong@rivai.ai>
> Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Update the Patch v2 for more detail information for clarification. Please help to review continuously.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 6:33 PM
> To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Sure thing.
>
> For Changlog, I consider it was generated automatically in previous. LOL.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Wednesday, April 19, 2023 5:46 PM
> To: juzhe.zhong@rivai.ai
> Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang,
> Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> HI JuZhe:
>
> Thanks for explaining!
>
>
> Hi Pan:
>
> I think that would be helpful if JuZhe's explaining that could be written into the commit log.
>
>
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-v.cc (emit_pred_op):
> > * config/riscv/riscv-vector-builtins-bases.cc:
> > * config/riscv/vector.md:
>
> And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-21 11:16 ` Li, Pan2
@ 2023-04-21 13:01 ` Kito Cheng
2023-04-22 5:33 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-21 13:01 UTC (permalink / raw)
To: Li, Pan2; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
Hi Pan:
One idea come to my mind, maybe we should add a new
define_insn_and_split pattern instead of change @pred_mov<mode>
On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Thanks kito, will try to reproduce this issue and keep you posted.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Friday, April 21, 2023 6:17 PM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
>
> I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
>
> $ riscv64-unknown-linux-gnu-gcc
> gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> -mabi=ilp32
> during RTL pass: expand
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> In function 'f':
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> | ^~~~
> 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
>
>
> On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> >
> > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Li, Pan2
> > Sent: Wednesday, April 19, 2023 7:27 PM
> > To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> > <juzhe.zhong@rivai.ai>
> > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> > optimization
> >
> > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> >
> > Pan
> >
> > -----Original Message-----
> > From: Li, Pan2
> > Sent: Wednesday, April 19, 2023 6:33 PM
> > To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> > Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> > optimization
> >
> > Sure thing.
> >
> > For Changlog, I consider it was generated automatically in previous. LOL.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com>
> > Sent: Wednesday, April 19, 2023 5:46 PM
> > To: juzhe.zhong@rivai.ai
> > Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> > <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang,
> > Yanzhang <yanzhang.wang@intel.com>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> > optimization
> >
> > HI JuZhe:
> >
> > Thanks for explaining!
> >
> >
> > Hi Pan:
> >
> > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> >
> >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > * config/riscv/vector.md:
> >
> > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-21 13:01 ` Kito Cheng
@ 2023-04-22 5:33 ` Li, Pan2
2023-04-25 13:08 ` Kito Cheng
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-22 5:33 UTC (permalink / raw)
To: Kito Cheng; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
Hi Kito
Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv test files auto generation.
I have similar discuss with juzhe for this approach, and take Patch v2's way due to the below concern.
1. The vector.md Is quite complicated already, the maintenance may be out of control if we will add many new define_insn_and_split for the shortcut.
2. The new added pattern may not friendly for the underlying auto-vectorization.
Juzhe can help to correct me if any misleading.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Friday, April 21, 2023 9:02 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Hi Pan:
One idea come to my mind, maybe we should add a new define_insn_and_split pattern instead of change @pred_mov<mode>
On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Thanks kito, will try to reproduce this issue and keep you posted.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Friday, April 21, 2023 6:17 PM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
>
> $ riscv64-unknown-linux-gnu-gcc
> gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> -mabi=ilp32
> during RTL pass: expand
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> In function 'f':
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> | ^~~~
> 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
>
>
> On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> >
> > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Li, Pan2
> > Sent: Wednesday, April 19, 2023 7:27 PM
> > To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> > <juzhe.zhong@rivai.ai>
> > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> >
> > Pan
> >
> > -----Original Message-----
> > From: Li, Pan2
> > Sent: Wednesday, April 19, 2023 6:33 PM
> > To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> > Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > Sure thing.
> >
> > For Changlog, I consider it was generated automatically in previous. LOL.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com>
> > Sent: Wednesday, April 19, 2023 5:46 PM
> > To: juzhe.zhong@rivai.ai
> > Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> > <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang,
> > Yanzhang <yanzhang.wang@intel.com>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > HI JuZhe:
> >
> > Thanks for explaining!
> >
> >
> > Hi Pan:
> >
> > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> >
> >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > * config/riscv/vector.md:
> >
> > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-22 5:33 ` Li, Pan2
@ 2023-04-25 13:08 ` Kito Cheng
2023-04-25 13:51 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-25 13:08 UTC (permalink / raw)
To: Li, Pan2, Jeff Law; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
Second thought on this, we should just add define_split rather than
define_insn_and_split, otherwise we might hit the same issue again,
and I expect the split pattern will only used in combine pass.
On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi Kito
>
> Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv test files auto generation.
>
> I have similar discuss with juzhe for this approach, and take Patch v2's way due to the below concern.
>
> 1. The vector.md Is quite complicated already, the maintenance may be out of control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Friday, April 21, 2023 9:02 PM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
>
> Hi Pan:
>
> One idea come to my mind, maybe we should add a new define_insn_and_split pattern instead of change @pred_mov<mode>
>
> On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> >
> > Thanks kito, will try to reproduce this issue and keep you posted.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com>
> > Sent: Friday, April 21, 2023 6:17 PM
> > To: Li, Pan2 <pan2.li@intel.com>
> > Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> > Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> > <yanzhang.wang@intel.com>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> > optimization
> >
> > I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
> >
> > $ riscv64-unknown-linux-gnu-gcc
> > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> > -mabi=ilp32
> > during RTL pass: expand
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> > In function 'f':
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> > internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> > 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> > | ^~~~
> > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
> >
> >
> > On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 7:27 PM
> > > To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> > > <juzhe.zhong@rivai.ai>
> > > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> > >
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 6:33 PM
> > > To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> > > Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Sure thing.
> > >
> > > For Changlog, I consider it was generated automatically in previous. LOL.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@gmail.com>
> > > Sent: Wednesday, April 19, 2023 5:46 PM
> > > To: juzhe.zhong@rivai.ai
> > > Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> > > <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang,
> > > Yanzhang <yanzhang.wang@intel.com>
> > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > HI JuZhe:
> > >
> > > Thanks for explaining!
> > >
> > >
> > > Hi Pan:
> > >
> > > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> > >
> > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > > * config/riscv/vector.md:
> > >
> > > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-25 13:08 ` Kito Cheng
@ 2023-04-25 13:51 ` Li, Pan2
2023-04-25 13:56 ` Kito Cheng
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-25 13:51 UTC (permalink / raw)
To: Kito Cheng, Jeff Law; +Cc: juzhe.zhong, gcc-patches, Kito.cheng, Wang, Yanzhang
Thanks Kito.
Actually I fixed the below ICE with all riscv tests passed, but hold the PATCH v3 as may conflict with one of Juzhe's PATCH.
Thus, there will be 2 options for the shortcut optimization.
1. Adjust existing define and let the underlying pass to perform the optimization.
2. Add new define_split(s) for each of the shortcut optimization.
Personally I may prefer the option 1. But here we would like the figure out the one and the only one right way for the implementation. Thus, it is OK if we think option 2 is a better way for this.
Kito and Juzhe, any idea for making the decision? Thanks in advance!
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Tuesday, April 25, 2023 9:08 PM
To: Li, Pan2 <pan2.li@intel.com>; Jeff Law <jeffreyalaw@gmail.com>
Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass.
On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi Kito
>
> Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv test files auto generation.
>
> I have similar discuss with juzhe for this approach, and take Patch v2's way due to the below concern.
>
> 1. The vector.md Is quite complicated already, the maintenance may be out of control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Friday, April 21, 2023 9:02 PM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Hi Pan:
>
> One idea come to my mind, maybe we should add a new
> define_insn_and_split pattern instead of change @pred_mov<mode>
>
> On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> >
> > Thanks kito, will try to reproduce this issue and keep you posted.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com>
> > Sent: Friday, April 21, 2023 6:17 PM
> > To: Li, Pan2 <pan2.li@intel.com>
> > Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> > Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> > <yanzhang.wang@intel.com>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
> >
> > $ riscv64-unknown-linux-gnu-gcc
> > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> > -mabi=ilp32
> > during RTL pass: expand
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> > In function 'f':
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> > internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> > 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> > | ^~~~
> > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
> >
> >
> > On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
> > >
> > > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 7:27 PM
> > > To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> > > <juzhe.zhong@rivai.ai>
> > > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> > >
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 6:33 PM
> > > To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> > > Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Sure thing.
> > >
> > > For Changlog, I consider it was generated automatically in previous. LOL.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@gmail.com>
> > > Sent: Wednesday, April 19, 2023 5:46 PM
> > > To: juzhe.zhong@rivai.ai
> > > Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> > > <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>;
> > > Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > HI JuZhe:
> > >
> > > Thanks for explaining!
> > >
> > >
> > > Hi Pan:
> > >
> > > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> > >
> > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > > * config/riscv/vector.md:
> > >
> > > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-25 13:51 ` Li, Pan2
@ 2023-04-25 13:56 ` Kito Cheng
2023-04-25 14:11 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Kito Cheng @ 2023-04-25 13:56 UTC (permalink / raw)
To: Li, Pan2; +Cc: Kito Cheng, Jeff Law, juzhe.zhong, gcc-patches, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 7009 bytes --]
I would strongly prefer 2 since I believe this won't be the last
optimization we did for this kind of thing, and I don't want to see we need
to fix or worry about vsetvli stuff every time if possible.
And the current pattern design is more reasonable to me - only defining
those fields is really useful.
On Tue, Apr 25, 2023 at 9:51 PM Li, Pan2 <pan2.li@intel.com> wrote:
> Thanks Kito.
>
> Actually I fixed the below ICE with all riscv tests passed, but hold the
> PATCH v3 as may conflict with one of Juzhe's PATCH.
>
> Thus, there will be 2 options for the shortcut optimization.
>
> 1. Adjust existing define and let the underlying pass to perform the
> optimization.
> 2. Add new define_split(s) for each of the shortcut optimization.
>
> Personally I may prefer the option 1. But here we would like the figure
> out the one and the only one right way for the implementation. Thus, it is
> OK if we think option 2 is a better way for this.
>
> Kito and Juzhe, any idea for making the decision? Thanks in advance!
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Tuesday, April 25, 2023 9:08 PM
> To: Li, Pan2 <pan2.li@intel.com>; Jeff Law <jeffreyalaw@gmail.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <
> yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Second thought on this, we should just add define_split rather than
> define_insn_and_split, otherwise we might hit the same issue again, and I
> expect the split pattern will only used in combine pass.
>
> On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches
>
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > Hi Kito
> >
> > Thanks for the suggestion. Sorry for late response due to stuck in the
> rest rvv test files auto generation.
> >
> > I have similar discuss with juzhe for this approach, and take Patch v2's
> way due to the below concern.
> >
> > 1. The vector.md Is quite complicated already, the maintenance may be
> out of control if we will add many new define_insn_and_split for the
> shortcut.
> > 2. The new added pattern may not friendly for the underlying
> auto-vectorization.
> >
> > Juzhe can help to correct me if any misleading.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com>
> > Sent: Friday, April 21, 2023 9:02 PM
> > To: Li, Pan2 <pan2.li@intel.com>
> > Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> > Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> > <yanzhang.wang@intel.com>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> > optimization
> >
> > Hi Pan:
> >
> > One idea come to my mind, maybe we should add a new
> > define_insn_and_split pattern instead of change @pred_mov<mode>
> >
> > On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
> > >
> > > Thanks kito, will try to reproduce this issue and keep you posted.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@gmail.com>
> > > Sent: Friday, April 21, 2023 6:17 PM
> > > To: Li, Pan2 <pan2.li@intel.com>
> > > Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>;
> > > Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang
> > > <yanzhang.wang@intel.com>
> > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > I got a bunch of new fails including ICE for gcc testsuite, and some
> cases are hanging there, could you take a look?
> > >
> > > $ riscv64-unknown-linux-gnu-gcc
> > > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> > > -mabi=ilp32
> > > during RTL pass: expand
> > >
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> > > In function 'f':
> > >
> /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> > > internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> > > 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> > > | ^~~~
> > > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> > > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
> > >
> > >
> > > On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
> > > >
> > > > Kindly ping for the PATCH v2. Just FYI there will be some underlying
> investigation based on this PATCH like VMSEQ.
> > > >
> > > > Pan
> > > >
> > > > -----Original Message-----
> > > > From: Li, Pan2
> > > > Sent: Wednesday, April 19, 2023 7:27 PM
> > > > To: 'Kito Cheng' <kito.cheng@gmail.com>; 'juzhe.zhong@rivai.ai'
> > > > <juzhe.zhong@rivai.ai>
> > > > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org>; 'Kito.cheng'
> > > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > > shortcut optimization
> > > >
> > > > Update the Patch v2 for more detail information for clarification.
> Please help to review continuously.
> > > >
> > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> > > >
> > > > Pan
> > > >
> > > > -----Original Message-----
> > > > From: Li, Pan2
> > > > Sent: Wednesday, April 19, 2023 6:33 PM
> > > > To: Kito Cheng <kito.cheng@gmail.com>; juzhe.zhong@rivai.ai
> > > > Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> > > > <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > > shortcut optimization
> > > >
> > > > Sure thing.
> > > >
> > > > For Changlog, I consider it was generated automatically in previous.
> LOL.
> > > >
> > > > Pan
> > > >
> > > > -----Original Message-----
> > > > From: Kito Cheng <kito.cheng@gmail.com>
> > > > Sent: Wednesday, April 19, 2023 5:46 PM
> > > > To: juzhe.zhong@rivai.ai
> > > > Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches
> > > > <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>;
> > > > Wang, Yanzhang <yanzhang.wang@intel.com>
> > > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > > shortcut optimization
> > > >
> > > > HI JuZhe:
> > > >
> > > > Thanks for explaining!
> > > >
> > > >
> > > > Hi Pan:
> > > >
> > > > I think that would be helpful if JuZhe's explaining that could be
> written into the commit log.
> > > >
> > > >
> > > > > gcc/ChangeLog:
> > > > >
> > > > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > > > * config/riscv/vector.md:
> > > >
> > > > And don't forgot write some thing in ChangeLog...:P
>
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-25 13:56 ` Kito Cheng
@ 2023-04-25 14:11 ` Li, Pan2
2023-04-26 2:04 ` Li, Pan2
0 siblings, 1 reply; 18+ messages in thread
From: Li, Pan2 @ 2023-04-25 14:11 UTC (permalink / raw)
To: Kito Cheng; +Cc: Kito Cheng, Jeff Law, juzhe.zhong, gcc-patches, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 8310 bytes --]
I see. If there is no question from Juzhe, I will try to implement it follow the option 2.
Pan
From: Kito Cheng <kito.cheng@sifive.com>
Sent: Tuesday, April 25, 2023 9:57 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: Kito Cheng <kito.cheng@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>; juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
I would strongly prefer 2 since I believe this won't be the last optimization we did for this kind of thing, and I don't want to see we need to fix or worry about vsetvli stuff every time if possible.
And the current pattern design is more reasonable to me - only defining those fields is really useful.
On Tue, Apr 25, 2023 at 9:51 PM Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>> wrote:
Thanks Kito.
Actually I fixed the below ICE with all riscv tests passed, but hold the PATCH v3 as may conflict with one of Juzhe's PATCH.
Thus, there will be 2 options for the shortcut optimization.
1. Adjust existing define and let the underlying pass to perform the optimization.
2. Add new define_split(s) for each of the shortcut optimization.
Personally I may prefer the option 1. But here we would like the figure out the one and the only one right way for the implementation. Thus, it is OK if we think option 2 is a better way for this.
Kito and Juzhe, any idea for making the decision? Thanks in advance!
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Sent: Tuesday, April 25, 2023 9:08 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Jeff Law <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>
Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass.
On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
>
> Hi Kito
>
> Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv test files auto generation.
>
> I have similar discuss with juzhe for this approach, and take Patch v2's way due to the below concern.
>
> 1. The vector.md Is quite complicated already, the maintenance may be out of control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> Sent: Friday, April 21, 2023 9:02 PM
> To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
> Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang
> <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Hi Pan:
>
> One idea come to my mind, maybe we should add a new
> define_insn_and_split pattern instead of change @pred_mov<mode>
>
> On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
> >
> > Thanks kito, will try to reproduce this issue and keep you posted.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> > Sent: Friday, April 21, 2023 6:17 PM
> > To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
> > Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang
> > <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
> >
> > $ riscv64-unknown-linux-gnu-gcc
> > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> > -mabi=ilp32
> > during RTL pass: expand
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> > In function 'f':
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> > internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> > 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> > | ^~~~
> > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
> >
> >
> > On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
> > >
> > > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 7:27 PM
> > > To: 'Kito Cheng' <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; 'juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>'
> > > <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
> > > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; 'Kito.cheng'
> > > <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> > >
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 6:33 PM
> > > To: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> > > Cc: gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng
> > > <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Sure thing.
> > >
> > > For Changlog, I consider it was generated automatically in previous. LOL.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> > > Sent: Wednesday, April 19, 2023 5:46 PM
> > > To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> > > Cc: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches
> > > <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>;
> > > Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > HI JuZhe:
> > >
> > > Thanks for explaining!
> > >
> > >
> > > Hi Pan:
> > >
> > > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> > >
> > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > > * config/riscv/vector.md:
> > >
> > > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-25 14:11 ` Li, Pan2
@ 2023-04-26 2:04 ` Li, Pan2
0 siblings, 0 replies; 18+ messages in thread
From: Li, Pan2 @ 2023-04-26 2:04 UTC (permalink / raw)
To: Kito Cheng; +Cc: Kito Cheng, Jeff Law, juzhe.zhong, gcc-patches, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 8965 bytes --]
Aligned with Ju-Zhe, will take the option 2 for the VMS{Compare} optimization.
Pan
From: Li, Pan2
Sent: Tuesday, April 25, 2023 10:11 PM
To: Kito Cheng <kito.cheng@sifive.com>
Cc: Kito Cheng <kito.cheng@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>; juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
I see. If there is no question from Juzhe, I will try to implement it follow the option 2.
Pan
From: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>
Sent: Tuesday, April 25, 2023 9:57 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Cc: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; Jeff Law <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>; juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
I would strongly prefer 2 since I believe this won't be the last optimization we did for this kind of thing, and I don't want to see we need to fix or worry about vsetvli stuff every time if possible.
And the current pattern design is more reasonable to me - only defining those fields is really useful.
On Tue, Apr 25, 2023 at 9:51 PM Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>> wrote:
Thanks Kito.
Actually I fixed the below ICE with all riscv tests passed, but hold the PATCH v3 as may conflict with one of Juzhe's PATCH.
Thus, there will be 2 options for the shortcut optimization.
1. Adjust existing define and let the underlying pass to perform the optimization.
2. Add new define_split(s) for each of the shortcut optimization.
Personally I may prefer the option 1. But here we would like the figure out the one and the only one right way for the implementation. Thus, it is OK if we think option 2 is a better way for this.
Kito and Juzhe, any idea for making the decision? Thanks in advance!
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Sent: Tuesday, April 25, 2023 9:08 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Jeff Law <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>
Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass.
On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
>
> Hi Kito
>
> Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv test files auto generation.
>
> I have similar discuss with juzhe for this approach, and take Patch v2's way due to the below concern.
>
> 1. The vector.md Is quite complicated already, the maintenance may be out of control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> Sent: Friday, April 21, 2023 9:02 PM
> To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
> Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang
> <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> Hi Pan:
>
> One idea come to my mind, maybe we should add a new
> define_insn_and_split pattern instead of change @pred_mov<mode>
>
> On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
> >
> > Thanks kito, will try to reproduce this issue and keep you posted.
> >
> > Pan
> >
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> > Sent: Friday, April 21, 2023 6:17 PM
> > To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > Cc: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
> > Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang
> > <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > shortcut optimization
> >
> > I got a bunch of new fails including ICE for gcc testsuite, and some cases are hanging there, could you take a look?
> >
> > $ riscv64-unknown-linux-gnu-gcc
> > gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
> > -mabi=ilp32
> > during RTL pass: expand
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:
> > In function 'f':
> > /scratch1/kitoc/riscv-gnu-workspace/riscv-gnu-toolchain-trunk/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c:8:13:
> > internal compiler error: in maybe_gen_insn, at optabs.cc:8102
> > 8 | vbool64_t mask = *(vbool64_t*) (in + 1000000);
> > | ^~~~
> > 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102
> >
> >
> > On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
> > >
> > > Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 7:27 PM
> > > To: 'Kito Cheng' <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; 'juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>'
> > > <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
> > > Cc: 'gcc-patches' <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; 'Kito.cheng'
> > > <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Update the Patch v2 for more detail information for clarification. Please help to review continuously.
> > >
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Li, Pan2
> > > Sent: Wednesday, April 19, 2023 6:33 PM
> > > To: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> > > Cc: gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng
> > > <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > Sure thing.
> > >
> > > For Changlog, I consider it was generated automatically in previous. LOL.
> > >
> > > Pan
> > >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
> > > Sent: Wednesday, April 19, 2023 5:46 PM
> > > To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> > > Cc: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches
> > > <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>; Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>;
> > > Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
> > > Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1)
> > > shortcut optimization
> > >
> > > HI JuZhe:
> > >
> > > Thanks for explaining!
> > >
> > >
> > > Hi Pan:
> > >
> > > I think that would be helpful if JuZhe's explaining that could be written into the commit log.
> > >
> > >
> > > > gcc/ChangeLog:
> > > >
> > > > * config/riscv/riscv-v.cc (emit_pred_op):
> > > > * config/riscv/riscv-vector-builtins-bases.cc:
> > > > * config/riscv/vector.md:
> > >
> > > And don't forgot write some thing in ChangeLog...:P
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
2023-04-19 3:21 [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization pan2.li
2023-04-19 8:49 ` Li, Pan2
@ 2023-04-19 11:23 ` pan2.li
1 sibling, 0 replies; 18+ messages in thread
From: pan2.li @ 2023-04-19 11:23 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch try to adjust the RISC-V Vector RTL for the
generic shortcut optimization for RVV integer compare.
It includes compare operator eq, ne, ltu, lt, leu, le,
gtu, gt, geu and ge.
Assume we have below test code.
vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) {
return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl);
}
Before this patch:
vsetvli zero,a2,e8,m8,ta,ma
vl8re8.v v24,0(a1)
vmslt.vv v8,v24,v24
vsetvli a5,zero,e8,m8,ta,ma
vsm.v v8,0(a0)
ret
After this patch:
vsetvli zero,a2,e8,mf8,ta,ma
vmclr.m v24 <- optimized to vmclr.m
vsetvli zero,a5,e8,mf8,ta,ma
vsm.v v24,0(a0)
ret
We would like to make it happen in the generic way for the optimization.
The patch add one more operand(aka policy tail) to VMS{Compare} pattern,
to match the pred_mov<mode> (aka vmset/vmclr) pattern. We would like to
let the GCC to recognize (lt:(reg v) (reg v)) and lower it to
(const_vector:0), and then map into the pred_mov and VMS{Compare} pattern
for both the tail policy and avl operand.
The pred_mov may looks like
...(unspec:
[(match_operand 1 ...)
(match_operand 4 ...)
+ (match_operand 5 ...) <- added policy tail
(reg:SI VL)
(reg:SI VTYPE)] ...)
(match_operand 3 "vector_move_operand" ...) <-------+
(match_operand 2 "vector_undef_operand" ...) |
|
The pred_cmp may looks like |
...(unspec: |
[(match_operand 1 ...) |
(match_operand 6 ...) |
(match_operand 7 ...) |
(match_operand 8 ...) <- existing policy tail |
(reg:SI VL) |
(reg:SI VTYPE)] ...) lower to
(match_operator 3 ...) ----+ |
[(match_operator 4 ...) +-----+
(match_operator 5 "vector_arith_operand"])] ----+
(match_operand 2 "vector_undef_operand" ...)
However, there some cases in the test files cannot be optimized right
now. We will file separated patches to try to make it happen.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_pred_op): Add api to add the
policy tail or policy mask separately.
* config/riscv/riscv-vector-builtins-bases.cc: Change the
VMS{Compare} default tail policy from false to true.
* config/riscv/vector.md: Add the policy tail operand for the
pred_mov, pred_cmp.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-v.cc | 15 +-
.../riscv/riscv-vector-builtins-bases.cc | 6 +-
gcc/config/riscv/vector.md | 14 +-
.../rvv/base/integer_compare_insn_shortcut.c | 291 ++++++++++++++++++
4 files changed, 319 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 392f5d02e17..c3881920812 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -71,12 +71,23 @@ public:
add_input_operand (RVV_VUNDEF (mode), mode);
}
void add_policy_operand (enum tail_policy vta, enum mask_policy vma)
+ {
+ add_tail_policy_operand (vta);
+ add_mask_policy_operand (vma);
+ }
+
+ void add_tail_policy_operand (enum tail_policy vta)
{
rtx tail_policy_rtx = gen_int_mode (vta, Pmode);
- rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (tail_policy_rtx, Pmode);
+ }
+
+ void add_mask_policy_operand (enum mask_policy vma)
+ {
+ rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
add_input_operand (mask_policy_rtx, Pmode);
}
+
void add_avl_type_operand (avl_type type)
{
add_input_operand (gen_int_mode (type, Pmode), Pmode);
@@ -206,6 +217,8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
+ else
+ e.add_tail_policy_operand (get_prefer_tail_policy ());
if (vlmax_p)
e.add_avl_type_operand (avl_type::VLMAX);
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 52467bbc961..7c6064a5a24 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -756,7 +756,7 @@ template<rtx_code CODE>
class mask_logic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
@@ -768,7 +768,7 @@ template<rtx_code CODE>
class mask_nlogic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
@@ -780,7 +780,7 @@ template<rtx_code CODE>
class mask_notlogic : public function_base
{
public:
- bool apply_tail_policy_p () const override { return false; }
+ bool apply_tail_policy_p () const override { return true; }
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander &e) const override
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0ecca98f20c..6819363b9ff 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
@@ -4113,7 +4114,8 @@ (define_expand "@pred_ge<mode>_scalar"
if (satisfies_constraint_Wc1 (operands[1]))
emit_insn (
gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
- CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
+ CONSTM1_RTX (<VM>mode), operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
else
{
/* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
@@ -4158,7 +4160,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[6], operands[7], operands[8]));
emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
undef, operands[0], operands[0],
- operands[6], operands[8]));
+ operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
}
else
{
@@ -4173,7 +4176,8 @@ (define_expand "@pred_ge<mode>_scalar"
operands[5], operands[6], operands[7], operands[8]));
emit_insn (
gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
- operands[1], reg, operands[6], operands[8]));
+ operands[1], reg, operands[6], operands[8],
+ gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode)));
}
else
{
@@ -5196,6 +5200,7 @@ (define_insn "@pred_<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_bitwise:VB
@@ -5216,6 +5221,7 @@ (define_insn "@pred_n<optab><mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
@@ -5237,6 +5243,7 @@ (define_insn "@pred_<optab>not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 5 "vector_length_operand" " rK")
(match_operand 6 "const_int_operand" " i")
+ (match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(and_ior:VB
@@ -5258,6 +5265,7 @@ (define_insn "@pred_not<mode>"
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
+ (match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(not:VB
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
new file mode 100644
index 00000000000..495a0f11440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -0,0 +1,291 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmseq_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmseq_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmseq_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmseq_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmseq_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmseq_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmseq_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsne_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsne_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsne_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsne_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsne_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsne_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsne_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsne_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmslt_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmslt_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmslt_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmslt_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmslt_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmslt_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmslt_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsltu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsltu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsltu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsltu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsltu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsltu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsltu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsltu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsle_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsle_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsle_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsle_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsle_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsle_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsle_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsle_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsleu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsleu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsleu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsleu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsleu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsleu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsleu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsleu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgt_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgt_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgt_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgt_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgt_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgt_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgt_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgt_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgtu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgtu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgtu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgtu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgtu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgtu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgtu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgtu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsge_case_0(vint8m8_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsge_case_1(vint8m4_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsge_case_2(vint8m2_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsge_case_3(vint8m1_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsge_case_4(vint8mf2_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsge_case_5(vint8mf4_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsge_case_6(vint8mf8_t v1, size_t vl) {
+ return __riscv_vmsge_vv_i8mf8_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmsgeu_case_0(vuint8m8_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m8_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmsgeu_case_1(vuint8m4_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m4_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmsgeu_case_2(vuint8m2_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m2_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmsgeu_case_3(vuint8m1_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8m1_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmsgeu_case_4(vuint8mf2_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf2_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmsgeu_case_5(vuint8mf4_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf4_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t vl) {
+ return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 35 } } */
--
2.34.1
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2023-04-19 3:21 [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization pan2.li
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2023-04-19 9:45 ` Kito Cheng
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2023-04-25 13:08 ` Kito Cheng
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2023-04-19 11:23 ` [PATCH v2] " pan2.li
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