* [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
@ 2015-05-27 20:16 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests Christophe Lyon
` (19 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:16 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c
new file mode 100644
index 0000000..a2b40b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c
@@ -0,0 +1,143 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results with input=0. */
+VECT_VAR_DECL(expected_0,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,32,2) [] = { 0x0, 0x0 };
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff9, 0xfff9, 0xfffa };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfc, 0xfc, 0xfd, 0xfd,
+ 0xfd, 0xfd, 0xfe, 0xfe };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffffe, 0xfffffffe };
+
+/* Expected results with large shift amount. */
+VECT_VAR_DECL(expected_sh_large,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_large,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_large,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_large,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_large,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_large,uint,32,2) [] = { 0x0, 0x0 };
+
+#define TEST_MSG "VRSHRN_N"
+void exec_vrshrn_n (void)
+{
+ /* Basic test: v2=vrshrn_n(v1,v), then store the result. */
+#define TEST_VRSHRN_N(T1, T2, W, N, W2, V) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ vrshrn_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+ /* vector is twice as large as vector_res. */
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+
+ clean_results ();
+
+ /* Fill input vector with 0, to check behavior on limits. */
+ VDUP(vector, q, int, s, 16, 8, 0);
+ VDUP(vector, q, int, s, 32, 4, 0);
+ VDUP(vector, q, int, s, 64, 2, 0);
+ VDUP(vector, q, uint, u, 16, 8, 0);
+ VDUP(vector, q, uint, u, 32, 4, 0);
+ VDUP(vector, q, uint, u, 64, 2, 0);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VRSHRN_N(int, s, 16, 8, 8, 1);
+ TEST_VRSHRN_N(int, s, 32, 4, 16, 1);
+ TEST_VRSHRN_N(int, s, 64, 2, 32, 2);
+ TEST_VRSHRN_N(uint, u, 16, 8, 8, 2);
+ TEST_VRSHRN_N(uint, u, 32, 4, 16, 3);
+ TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
+
+#define CMT " (with input = 0)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0, CMT);
+
+
+ /* Test again, with predefined input values. */
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VRSHRN_N(int, s, 16, 8, 8, 1);
+ TEST_VRSHRN_N(int, s, 32, 4, 16, 1);
+ TEST_VRSHRN_N(int, s, 64, 2, 32, 2);
+ TEST_VRSHRN_N(uint, u, 16, 8, 8, 2);
+ TEST_VRSHRN_N(uint, u, 32, 4, 16, 3);
+ TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
+
+#undef CMT
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+
+
+ /* Fill input arbitrary values. */
+ VDUP(vector, q, int, s, 16, 8, 30);
+ VDUP(vector, q, int, s, 32, 4, 0);
+ VDUP(vector, q, int, s, 64, 2, 0);
+ VDUP(vector, q, uint, u, 16, 8, 0xFFF0);
+ VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFF0);
+ VDUP(vector, q, uint, u, 64, 2, 0);
+
+ /* Choose large shift amount arbitrarily. */
+ TEST_VRSHRN_N(int, s, 16, 8, 8, 7);
+ TEST_VRSHRN_N(int, s, 32, 4, 16, 14);
+ TEST_VRSHRN_N(int, s, 64, 2, 32, 31);
+ TEST_VRSHRN_N(uint, u, 16, 8, 8, 7);
+ TEST_VRSHRN_N(uint, u, 32, 4, 16, 16);
+ TEST_VRSHRN_N(uint, u, 64, 2, 32, 3);
+
+#undef CMT
+#define CMT " (with large shift amount)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_sh_large, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_sh_large, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh_large, CMT);
+}
+
+int main (void)
+{
+ exec_vrshrn_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
@ 2015-05-27 20:16 Christophe Lyon
2015-05-27 20:16 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests Christophe Lyon
` (20 more replies)
0 siblings, 21 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:16 UTC (permalink / raw)
To: gcc-patches
This patch series is a follow-up to the tests I already contributed,
converted from my original testsuite.
This series consists in 20 new patches, which can be committed
independently. For vrecpe, I added the setting of the "Flush-to-Zero"
FP flag, to force AArch64 to behave the same as ARM by default.
This is the final batch, except for the vget_lane tests which I will
submit later. This should cover the subset of AdvSIMD intrinsics
common to ARMv7 and AArch64.
Tested with qemu on arm*linux, aarch64-linux.
2015-05-27 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(_ARM_FPSCR): Add FZ field.
(clean_results): Force FZ=1 on AArch64.
* gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
Christophe Lyon (20):
Add vrecpe tests.
Add vrecps tests.
Add vreinterpret tests.
Add vrev tests.
Add vrshl tests.
Add vshr_n tests.
Add vrshr_n tests.
Add vrshrn_n tests.
Add vrsqrte tests.
Add vrsqrts tests.
Add vrsra_n tests.
Add vset_lane tests.
Add vshll_n tests.
Add vshl_n tests.
Add vshrn_n tests.
Add vsra_n tests.
Add vst1_lane tests.
Add vstX_lane tests.
Add vtbX tests.
Add vtst tests.
.../aarch64/advsimd-intrinsics/arm-neon-ref.h | 19 +-
.../gcc.target/aarch64/advsimd-intrinsics/vrecpe.c | 154 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vrecps.c | 117 ++++
.../aarch64/advsimd-intrinsics/vreinterpret.c | 741 +++++++++++++++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vrev.c | 200 ++++++
.../gcc.target/aarch64/advsimd-intrinsics/vrshl.c | 627 +++++++++++++++++
.../aarch64/advsimd-intrinsics/vrshr_n.c | 504 ++++++++++++++
.../aarch64/advsimd-intrinsics/vrshrn_n.c | 143 ++++
.../aarch64/advsimd-intrinsics/vrsqrte.c | 157 +++++
.../aarch64/advsimd-intrinsics/vrsqrts.c | 118 ++++
.../aarch64/advsimd-intrinsics/vrsra_n.c | 553 +++++++++++++++
.../aarch64/advsimd-intrinsics/vset_lane.c | 99 +++
.../gcc.target/aarch64/advsimd-intrinsics/vshl_n.c | 96 +++
.../aarch64/advsimd-intrinsics/vshll_n.c | 56 ++
.../gcc.target/aarch64/advsimd-intrinsics/vshr_n.c | 95 +++
.../aarch64/advsimd-intrinsics/vshrn_n.c | 70 ++
.../gcc.target/aarch64/advsimd-intrinsics/vsra_n.c | 117 ++++
.../aarch64/advsimd-intrinsics/vst1_lane.c | 93 +++
.../aarch64/advsimd-intrinsics/vstX_lane.c | 578 ++++++++++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vtbX.c | 289 ++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vtst.c | 120 ++++
21 files changed, 4940 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (13 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests Christophe Lyon
` (5 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c
new file mode 100644
index 0000000..d970fbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c
@@ -0,0 +1,627 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results with input=0. */
+VECT_VAR_DECL(expected_0,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_0,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_0,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0,uint,64,2) [] = { 0x0, 0x0 };
+
+/* Expected results with input=0 and negative shift amount. */
+VECT_VAR_DECL(expected_0_sh_neg,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_0_sh_neg,uint,64,2) [] = { 0x0, 0x0 };
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe0, 0xe2, 0xe4, 0xe6,
+ 0xe8, 0xea, 0xec, 0xee };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xff80, 0xff88, 0xff90, 0xff98 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff000, 0xfffff100 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffffe };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe0, 0xe2, 0xe4, 0xe6,
+ 0xe8, 0xea, 0xec, 0xee };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xff80, 0xff88, 0xff90, 0xff98 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff000, 0xfffff100 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffffffffffe };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x0, 0x1000, 0x2000, 0x3000,
+ 0x4000, 0x5000, 0x6000, 0x7000 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x8000000000000000 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x1000, 0x2000, 0x3000,
+ 0x4000, 0x5000, 0x6000, 0x7000 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x8000000000000000 };
+
+/* Expected results with negative shift amount. */
+VECT_VAR_DECL(expected_sh_neg,int,8,8) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc };
+VECT_VAR_DECL(expected_sh_neg,int,16,4) [] = { 0xfffc, 0xfffc, 0xfffd, 0xfffd };
+VECT_VAR_DECL(expected_sh_neg,int,32,2) [] = { 0xfffffffe, 0xfffffffe };
+VECT_VAR_DECL(expected_sh_neg,int,64,1) [] = { 0xffffffffffffffff };
+VECT_VAR_DECL(expected_sh_neg,uint,8,8) [] = { 0x78, 0x79, 0x79, 0x7a,
+ 0x7a, 0x7b, 0x7b, 0x7c };
+VECT_VAR_DECL(expected_sh_neg,uint,16,4) [] = { 0x3ffc, 0x3ffc, 0x3ffd, 0x3ffd };
+VECT_VAR_DECL(expected_sh_neg,uint,32,2) [] = { 0x1ffffffe, 0x1ffffffe };
+VECT_VAR_DECL(expected_sh_neg,uint,64,1) [] = { 0xfffffffffffffff };
+VECT_VAR_DECL(expected_sh_neg,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_neg,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_neg,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_neg,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_sh_neg,uint,8,16) [] = { 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected_sh_neg,uint,16,8) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_sh_neg,uint,32,4) [] = { 0x80000, 0x80000,
+ 0x80000, 0x80000 };
+VECT_VAR_DECL(expected_sh_neg,uint,64,2) [] = { 0x100000000000, 0x100000000000 };
+
+/* Expected results with max input value shifted by -1 to test
+ round_const. */
+VECT_VAR_DECL(expected_max_sh_minus1,int,8,8) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,16,4) [] = { 0x4000, 0x4000,
+ 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,32,2) [] = { 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,64,1) [] = { 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,16,4) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,64,1) [] = { 0x8000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,8,16) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,16,8) [] = { 0x4000, 0x4000,
+ 0x4000, 0x4000,
+ 0x4000, 0x4000,
+ 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,32,4) [] = { 0x40000000, 0x40000000,
+ 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,int,64,2) [] = { 0x4000000000000000,
+ 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,16,8) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh_minus1,uint,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+/* Expected results with max input value shifted by -3 to test
+ round_const. */
+VECT_VAR_DECL(expected_max_sh_minus3,int,8,8) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,16,4) [] = { 0x1000, 0x1000,
+ 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,32,2) [] = { 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,64,1) [] = { 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,8,8) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,16,4) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,32,2) [] = { 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,64,1) [] = { 0x2000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,8,16) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,16,8) [] = { 0x1000, 0x1000,
+ 0x1000, 0x1000,
+ 0x1000, 0x1000,
+ 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,32,4) [] = { 0x10000000, 0x10000000,
+ 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,int,64,2) [] = { 0x1000000000000000,
+ 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,8,16) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,16,8) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,32,4) [] = { 0x20000000, 0x20000000,
+ 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh_minus3,uint,64,2) [] = { 0x2000000000000000,
+ 0x2000000000000000 };
+
+/* Expected results with negative shift by vector width. */
+VECT_VAR_DECL(expected_max_sh_minus_width,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_minus_width,uint,64,2) [] = { 0x1, 0x1 };
+
+/* Expected results with large shift amount. */
+VECT_VAR_DECL(expected_max_sh_large,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large,uint,64,2) [] = { 0x0, 0x0 };
+
+/* Expected results with large negative shift amount. */
+VECT_VAR_DECL(expected_max_sh_large_neg,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_large_neg,uint,64,2) [] = { 0x1, 0x1 };
+
+#define TEST_MSG "VRSHL/VRSHLQ"
+void exec_vrshl (void)
+{
+ /* Basic test: v3=vrshl(v1,v2), then store the result. */
+#define TEST_VRSHL(T3, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrshl##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector_shift, T3, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ DECL_VARIABLE_SIGNED_VARIANTS(vector_shift);
+
+ clean_results ();
+
+ /* Fill input vector with 0, to check behavior on limits. */
+ VDUP(vector, , int, s, 8, 8, 0);
+ VDUP(vector, , int, s, 16, 4, 0);
+ VDUP(vector, , int, s, 32, 2, 0);
+ VDUP(vector, , int, s, 64, 1, 0);
+ VDUP(vector, , uint, u, 8, 8, 0);
+ VDUP(vector, , uint, u, 16, 4, 0);
+ VDUP(vector, , uint, u, 32, 2, 0);
+ VDUP(vector, , uint, u, 64, 1, 0);
+ VDUP(vector, q, int, s, 8, 16, 0);
+ VDUP(vector, q, int, s, 16, 8, 0);
+ VDUP(vector, q, int, s, 32, 4, 0);
+ VDUP(vector, q, int, s, 64, 2, 0);
+ VDUP(vector, q, uint, u, 8, 16, 0);
+ VDUP(vector, q, uint, u, 16, 8, 0);
+ VDUP(vector, q, uint, u, 32, 4, 0);
+ VDUP(vector, q, uint, u, 64, 2, 0);
+
+ /* Choose init value arbitrarily, will be used as shift amount. */
+ /* Use values equal to one-less-than the type width to check
+ behaviour on limits. */
+ VDUP(vector_shift, , int, s, 8, 8, 7);
+ VDUP(vector_shift, , int, s, 16, 4, 15);
+ VDUP(vector_shift, , int, s, 32, 2, 31);
+ VDUP(vector_shift, , int, s, 64, 1, 63);
+ VDUP(vector_shift, q, int, s, 8, 16, 7);
+ VDUP(vector_shift, q, int, s, 16, 8, 15);
+ VDUP(vector_shift, q, int, s, 32, 4, 31);
+ VDUP(vector_shift, q, int, s, 64, 2, 63);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#define CMT " (with input = 0)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_0, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_0, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_0, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_0, CMT);
+
+
+ /* Use negative shift amounts. */
+ VDUP(vector_shift, , int, s, 8, 8, -1);
+ VDUP(vector_shift, , int, s, 16, 4, -2);
+ VDUP(vector_shift, , int, s, 32, 2, -3);
+ VDUP(vector_shift, , int, s, 64, 1, -4);
+ VDUP(vector_shift, q, int, s, 8, 16, -7);
+ VDUP(vector_shift, q, int, s, 16, 8, -11);
+ VDUP(vector_shift, q, int, s, 32, 4, -13);
+ VDUP(vector_shift, q, int, s, 64, 2, -20);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (input 0 and negative shift amount)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_0_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_0_sh_neg, CMT);
+
+
+ /* Test again, with predefined input values. */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose init value arbitrarily, will be used as shift amount. */
+ VDUP(vector_shift, , int, s, 8, 8, 1);
+ VDUP(vector_shift, , int, s, 16, 4, 3);
+ VDUP(vector_shift, , int, s, 32, 2, 8);
+ VDUP(vector_shift, , int, s, 64, 1, -3);
+ VDUP(vector_shift, q, int, s, 8, 16, 10);
+ VDUP(vector_shift, q, int, s, 16, 8, 12);
+ VDUP(vector_shift, q, int, s, 32, 4, 32);
+ VDUP(vector_shift, q, int, s, 64, 2, 63);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+
+
+ /* Use negative shift amounts. */
+ VDUP(vector_shift, , int, s, 8, 8, -1);
+ VDUP(vector_shift, , int, s, 16, 4, -2);
+ VDUP(vector_shift, , int, s, 32, 2, -3);
+ VDUP(vector_shift, , int, s, 64, 1, -4);
+ VDUP(vector_shift, q, int, s, 8, 16, -7);
+ VDUP(vector_shift, q, int, s, 16, 8, -11);
+ VDUP(vector_shift, q, int, s, 32, 4, -13);
+ VDUP(vector_shift, q, int, s, 64, 2, -20);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (negative shift amount)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_sh_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_sh_neg, CMT);
+
+ /* Fill input vector with max value, to check behavior on limits. */
+ VDUP(vector, , int, s, 8, 8, 0x7F);
+ VDUP(vector, , int, s, 16, 4, 0x7FFF);
+ VDUP(vector, , int, s, 32, 2, 0x7FFFFFFF);
+ VDUP(vector, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector, , uint, u, 8, 8, 0xFF);
+ VDUP(vector, , uint, u, 16, 4, 0xFFFF);
+ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
+ VDUP(vector, q, int, s, 8, 16, 0x7F);
+ VDUP(vector, q, int, s, 16, 8, 0x7FFF);
+ VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF);
+ VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector, q, uint, u, 8, 16, 0xFF);
+ VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
+ VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
+ VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
+
+ /* Use -1 shift amount to check overflow with round_const. */
+ VDUP(vector_shift, , int, s, 8, 8, -1);
+ VDUP(vector_shift, , int, s, 16, 4, -1);
+ VDUP(vector_shift, , int, s, 32, 2, -1);
+ VDUP(vector_shift, , int, s, 64, 1, -1);
+ VDUP(vector_shift, q, int, s, 8, 16, -1);
+ VDUP(vector_shift, q, int, s, 16, 8, -1);
+ VDUP(vector_shift, q, int, s, 32, 4, -1);
+ VDUP(vector_shift, q, int, s, 64, 2, -1);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (max input, shift by -1)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_minus1, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_minus1, CMT);
+
+ /* Use -3 shift amount to check overflow with round_const. */
+ VDUP(vector_shift, , int, s, 8, 8, -3);
+ VDUP(vector_shift, , int, s, 16, 4, -3);
+ VDUP(vector_shift, , int, s, 32, 2, -3);
+ VDUP(vector_shift, , int, s, 64, 1, -3);
+ VDUP(vector_shift, q, int, s, 8, 16, -3);
+ VDUP(vector_shift, q, int, s, 16, 8, -3);
+ VDUP(vector_shift, q, int, s, 32, 4, -3);
+ VDUP(vector_shift, q, int, s, 64, 2, -3);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (check rounding constant: max input, shift by -3)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_minus3, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_minus3, CMT);
+
+
+ /* Use negative shift amount as large as input vector width. */
+ VDUP(vector_shift, , int, s, 8, 8, -8);
+ VDUP(vector_shift, , int, s, 16, 4, -16);
+ VDUP(vector_shift, , int, s, 32, 2, -32);
+ VDUP(vector_shift, , int, s, 64, 1, -64);
+ VDUP(vector_shift, q, int, s, 8, 16, -8);
+ VDUP(vector_shift, q, int, s, 16, 8, -16);
+ VDUP(vector_shift, q, int, s, 32, 4, -32);
+ VDUP(vector_shift, q, int, s, 64, 2, -64);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (max input, right shift by vector width)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_minus_width, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_minus_width, CMT);
+
+
+ /* Test large shift amount. */
+ VDUP(vector_shift, , int, s, 8, 8, 10);
+ VDUP(vector_shift, , int, s, 16, 4, 20);
+ VDUP(vector_shift, , int, s, 32, 2, 33);
+ VDUP(vector_shift, , int, s, 64, 1, 65);
+ VDUP(vector_shift, q, int, s, 8, 16, 9);
+ VDUP(vector_shift, q, int, s, 16, 8, 16);
+ VDUP(vector_shift, q, int, s, 32, 4, 32);
+ VDUP(vector_shift, q, int, s, 64, 2, 64);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (max input, large shift amount)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_large, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_large, CMT);
+
+
+ /* Test large negative shift amount. */
+ VDUP(vector_shift, , int, s, 8, 8, -10);
+ VDUP(vector_shift, , int, s, 16, 4, -20);
+ VDUP(vector_shift, , int, s, 32, 2, -33);
+ VDUP(vector_shift, , int, s, 64, 1, -65);
+ VDUP(vector_shift, q, int, s, 8, 16, -9);
+ VDUP(vector_shift, q, int, s, 16, 8, -16);
+ VDUP(vector_shift, q, int, s, 32, 4, -32);
+ VDUP(vector_shift, q, int, s, 64, 2, -64);
+
+ TEST_MACRO_ALL_VARIANTS_1_5(TEST_VRSHL, int);
+
+#undef CMT
+#define CMT " (max input, large negative shift amount)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_large_neg, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_large_neg, CMT);
+}
+
+int main (void)
+{
+ exec_vrshl ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (7 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests Christophe Lyon
` (11 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c
new file mode 100644
index 0000000..07bc904d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c
@@ -0,0 +1,56 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe0, 0xffe2, 0xffe4, 0xffe6,
+ 0xffe8, 0xffea, 0xffec, 0xffee };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe0, 0xffffffe2,
+ 0xffffffe4, 0xffffffe6 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffff80, 0xffffffffffffff88 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3c0, 0x3c4, 0x3c8, 0x3cc,
+ 0x3d0, 0x3d4, 0x3d8, 0x3dc };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff00, 0xfff10, 0xfff20, 0xfff30 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x7ffffff80, 0x7ffffff88 };
+
+#define TEST_MSG "VSHLL_N"
+void exec_vshll_n (void)
+{
+ /* Basic test: v2=vshll_n(v1,v), then store the result. */
+#define TEST_VSHLL_N(T1, T2, W, W2, N, V) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ vshll##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1q##_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSHLL_N(int, s, 8, 16, 8, 1);
+ TEST_VSHLL_N(int, s, 16, 32, 4, 1);
+ TEST_VSHLL_N(int, s, 32, 64, 2, 3);
+ TEST_VSHLL_N(uint, u, 8, 16, 8, 2);
+ TEST_VSHLL_N(uint, u, 16, 32, 4, 4);
+ TEST_VSHLL_N(uint, u, 32, 64, 2, 3);
+
+#undef CMT
+#define CMT ""
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+}
+
+int main (void)
+{
+ exec_vshll_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (5 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests Christophe Lyon
` (13 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
new file mode 100644
index 0000000..08583b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
@@ -0,0 +1,93 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf7, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff3, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf6, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff2, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf6, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff2, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xff, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff5, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff1, 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfa, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff4, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff3, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xfa, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff4, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#define TEST_MSG "VST1_LANE/VST1_LANEQ"
+void exec_vst1_lane (void)
+{
+#define TEST_VST1_LANE(Q, T1, T2, W, N, L) \
+ VECT_VAR(vector, T1, W, N) = \
+ vld1##Q##_##T2##W(VECT_VAR(buffer, T1, W, N)); \
+ vst1##Q##_lane_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector, T1, W, N), L)
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+
+ clean_results ();
+
+ /* Choose lane arbitrarily. */
+ TEST_VST1_LANE(, int, s, 8, 8, 7);
+ TEST_VST1_LANE(, int, s, 16, 4, 3);
+ TEST_VST1_LANE(, int, s, 32, 2, 1);
+ TEST_VST1_LANE(, int, s, 64, 1, 0);
+ TEST_VST1_LANE(, uint, u, 8, 8, 6);
+ TEST_VST1_LANE(, uint, u, 16, 4, 2);
+ TEST_VST1_LANE(, uint, u, 32, 2, 0);
+ TEST_VST1_LANE(, uint, u, 64, 1, 0);
+ TEST_VST1_LANE(, poly, p, 8, 8, 6);
+ TEST_VST1_LANE(, poly, p, 16, 4, 2);
+ TEST_VST1_LANE(, float, f, 32, 2, 1);
+
+ TEST_VST1_LANE(q, int, s, 8, 16, 15);
+ TEST_VST1_LANE(q, int, s, 16, 8, 5);
+ TEST_VST1_LANE(q, int, s, 32, 4, 1);
+ TEST_VST1_LANE(q, int, s, 64, 2, 1);
+ TEST_VST1_LANE(q, uint, u, 8, 16, 10);
+ TEST_VST1_LANE(q, uint, u, 16, 8, 4);
+ TEST_VST1_LANE(q, uint, u, 32, 4, 3);
+ TEST_VST1_LANE(q, uint, u, 64, 2, 0);
+ TEST_VST1_LANE(q, poly, p, 8, 16, 10);
+ TEST_VST1_LANE(q, poly, p, 16, 8, 4);
+ TEST_VST1_LANE(q, float, f, 32, 4, 1);
+
+ CHECK_RESULTS(TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vst1_lane ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (10 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests Christophe Lyon
` (8 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c
new file mode 100644
index 0000000..d807ebb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c
@@ -0,0 +1,96 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe0, 0xe2, 0xe4, 0xe6,
+ 0xe8, 0xea, 0xec, 0xee };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe0, 0xffe2, 0xffe4, 0xffe6 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffff80, 0xffffff88 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffc0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc0, 0xc4, 0xc8, 0xcc,
+ 0xd0, 0xd4, 0xd8, 0xdc };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xff00, 0xff10, 0xff20, 0xff30 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffff80, 0xffffff88 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffffe0 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x20, 0x40, 0x60,
+ 0x80, 0xa0, 0xc0, 0xe0,
+ 0x0, 0x20, 0x40, 0x60,
+ 0x80, 0xa0, 0xc0, 0xe0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe0, 0xffe2, 0xffe4, 0xffe6,
+ 0xffe8, 0xffea, 0xffec, 0xffee };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffc0, 0xffffffc4,
+ 0xffffffc8, 0xffffffcc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffc0, 0xffffffffffffffc4 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xc0, 0xc4, 0xc8, 0xcc,
+ 0xd0, 0xd4, 0xd8, 0xdc,
+ 0xe0, 0xe4, 0xe8, 0xec,
+ 0xf0, 0xf4, 0xf8, 0xfc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xff80, 0xff88, 0xff90, 0xff98,
+ 0xffa0, 0xffa8, 0xffb0, 0xffb8 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffc0, 0xffffffc4,
+ 0xffffffc8, 0xffffffcc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffe0,
+ 0xffffffffffffffe2 };
+
+#define TEST_MSG "VSHL_N"
+void exec_vshl_n (void)
+{
+ /* Basic test: v2=vshl_n(v1,v), then store the result. */
+#define TEST_VSHL_N(Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vshl##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSHL_N(, int, s, 8, 8, 1);
+ TEST_VSHL_N(, int, s, 16, 4, 1);
+ TEST_VSHL_N(, int, s, 32, 2, 3);
+ TEST_VSHL_N(, int, s, 64, 1, 2);
+ TEST_VSHL_N(, uint, u, 8, 8, 2);
+ TEST_VSHL_N(, uint, u, 16, 4, 4);
+ TEST_VSHL_N(, uint, u, 32, 2, 3);
+ TEST_VSHL_N(, uint, u, 64, 1, 1);
+
+ TEST_VSHL_N(q, int, s, 8, 16, 5);
+ TEST_VSHL_N(q, int, s, 16, 8, 1);
+ TEST_VSHL_N(q, int, s, 32, 4, 2);
+ TEST_VSHL_N(q, int, s, 64, 2, 2);
+ TEST_VSHL_N(q, uint, u, 8, 16, 2);
+ TEST_VSHL_N(q, uint, u, 16, 8, 3);
+ TEST_VSHL_N(q, uint, u, 32, 4, 2);
+ TEST_VSHL_N(q, uint, u, 64, 2, 1);
+
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+}
+
+int main (void)
+{
+ exec_vshl_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (11 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests Christophe Lyon
` (7 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
In order to have the same behaviour on ARM and AArch64 targets, we
need to force flush to zero on AArch64.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 1742e99..4e728d5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -235,7 +235,8 @@ extern ARRAY(expected, hfloat, 64, 2);
typedef union {
struct {
- int _xxx:25;
+ int _xxx:24;
+ unsigned int FZ:1;
unsigned int DN:1;
unsigned int AHP:1;
unsigned int QC:1;
@@ -258,7 +259,8 @@ typedef union {
unsigned int QC:1;
unsigned int AHP:1;
unsigned int DN:1;
- int _dnm:25;
+ unsigned int FZ:1;
+ int _dnm:24;
} b;
unsigned int word;
} _ARM_FPSCR;
@@ -395,10 +397,15 @@ static void clean_results (void)
#if defined(__aarch64__)
/* On AArch64, make sure to return DefaultNaN to have the same
results as on AArch32. */
- _ARM_FPSCR _afpscr_for_dn;
- asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
- _afpscr_for_dn.b.DN = 1;
- asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
+ _ARM_FPSCR _afpscr;
+ asm volatile ("mrs %0,fpcr" : "=r" (_afpscr));
+ _afpscr.b.DN = 1;
+
+ /* On AArch64, make sure to flush to zero by default, as on
+ AArch32. */
+ _afpscr.b.FZ = 1;
+
+ asm volatile ("msr fpcr,%0" : : "r" (_afpscr));
#endif
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
new file mode 100644
index 0000000..55b45b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
@@ -0,0 +1,154 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+#include <math.h>
+
+/* Expected results with positive input. */
+VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000,
+ 0xbf000000, 0xbf000000 };
+VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 };
+VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000,
+ 0x3c030000, 0x3c030000 };
+
+/* Expected results with negative input. */
+VECT_VAR_DECL(expected_negative,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_negative,uint,32,4) [] = { 0xee800000, 0xee800000,
+ 0xee800000, 0xee800000 };
+VECT_VAR_DECL(expected_negative,hfloat,32,2) [] = { 0xbdcc8000, 0xbdcc8000 };
+VECT_VAR_DECL(expected_negative,hfloat,32,4) [] = { 0xbc030000, 0xbc030000,
+ 0xbc030000, 0xbc030000 };
+
+/* Expected results with FP special values (NaN, infinity). */
+VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results with FP special values (zero, large value). */
+VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7f800000, 0x7f800000 };
+VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results with FP special values (-0, -infinity). */
+VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+
+/* Expected results with FP special large negative value. */
+VECT_VAR_DECL(expected_fp4,hfloat,32,2) [] = { 0x80000000, 0x80000000 };
+
+#define TEST_MSG "VRECPE/VRECPEQ"
+void exec_vrecpe(void)
+{
+ int i;
+
+ /* Basic test: y=vrecpe(x), then store the result. */
+#define TEST_VRECPE(Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrecpe##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, float, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 4);
+
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 4);
+
+ clean_results ();
+
+ /* Choose init value arbitrarily, positive. */
+ VDUP(vector, , uint, u, 32, 2, 0x12345678);
+ VDUP(vector, , float, f, 32, 2, 1.9f);
+ VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
+ VDUP(vector, q, float, f, 32, 4, 125.0f);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, uint, u, 32, 2);
+ TEST_VRECPE(, float, f, 32, 2);
+ TEST_VRECPE(q, uint, u, 32, 4);
+ TEST_VRECPE(q, float, f, 32, 4);
+
+#define CMT " (positive input)"
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT);
+
+ /* Choose init value arbitrarily,negative. */
+ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector, , float, f, 32, 2, -10.0f);
+ VDUP(vector, q, uint, u, 32, 4, 0x89081234);
+ VDUP(vector, q, float, f, 32, 4, -125.0f);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, uint, u, 32, 2);
+ TEST_VRECPE(, float, f, 32, 2);
+ TEST_VRECPE(q, uint, u, 32, 4);
+ TEST_VRECPE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " (negative input)"
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_negative, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_negative, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_negative, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_negative, CMT);
+
+ /* Test FP variants with special input values (NaN, infinity). */
+ VDUP(vector, , float, f, 32, 2, NAN);
+ VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, float, f, 32, 2);
+ TEST_VRECPE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (NaN, infinity)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+
+ /* Test FP variants with special input values (zero, large value). */
+ VDUP(vector, , float, f, 32, 2, 0.0f);
+ VDUP(vector, q, float, f, 32, 4, 8.97229e37f /*9.0e37f*/);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, float, f, 32, 2);
+ TEST_VRECPE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (zero, large value)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+
+ /* Test FP variants with special input values (-0, -infinity). */
+ VDUP(vector, , float, f, 32, 2, -0.0f);
+ VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, float, f, 32, 2);
+ TEST_VRECPE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (-0, -infinity)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+
+ /* Test FP variants with special input values (large negative value). */
+ VDUP(vector, , float, f, 32, 2, -9.0e37f);
+
+ /* Apply the operator. */
+ TEST_VRECPE(, float, f, 32, 2);
+
+#undef CMT
+#define CMT " FP special (large negative value)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp4, CMT);
+}
+
+int main (void)
+{
+ exec_vrecpe ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (12 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests Christophe Lyon
` (6 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
new file mode 100644
index 0000000..0e41947
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
@@ -0,0 +1,117 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+#include <math.h>
+
+/* Expected results with positive input. */
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2e19eb7, 0xc2e19eb7 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1db851f, 0xc1db851f,
+ 0xc1db851f, 0xc1db851f };
+
+/* Expected results with FP special values (NaN). */
+VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+
+/* Expected results with FP special values (infinity, 0) and normal
+ values. */
+VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 0x40000000, 0x40000000 };
+
+/* Expected results with FP special values (infinity, 0). */
+VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 0x40000000, 0x40000000 };
+
+#define TEST_MSG "VRECPS/VRECPSQ"
+void exec_vrecps(void)
+{
+ int i;
+
+ /* Basic test: y=vrecps(x), then store the result. */
+#define TEST_VRECPS(Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrecps##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ /* No need for integer variants. */
+ DECL_VARIABLE(vector, float, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 4);
+
+ DECL_VARIABLE(vector2, float, 32, 2);
+ DECL_VARIABLE(vector2, float, 32, 4);
+
+ DECL_VARIABLE(vector_res, float, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 4);
+
+ clean_results ();
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector, , float, f, 32, 2, 12.9f);
+ VDUP(vector, q, float, f, 32, 4, 9.2f);
+
+ VDUP(vector2, , float, f, 32, 2, 8.9f);
+ VDUP(vector2, q, float, f, 32, 4, 3.2f);
+
+ /* Apply the operator. */
+ TEST_VRECPS(, float, f, 32, 2);
+ TEST_VRECPS(q, float, f, 32, 4);
+
+#define CMT " (positive input)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+
+
+ /* Test FP variants with special input values (NaN). */
+ VDUP(vector, , float, f, 32, 2, NAN);
+ VDUP(vector2, q, float, f, 32, 4, NAN);
+
+ /* Apply the operator. */
+ TEST_VRECPS(, float, f, 32, 2);
+ TEST_VRECPS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (NaN)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+
+
+ /* Test FP variants with special input values (infinity, 0). */
+ VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Restore a normal value. */
+
+ /* Apply the operator. */
+ TEST_VRECPS(, float, f, 32, 2);
+ TEST_VRECPS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (infinity, 0) and normal value"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+
+
+ /* Test FP variants with only special input values (infinity, 0). */
+ VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ VDUP(vector2, , float, f, 32, 2, 0.0f);
+ VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+
+ /* Apply the operator */
+ TEST_VRECPS(, float, f, 32, 2);
+ TEST_VRECPS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (infinity, 0)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+}
+
+int main (void)
+{
+ exec_vrecps ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (9 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests Christophe Lyon
` (9 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
new file mode 100644
index 0000000..9e45e25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -0,0 +1,741 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results for vreinterpret_s8_xx. */
+VECT_VAR_DECL(expected_s8_1,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_s8_2,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_s8_3,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_s8_4,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_s8_5,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_s8_6,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_s8_7,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+
+/* Expected results for vreinterpret_s16_xx. */
+VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_s16_2,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_s16_3,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_s16_4,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_s16_5,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+
+/* Expected results for vreinterpret_s32_xx. */
+VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_s32_2,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_s32_3,int,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_s32_4,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_s32_5,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+
+/* Expected results for vreinterpret_s64_xx. */
+VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_s64_2,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_s64_3,int,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(expected_s64_4,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_s64_5,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+
+/* Expected results for vreinterpret_u8_xx. */
+VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_u8_2,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_u8_3,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_u8_4,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_u8_5,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_u8_6,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_u8_7,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+
+/* Expected results for vreinterpret_u16_xx. */
+VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_u16_2,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_u16_3,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_u16_4,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_u16_5,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+
+/* Expected results for vreinterpret_u32_xx. */
+VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_u32_2,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_u32_3,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_u32_4,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_u32_5,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+
+/* Expected results for vreinterpret_u64_xx. */
+VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_u64_2,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_u64_3,uint,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(expected_u64_4,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_u64_5,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
+VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+
+/* Expected results for vreinterpret_p8_xx. */
+VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_p8_2,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_p8_3,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_p8_4,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_p8_5,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_p8_6,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_p8_7,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff };
+
+/* Expected results for vreinterpret_p16_xx. */
+VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_p16_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_p16_3,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_p16_4,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_p16_5,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+
+/* Expected results for vreinterpretq_s8_xx. */
+VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_s8_2,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xf2, 0xff, 0xff, 0xff,
+ 0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_s8_3,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_s8_4,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_s8_5,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_s8_6,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xf2, 0xff, 0xff, 0xff,
+ 0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_s8_7,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_s8_8,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+
+/* Expected results for vreinterpretq_s16_xx. */
+VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_s16_2,int,16,8) [] = { 0xfff0, 0xffff,
+ 0xfff1, 0xffff,
+ 0xfff2, 0xffff,
+ 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_s16_3,int,16,8) [] = { 0xfff0, 0xffff,
+ 0xffff, 0xffff,
+ 0xfff1, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_s16_4,int,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_s16_5,int,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_s16_6,int,16,8) [] = { 0xfff0, 0xffff,
+ 0xfff1, 0xffff,
+ 0xfff2, 0xffff,
+ 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_s16_7,int,16,8) [] = { 0xfff0, 0xffff,
+ 0xffff, 0xffff,
+ 0xfff1, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_s16_8,int,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+
+/* Expected results for vreinterpretq_s32_xx. */
+VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_s32_2,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_s32_3,int,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_s32_4,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_s32_5,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_s32_6,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_q_s32_7,int,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+
+/* Expected results for vreinterpretq_s64_xx. */
+VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_s64_2,int,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(expected_q_s64_3,int,64,2) [] = { 0xfffffff1fffffff0,
+ 0xfffffff3fffffff2 };
+VECT_VAR_DECL(expected_q_s64_4,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_s64_5,int,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(expected_q_s64_6,int,64,2) [] = { 0xfffffff1fffffff0,
+ 0xfffffff3fffffff2 };
+VECT_VAR_DECL(expected_q_s64_7,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+
+/* Expected results for vreinterpretq_u8_xx. */
+VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_u8_2,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_u8_3,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xf2, 0xff, 0xff, 0xff,
+ 0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_u8_4,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_u8_5,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+VECT_VAR_DECL(expected_q_u8_6,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xf2, 0xff, 0xff, 0xff,
+ 0xf3, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_u8_7,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf1, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_q_u8_8,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 0xf2, 0xff, 0xf3, 0xff,
+ 0xf4, 0xff, 0xf5, 0xff,
+ 0xf6, 0xff, 0xf7, 0xff };
+
+/* Expected results for vreinterpretq_u16_xx. */
+VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_u16_2,uint,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_q_u16_3,uint,16,8) [] = { 0xfff0, 0xffff,
+ 0xfff1, 0xffff,
+ 0xfff2, 0xffff,
+ 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_u16_4,uint,16,8) [] = { 0xfff0, 0xffff,
+ 0xffff, 0xffff,
+ 0xfff1, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_u16_5,uint,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_u16_6,uint,16,8) [] = { 0xfff0, 0xffff,
+ 0xfff1, 0xffff,
+ 0xfff2, 0xffff,
+ 0xfff3, 0xffff };
+VECT_VAR_DECL(expected_q_u16_7,uint,16,8) [] = { 0xfff0, 0xffff,
+ 0xffff, 0xffff,
+ 0xfff1, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_q_u16_8,uint,16,8) [] = { 0xf1f0, 0xf3f2,
+ 0xf5f4, 0xf7f6,
+ 0xf9f8, 0xfbfa,
+ 0xfdfc, 0xfffe };
+VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+
+/* Expected results for vreinterpretq_u32_xx. */
+VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_u32_2,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_u32_3,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_q_u32_4,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_u32_5,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_u32_6,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_u32_7,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+
+/* Expected results for vreinterpretq_u64_xx. */
+VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_u64_2,uint,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(expected_q_u64_3,uint,64,2) [] = { 0xfffffff1fffffff0,
+ 0xfffffff3fffffff2 };
+VECT_VAR_DECL(expected_q_u64_4,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_q_u64_5,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_u64_6,uint,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+VECT_VAR_DECL(expected_q_u64_7,uint,64,2) [] = { 0xfffffff1fffffff0,
+ 0xfffffff3fffffff2 };
+VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 0xfffefdfcfbfaf9f8 };
+VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
+ 0xfff7fff6fff5fff4 };
+
+/* Expected results for vreinterpret_f32_xx. */
+VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_f32_2,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_f32_3,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_f32_4,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_f32_5,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_f32_6,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+
+/* Expected results for vreinterpretq_f32_xx. */
+VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_f32_2,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_f32_3,hfloat,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_q_f32_4,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_f32_5,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_f32_6,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+VECT_VAR_DECL(expected_q_f32_7,hfloat,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_q_f32_8,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
+ 0xfffffff1, 0xffffffff };
+VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 0xfbfaf9f8, 0xfffefdfc };
+VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 0xfff5fff4, 0xfff7fff6 };
+
+/* Expected results for vreinterpretq_xx_f32. */
+VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1 };
+VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+VECT_VAR_DECL(expected_xx_f32_3,int,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_xx_f32_4,int,64,1) [] = { 0xc1700000c1800000 };
+VECT_VAR_DECL(expected_xx_f32_5,uint,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1 };
+VECT_VAR_DECL(expected_xx_f32_6,uint,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+VECT_VAR_DECL(expected_xx_f32_7,uint,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
+VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1 };
+VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+
+/* Expected results for vreinterpretq_xx_f32. */
+VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1,
+ 0x0, 0x0, 0x60, 0xc1,
+ 0x0, 0x0, 0x50, 0xc1 };
+VECT_VAR_DECL(expected_q_xx_f32_2,int,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+ 0x0, 0xc160, 0x0, 0xc150 };
+VECT_VAR_DECL(expected_q_xx_f32_3,int,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0xc1500000 };
+VECT_VAR_DECL(expected_q_xx_f32_4,int,64,2) [] = { 0xc1700000c1800000,
+ 0xc1500000c1600000 };
+VECT_VAR_DECL(expected_q_xx_f32_5,uint,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1,
+ 0x0, 0x0, 0x60, 0xc1,
+ 0x0, 0x0, 0x50, 0xc1 };
+VECT_VAR_DECL(expected_q_xx_f32_6,uint,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+ 0x0, 0xc160, 0x0, 0xc150 };
+VECT_VAR_DECL(expected_q_xx_f32_7,uint,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0xc1500000 };
+VECT_VAR_DECL(expected_q_xx_f32_8,uint,64,2) [] = { 0xc1700000c1800000,
+ 0xc1500000c1600000 };
+VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 0x0, 0x0, 0x70, 0xc1,
+ 0x0, 0x0, 0x60, 0xc1,
+ 0x0, 0x0, 0x50, 0xc1 };
+VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+ 0x0, 0xc160, 0x0, 0xc150 };
+
+#define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
+
+void exec_vreinterpret (void)
+{
+ int i;
+
+ /* Basic test: y=vreinterpret(x), then store the result. */
+#define TEST_VREINTERPRET(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vector, TS1, WS, NS)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+#define TEST_VREINTERPRET_POLY(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vector, TS1, WS, NS)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+#define TEST_VREINTERPRET_FP(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vector, TS1, WS, NS)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ /* vreinterpret_s8_xx. */
+ TEST_VREINTERPRET(, int, s, 8, 8, int, s, 16, 4, expected_s8_1);
+ TEST_VREINTERPRET(, int, s, 8, 8, int, s, 32, 2, expected_s8_2);
+ TEST_VREINTERPRET(, int, s, 8, 8, int, s, 64, 1, expected_s8_3);
+ TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 8, 8, expected_s8_4);
+ TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 16, 4, expected_s8_5);
+ TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 32, 2, expected_s8_6);
+ TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
+ TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
+ TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
+
+ /* vreinterpret_s16_xx. */
+ TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
+ TEST_VREINTERPRET(, int, s, 16, 4, int, s, 32, 2, expected_s16_2);
+ TEST_VREINTERPRET(, int, s, 16, 4, int, s, 64, 1, expected_s16_3);
+ TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 8, 8, expected_s16_4);
+ TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 16, 4, expected_s16_5);
+ TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 32, 2, expected_s16_6);
+ TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
+ TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
+ TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
+
+ /* vreinterpret_s32_xx. */
+ TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
+ TEST_VREINTERPRET(, int, s, 32, 2, int, s, 16, 4, expected_s32_2);
+ TEST_VREINTERPRET(, int, s, 32, 2, int, s, 64, 1, expected_s32_3);
+ TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 8, 8, expected_s32_4);
+ TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 16, 4, expected_s32_5);
+ TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 32, 2, expected_s32_6);
+ TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
+ TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
+ TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
+
+ /* vreinterpret_s64_xx. */
+ TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
+ TEST_VREINTERPRET(, int, s, 64, 1, int, s, 16, 4, expected_s64_2);
+ TEST_VREINTERPRET(, int, s, 64, 1, int, s, 32, 2, expected_s64_3);
+ TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 8, 8, expected_s64_4);
+ TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 16, 4, expected_s64_5);
+ TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 32, 2, expected_s64_6);
+ TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
+ TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
+ TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
+
+ /* vreinterpret_u8_xx. */
+ TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
+ TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 16, 4, expected_u8_2);
+ TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 32, 2, expected_u8_3);
+ TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 64, 1, expected_u8_4);
+ TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 16, 4, expected_u8_5);
+ TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 32, 2, expected_u8_6);
+ TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
+ TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
+ TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
+
+ /* vreinterpret_u16_xx. */
+ TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
+ TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 16, 4, expected_u16_2);
+ TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 32, 2, expected_u16_3);
+ TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 64, 1, expected_u16_4);
+ TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 8, 8, expected_u16_5);
+ TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 32, 2, expected_u16_6);
+ TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
+ TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
+ TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
+
+ /* vreinterpret_u32_xx. */
+ TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
+ TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 16, 4, expected_u32_2);
+ TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 32, 2, expected_u32_3);
+ TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 64, 1, expected_u32_4);
+ TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 8, 8, expected_u32_5);
+ TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 16, 4, expected_u32_6);
+ TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
+ TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
+ TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
+
+ /* vreinterpret_u64_xx. */
+ TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
+ TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 16, 4, expected_u64_2);
+ TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 32, 2, expected_u64_3);
+ TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 64, 1, expected_u64_4);
+ TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 8, 8, expected_u64_5);
+ TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 16, 4, expected_u64_6);
+ TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
+ TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
+ TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
+
+ /* vreinterpret_p8_xx. */
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 16, 4, expected_p8_2);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 32, 2, expected_p8_3);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 64, 1, expected_p8_4);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 8, 8, expected_p8_5);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 16, 4, expected_p8_6);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
+
+ /* vreinterpret_p16_xx. */
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 16, 4, expected_p16_2);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 32, 2, expected_p16_3);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 64, 1, expected_p16_4);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 8, 8, expected_p16_5);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 16, 4, expected_p16_6);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
+
+ /* vreinterpretq_s8_xx. */
+ TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
+ TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 32, 4, expected_q_s8_2);
+ TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 64, 2, expected_q_s8_3);
+ TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 8, 16, expected_q_s8_4);
+ TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 16, 8, expected_q_s8_5);
+ TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 32, 4, expected_q_s8_6);
+ TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
+ TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
+ TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
+
+ /* vreinterpretq_s16_xx. */
+ TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
+ TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 32, 4, expected_q_s16_2);
+ TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 64, 2, expected_q_s16_3);
+ TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 8, 16, expected_q_s16_4);
+ TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 16, 8, expected_q_s16_5);
+ TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 32, 4, expected_q_s16_6);
+ TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
+ TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
+ TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
+
+ /* vreinterpretq_s32_xx. */
+ TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
+ TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 16, 8, expected_q_s32_2);
+ TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 64, 2, expected_q_s32_3);
+ TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 8, 16, expected_q_s32_4);
+ TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 16, 8, expected_q_s32_5);
+ TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 32, 4, expected_q_s32_6);
+ TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
+ TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
+ TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
+
+ /* vreinterpretq_s64_xx. */
+ TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
+ TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 16, 8, expected_q_s64_2);
+ TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 32, 4, expected_q_s64_3);
+ TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 8, 16, expected_q_s64_4);
+ TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 16, 8, expected_q_s64_5);
+ TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 32, 4, expected_q_s64_6);
+ TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
+ TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
+ TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
+
+ /* vreinterpretq_u8_xx. */
+ TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 16, 8, expected_q_u8_2);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 32, 4, expected_q_u8_3);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 64, 2, expected_q_u8_4);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 16, 8, expected_q_u8_5);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 32, 4, expected_q_u8_6);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
+
+ /* vreinterpretq_u16_xx. */
+ TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 16, 8, expected_q_u16_2);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 32, 4, expected_q_u16_3);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 64, 2, expected_q_u16_4);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 8, 16, expected_q_u16_5);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 32, 4, expected_q_u16_6);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
+
+ /* vreinterpretq_u32_xx. */
+ TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 16, 8, expected_q_u32_2);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 32, 4, expected_q_u32_3);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 64, 2, expected_q_u32_4);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 8, 16, expected_q_u32_5);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 16, 8, expected_q_u32_6);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
+
+ /* vreinterpretq_u64_xx. */
+ TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 16, 8, expected_q_u64_2);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 32, 4, expected_q_u64_3);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 64, 2, expected_q_u64_4);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 8, 16, expected_q_u64_5);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 16, 8, expected_q_u64_6);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
+
+ /* vreinterpret_f32_xx. */
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 16, 4, expected_f32_2);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 32, 2, expected_f32_3);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 64, 1, expected_f32_4);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 8, 8, expected_f32_5);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 16, 4, expected_f32_6);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 32, 2, expected_f32_7);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
+ TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
+
+ /* vreinterpretq_f32_xx. */
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 16, 8, expected_q_f32_2);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 32, 4, expected_q_f32_3);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 64, 2, expected_q_f32_4);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 8, 16, expected_q_f32_5);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 16, 8, expected_q_f32_6);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 32, 4, expected_q_f32_7);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
+ TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
+
+ /* vreinterpret_xx_f32. */
+ TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
+ TEST_VREINTERPRET(, int, s, 16, 4, float, f, 32, 2, expected_xx_f32_2);
+ TEST_VREINTERPRET(, int, s, 32, 2, float, f, 32, 2, expected_xx_f32_3);
+ TEST_VREINTERPRET(, int, s, 64, 1, float, f, 32, 2, expected_xx_f32_4);
+ TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 32, 2, expected_xx_f32_5);
+ TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 32, 2, expected_xx_f32_6);
+ TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 32, 2, expected_xx_f32_7);
+ TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
+ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
+ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
+
+ /* vreinterpretq_xx_f32. */
+ TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
+ TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 32, 4, expected_q_xx_f32_2);
+ TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 32, 4, expected_q_xx_f32_3);
+ TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 32, 4, expected_q_xx_f32_4);
+ TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 32, 4, expected_q_xx_f32_5);
+ TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 32, 4, expected_q_xx_f32_6);
+ TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 32, 4, expected_q_xx_f32_7);
+ TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
+ TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
+ TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
+}
+
+int main (void)
+{
+ exec_vreinterpret ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (4 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests Christophe Lyon
` (14 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c
new file mode 100644
index 0000000..a9eda22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c
@@ -0,0 +1,553 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf9, 0xfa, 0xfb, 0xfc,
+ 0xfd, 0xfe, 0xff, 0x0 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffd, 0xfffffffe };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffd, 0xfffe, 0xffff, 0x0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff4, 0xfffffff5 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf9, 0xfa, 0xfb, 0xfc,
+ 0xfd, 0xfe, 0xff, 0x0,
+ 0x1, 0x2, 0x3, 0x4,
+ 0x5, 0x6, 0x7, 0x8 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffd, 0xfffffffe,
+ 0xffffffff, 0x0 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0, 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc,
+ 0xd, 0xe, 0xf, 0x10,
+ 0x11, 0x12, 0x13, 0x14 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
+ 0x1, 0x2, 0x3, 0x4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff4, 0xfffffff5,
+ 0xfffffff6, 0xfffffff7 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+
+/* Expected results with max input and shift by 1. */
+VECT_VAR_DECL(expected_max_sh1,int,8,8) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh1,int,16,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh1,int,32,2) [] = { 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh1,int,64,1) [] = { 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh1,uint,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh1,uint,16,4) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh1,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh1,uint,64,1) [] = { 0x8000000000000000 };
+VECT_VAR_DECL(expected_max_sh1,int,8,16) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh1,int,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000,
+ 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh1,int,32,4) [] = { 0x40000000, 0x40000000,
+ 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh1,int,64,2) [] = { 0x4000000000000000,
+ 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh1,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh1,uint,16,8) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh1,uint,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh1,uint,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+/* Expected results with max input and shift by 3. */
+VECT_VAR_DECL(expected_max_sh3,int,8,8) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh3,int,16,4) [] = { 0x1000, 0x1000, 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh3,int,32,2) [] = { 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh3,int,64,1) [] = { 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh3,uint,8,8) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh3,uint,16,4) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh3,uint,32,2) [] = { 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh3,uint,64,1) [] = { 0x2000000000000000 };
+VECT_VAR_DECL(expected_max_sh3,int,8,16) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh3,int,16,8) [] = { 0x1000, 0x1000, 0x1000, 0x1000,
+ 0x1000, 0x1000, 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh3,int,32,4) [] = { 0x10000000, 0x10000000,
+ 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh3,int,64,2) [] = { 0x1000000000000000,
+ 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh3,uint,8,16) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh3,uint,16,8) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh3,uint,32,4) [] = { 0x20000000, 0x20000000,
+ 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh3,uint,64,2) [] = { 0x2000000000000000,
+ 0x2000000000000000 };
+
+/* Expected results with max input and shift by type width. */
+VECT_VAR_DECL(expected_max_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_max_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_shmax,uint,64,2) [] = { 0x1, 0x1 };
+
+/* Expected results with min negative input and shift by 1. */
+VECT_VAR_DECL(expected_min_sh1,int,8,8) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0 };
+VECT_VAR_DECL(expected_min_sh1,int,16,4) [] = { 0xc000, 0xc000, 0xc000, 0xc000 };
+VECT_VAR_DECL(expected_min_sh1,int,32,2) [] = { 0xc0000000, 0xc0000000 };
+VECT_VAR_DECL(expected_min_sh1,int,64,1) [] = { 0xc000000000000000 };
+VECT_VAR_DECL(expected_min_sh1,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_min_sh1,int,8,16) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0 };
+VECT_VAR_DECL(expected_min_sh1,int,16,8) [] = { 0xc000, 0xc000, 0xc000, 0xc000,
+ 0xc000, 0xc000, 0xc000, 0xc000 };
+VECT_VAR_DECL(expected_min_sh1,int,32,4) [] = { 0xc0000000, 0xc0000000,
+ 0xc0000000, 0xc0000000 };
+VECT_VAR_DECL(expected_min_sh1,int,64,2) [] = { 0xc000000000000000,
+ 0xc000000000000000 };
+VECT_VAR_DECL(expected_min_sh1,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh1,uint,64,2) [] = { 0x1, 0x1 };
+
+/* Expected results with min negative input and shift by 3. */
+VECT_VAR_DECL(expected_min_sh3,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected_min_sh3,int,16,4) [] = { 0xf000, 0xf000, 0xf000, 0xf000 };
+VECT_VAR_DECL(expected_min_sh3,int,32,2) [] = { 0xf0000000, 0xf0000000 };
+VECT_VAR_DECL(expected_min_sh3,int,64,1) [] = { 0xf000000000000000 };
+VECT_VAR_DECL(expected_min_sh3,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_min_sh3,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected_min_sh3,int,16,8) [] = { 0xf000, 0xf000, 0xf000, 0xf000,
+ 0xf000, 0xf000, 0xf000, 0xf000 };
+VECT_VAR_DECL(expected_min_sh3,int,32,4) [] = { 0xf0000000, 0xf0000000,
+ 0xf0000000, 0xf0000000 };
+VECT_VAR_DECL(expected_min_sh3,int,64,2) [] = { 0xf000000000000000,
+ 0xf000000000000000 };
+VECT_VAR_DECL(expected_min_sh3,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_sh3,uint,64,2) [] = { 0x1, 0x1 };
+
+/* Expected results with min negative input and shift by type width. */
+VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_min_shmax,uint,64,2) [] = { 0x1, 0x1 };
+
+#define TEST_MSG "VRSRA_N"
+void exec_vrsra_n (void)
+{
+ /* Basic test: y=vrsra_n(x,v), then store the result. */
+#define TEST_VRSRA_N(Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose arbitrary initialization values. */
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , int, s, 64, 1, 0x44);
+ VDUP(vector2, , uint, u, 8, 8, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x66);
+ VDUP(vector2, , uint, u, 32, 2, 0x77);
+ VDUP(vector2, , uint, u, 64, 1, 0x88);
+
+ VDUP(vector2, q, int, s, 8, 16, 0x11);
+ VDUP(vector2, q, int, s, 16, 8, 0x22);
+ VDUP(vector2, q, int, s, 32, 4, 0x33);
+ VDUP(vector2, q, int, s, 64, 2, 0x44);
+ VDUP(vector2, q, uint, u, 8, 16, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x66);
+ VDUP(vector2, q, uint, u, 32, 4, 0x77);
+ VDUP(vector2, q, uint, u, 64, 2, 0x88);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VRSRA_N(, int, s, 8, 8, 1);
+ TEST_VRSRA_N(, int, s, 16, 4, 12);
+ TEST_VRSRA_N(, int, s, 32, 2, 2);
+ TEST_VRSRA_N(, int, s, 64, 1, 32);
+ TEST_VRSRA_N(, uint, u, 8, 8, 2);
+ TEST_VRSRA_N(, uint, u, 16, 4, 3);
+ TEST_VRSRA_N(, uint, u, 32, 2, 5);
+ TEST_VRSRA_N(, uint, u, 64, 1, 33);
+
+ TEST_VRSRA_N(q, int, s, 8, 16, 1);
+ TEST_VRSRA_N(q, int, s, 16, 8, 12);
+ TEST_VRSRA_N(q, int, s, 32, 4, 2);
+ TEST_VRSRA_N(q, int, s, 64, 2, 32);
+ TEST_VRSRA_N(q, uint, u, 8, 16, 2);
+ TEST_VRSRA_N(q, uint, u, 16, 8, 3);
+ TEST_VRSRA_N(q, uint, u, 32, 4, 5);
+ TEST_VRSRA_N(q, uint, u, 64, 2, 33);
+
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+
+
+ /* Initialize the accumulator with 0. */
+ VDUP(vector, , int, s, 8, 8, 0);
+ VDUP(vector, , int, s, 16, 4, 0);
+ VDUP(vector, , int, s, 32, 2, 0);
+ VDUP(vector, , int, s, 64, 1, 0);
+ VDUP(vector, , uint, u, 8, 8, 0);
+ VDUP(vector, , uint, u, 16, 4, 0);
+ VDUP(vector, , uint, u, 32, 2, 0);
+ VDUP(vector, , uint, u, 64, 1, 0);
+ VDUP(vector, q, int, s, 8, 16, 0);
+ VDUP(vector, q, int, s, 16, 8, 0);
+ VDUP(vector, q, int, s, 32, 4, 0);
+ VDUP(vector, q, int, s, 64, 2, 0);
+ VDUP(vector, q, uint, u, 8, 16, 0);
+ VDUP(vector, q, uint, u, 16, 8, 0);
+ VDUP(vector, q, uint, u, 32, 4, 0);
+ VDUP(vector, q, uint, u, 64, 2, 0);
+
+ /* Initialize with max values to check overflow. */
+ VDUP(vector2, , int, s, 8, 8, 0x7F);
+ VDUP(vector2, , int, s, 16, 4, 0x7FFF);
+ VDUP(vector2, , int, s, 32, 2, 0x7FFFFFFF);
+ VDUP(vector2, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector2, , uint, u, 8, 8, 0xFF);
+ VDUP(vector2, , uint, u, 16, 4, 0xFFFF);
+ VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector2, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
+ VDUP(vector2, q, int, s, 8, 16, 0x7F);
+ VDUP(vector2, q, int, s, 16, 8, 0x7FFF);
+ VDUP(vector2, q, int, s, 32, 4, 0x7FFFFFFF);
+ VDUP(vector2, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector2, q, uint, u, 8, 16, 0xFF);
+ VDUP(vector2, q, uint, u, 16, 8, 0xFFFF);
+ VDUP(vector2, q, uint, u, 32, 4, 0xFFFFFFFF);
+ VDUP(vector2, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
+
+ /* Shift by 1 to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 1);
+ TEST_VRSRA_N(, int, s, 16, 4, 1);
+ TEST_VRSRA_N(, int, s, 32, 2, 1);
+ TEST_VRSRA_N(, int, s, 64, 1, 1);
+ TEST_VRSRA_N(, uint, u, 8, 8, 1);
+ TEST_VRSRA_N(, uint, u, 16, 4, 1);
+ TEST_VRSRA_N(, uint, u, 32, 2, 1);
+ TEST_VRSRA_N(, uint, u, 64, 1, 1);
+ TEST_VRSRA_N(q, int, s, 8, 16, 1);
+ TEST_VRSRA_N(q, int, s, 16, 8, 1);
+ TEST_VRSRA_N(q, int, s, 32, 4, 1);
+ TEST_VRSRA_N(q, int, s, 64, 2, 1);
+ TEST_VRSRA_N(q, uint, u, 8, 16, 1);
+ TEST_VRSRA_N(q, uint, u, 16, 8, 1);
+ TEST_VRSRA_N(q, uint, u, 32, 4, 1);
+ TEST_VRSRA_N(q, uint, u, 64, 2, 1);
+
+#undef CMT
+#define CMT " (checking overflow: shift by 1, max input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh1, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh1, CMT);
+
+
+ /* Shift by 3 to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 3);
+ TEST_VRSRA_N(, int, s, 16, 4, 3);
+ TEST_VRSRA_N(, int, s, 32, 2, 3);
+ TEST_VRSRA_N(, int, s, 64, 1, 3);
+ TEST_VRSRA_N(, uint, u, 8, 8, 3);
+ TEST_VRSRA_N(, uint, u, 16, 4, 3);
+ TEST_VRSRA_N(, uint, u, 32, 2, 3);
+ TEST_VRSRA_N(, uint, u, 64, 1, 3);
+ TEST_VRSRA_N(q, int, s, 8, 16, 3);
+ TEST_VRSRA_N(q, int, s, 16, 8, 3);
+ TEST_VRSRA_N(q, int, s, 32, 4, 3);
+ TEST_VRSRA_N(q, int, s, 64, 2, 3);
+ TEST_VRSRA_N(q, uint, u, 8, 16, 3);
+ TEST_VRSRA_N(q, uint, u, 16, 8, 3);
+ TEST_VRSRA_N(q, uint, u, 32, 4, 3);
+ TEST_VRSRA_N(q, uint, u, 64, 2, 3);
+
+#undef CMT
+#define CMT " (checking overflow: shift by 3, max input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh3, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh3, CMT);
+
+
+ /* Shift by max to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 8);
+ TEST_VRSRA_N(, int, s, 16, 4, 16);
+ TEST_VRSRA_N(, int, s, 32, 2, 32);
+ TEST_VRSRA_N(, int, s, 64, 1, 64);
+ TEST_VRSRA_N(, uint, u, 8, 8, 8);
+ TEST_VRSRA_N(, uint, u, 16, 4, 16);
+ TEST_VRSRA_N(, uint, u, 32, 2, 32);
+ TEST_VRSRA_N(, uint, u, 64, 1, 64);
+ TEST_VRSRA_N(q, int, s, 8, 16, 8);
+ TEST_VRSRA_N(q, int, s, 16, 8, 16);
+ TEST_VRSRA_N(q, int, s, 32, 4, 32);
+ TEST_VRSRA_N(q, int, s, 64, 2, 64);
+ TEST_VRSRA_N(q, uint, u, 8, 16, 8);
+ TEST_VRSRA_N(q, uint, u, 16, 8, 16);
+ TEST_VRSRA_N(q, uint, u, 32, 4, 32);
+ TEST_VRSRA_N(q, uint, u, 64, 2, 64);
+
+#undef CMT
+#define CMT " (checking overflow: shift by max, max input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shmax, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shmax, CMT);
+
+
+ /* Initialize with min values to check overflow. */
+ VDUP(vector2, , int, s, 8, 8, 0x80);
+ VDUP(vector2, , int, s, 16, 4, 0x8000);
+ VDUP(vector2, , int, s, 32, 2, 0x80000000);
+ VDUP(vector2, , int, s, 64, 1, 0x8000000000000000LL);
+ VDUP(vector2, q, int, s, 8, 16, 0x80);
+ VDUP(vector2, q, int, s, 16, 8, 0x8000);
+ VDUP(vector2, q, int, s, 32, 4, 0x80000000);
+ VDUP(vector2, q, int, s, 64, 2, 0x8000000000000000ULL);
+
+ /* Shift by 1 to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 1);
+ TEST_VRSRA_N(, int, s, 16, 4, 1);
+ TEST_VRSRA_N(, int, s, 32, 2, 1);
+ TEST_VRSRA_N(, int, s, 64, 1, 1);
+ TEST_VRSRA_N(q, int, s, 8, 16, 1);
+ TEST_VRSRA_N(q, int, s, 16, 8, 1);
+ TEST_VRSRA_N(q, int, s, 32, 4, 1);
+ TEST_VRSRA_N(q, int, s, 64, 2, 1);
+
+#undef CMT
+#define CMT " (checking overflow: shift by 1, min negative input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_sh1, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_sh1, CMT);
+
+
+ /* Shift by 3 to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 3);
+ TEST_VRSRA_N(, int, s, 16, 4, 3);
+ TEST_VRSRA_N(, int, s, 32, 2, 3);
+ TEST_VRSRA_N(, int, s, 64, 1, 3);
+ TEST_VRSRA_N(q, int, s, 8, 16, 3);
+ TEST_VRSRA_N(q, int, s, 16, 8, 3);
+ TEST_VRSRA_N(q, int, s, 32, 4, 3);
+ TEST_VRSRA_N(q, int, s, 64, 2, 3);
+
+#undef CMT
+#define CMT " (checking overflow: shift by 3, min negative input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_sh3, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_sh3, CMT);
+
+
+ /* Shift by max to check overflow with rounding constant. */
+ TEST_VRSRA_N(, int, s, 8, 8, 8);
+ TEST_VRSRA_N(, int, s, 16, 4, 16);
+ TEST_VRSRA_N(, int, s, 32, 2, 32);
+ TEST_VRSRA_N(, int, s, 64, 1, 64);
+ TEST_VRSRA_N(q, int, s, 8, 16, 8);
+ TEST_VRSRA_N(q, int, s, 16, 8, 16);
+ TEST_VRSRA_N(q, int, s, 32, 4, 32);
+ TEST_VRSRA_N(q, int, s, 64, 2, 64);
+
+#undef CMT
+#define CMT " (checking overflow: shift by max, min negative input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_min_shmax, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_min_shmax, CMT);
+}
+
+int main (void)
+{
+ exec_vrsra_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (3 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests Christophe Lyon
` (15 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c
new file mode 100644
index 0000000..6d2f4dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c
@@ -0,0 +1,70 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
+ 0xfa, 0xfa, 0xfb, 0xfb };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff8, 0xfff9, 0xfff9 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfc, 0xfc, 0xfc, 0xfc,
+ 0xfd, 0xfd, 0xfd, 0xfd };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffffe, 0xfffffffe };
+
+#define TEST_MSG "VSHRN_N"
+void exec_vshrn_n (void)
+{
+ /* Basic test: y=vshrn_n(x,v), then store the result. */
+#define TEST_VSHRN_N(T1, T2, W, W2, N, V) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ vshrn_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+ /* vector is twice as large as vector_res. */
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSHRN_N(int, s, 16, 8, 8, 1);
+ TEST_VSHRN_N(int, s, 32, 16, 4, 1);
+ TEST_VSHRN_N(int, s, 64, 32, 2, 2);
+ TEST_VSHRN_N(uint, u, 16, 8, 8, 2);
+ TEST_VSHRN_N(uint, u, 32, 16, 4, 3);
+ TEST_VSHRN_N(uint, u, 64, 32, 2, 3);
+
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+}
+
+int main (void)
+{
+ exec_vshrn_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (14 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:26 ` [Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests Christophe Lyon
` (4 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c
new file mode 100644
index 0000000..122ce41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c
@@ -0,0 +1,95 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
+ 0xfa, 0xfa, 0xfb, 0xfb };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffff };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x3c, 0x3c, 0x3c, 0x3c,
+ 0x3d, 0x3d, 0x3d, 0x3d };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1ffe, 0x1ffe, 0x1ffe, 0x1ffe };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x7ffffff, 0x7ffffff };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x7fffffff };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf8, 0xf8, 0xf9, 0xf9,
+ 0xfa, 0xfa, 0xfb, 0xfb,
+ 0xfc, 0xfc, 0xfd, 0xfd,
+ 0xfe, 0xfe, 0xff, 0xff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffc, 0xfffffffc,
+ 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffff, 0xffffffffffffffff };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x3c, 0x3c, 0x3c, 0x3c,
+ 0x3d, 0x3d, 0x3d, 0x3d,
+ 0x3e, 0x3e, 0x3e, 0x3e,
+ 0x3f, 0x3f, 0x3f, 0x3f };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1ffe, 0x1ffe, 0x1ffe, 0x1ffe,
+ 0x1ffe, 0x1ffe, 0x1ffe, 0x1ffe };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x7ffffff, 0x7ffffff,
+ 0x7ffffff, 0x7ffffff };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x7fffffff, 0x7fffffff };
+
+#define TEST_MSG "VSHR_N"
+void exec_vshr_n (void)
+{
+ /* Basic test: y=vshr_n(x,v), then store the result. */
+#define TEST_VSHR_N(Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vshr##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSHR_N(, int, s, 8, 8, 1);
+ TEST_VSHR_N(, int, s, 16, 4, 12);
+ TEST_VSHR_N(, int, s, 32, 2, 2);
+ TEST_VSHR_N(, int, s, 64, 1, 32);
+ TEST_VSHR_N(, uint, u, 8, 8, 2);
+ TEST_VSHR_N(, uint, u, 16, 4, 3);
+ TEST_VSHR_N(, uint, u, 32, 2, 5);
+ TEST_VSHR_N(, uint, u, 64, 1, 33);
+
+ TEST_VSHR_N(q, int, s, 8, 16, 1);
+ TEST_VSHR_N(q, int, s, 16, 8, 12);
+ TEST_VSHR_N(q, int, s, 32, 4, 2);
+ TEST_VSHR_N(q, int, s, 64, 2, 32);
+ TEST_VSHR_N(q, uint, u, 8, 16, 2);
+ TEST_VSHR_N(q, uint, u, 16, 8, 3);
+ TEST_VSHR_N(q, uint, u, 32, 4, 5);
+ TEST_VSHR_N(q, uint, u, 64, 2, 33);
+
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+}
+
+int main (void)
+{
+ exec_vshr_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (8 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests Christophe Lyon
` (10 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
new file mode 100644
index 0000000..0291ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
@@ -0,0 +1,157 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+#include <math.h>
+
+/* Expected results. */
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x9c800000, 0x9c800000,
+ 0x9c800000, 0x9c800000 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x3e498000, 0x3e498000 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x3e700000, 0x3e700000,
+ 0x3e700000, 0x3e700000 };
+
+/* Expected results with large uint #1. */
+VECT_VAR_DECL(expected_1,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_1,uint,32,4) [] = { 0xae800000, 0xae800000,
+ 0xae800000, 0xae800000 };
+
+/* Expected results with large uint #2. */
+VECT_VAR_DECL(expected_2,uint,32,2) [] = { 0xb4800000, 0xb4800000 };
+VECT_VAR_DECL(expected_2,uint,32,4) [] = { 0xed000000, 0xed000000,
+ 0xed000000, 0xed000000 };
+
+/* Expected results with FP special inputs values (NaNs, ...). */
+VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
+ 0x7f800000, 0x7f800000 };
+
+/* Expected results with FP special inputs values
+ (negative, infinity). */
+VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results with FP special inputs values
+ (-0, -infinity). */
+VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+
+#define TEST_MSG "VRSQRTE/VRSQRTEQ"
+void exec_vrsqrte(void)
+{
+ int i;
+
+ /* Basic test: y=vrsqrte(x), then store the result. */
+#define TEST_VRSQRTE(Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrsqrte##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 2);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, float, 32, 4);
+
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, float, 32, 4);
+
+ clean_results ();
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector, , uint, u, 32, 2, 0x12345678);
+ VDUP(vector, , float, f, 32, 2, 25.799999f);
+ VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
+ VDUP(vector, q, float, f, 32, 4, 18.2f);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, uint, u, 32, 2);
+ TEST_VRSQRTE(, float, f, 32, 2);
+ TEST_VRSQRTE(q, uint, u, 32, 4);
+ TEST_VRSQRTE(q, float, f, 32, 4);
+
+#define CMT ""
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+
+
+ /* Don't test FP variants with negative inputs. */
+ /* Use input with various values of bits 30 and 31. */
+ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector, q, uint, u, 32, 4, 0x89081234);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, uint, u, 32, 2);
+ TEST_VRSQRTE(q, uint, u, 32, 4);
+
+#undef CMT
+#define CMT " (large uint #1)"
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_1, CMT);
+
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector, , uint, u, 32, 2, 0x80000000);
+ VDUP(vector, q, uint, u, 32, 4, 0x4ABCDEF0);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, uint, u, 32, 2);
+ TEST_VRSQRTE(q, uint, u, 32, 4);
+
+#undef CMT
+#define CMT " (large uint #2)"
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_2, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_2, CMT);
+
+
+ /* Test FP variants with special input values (NaNs, ...). */
+ VDUP(vector, , float, f, 32, 2, NAN);
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, float, f, 32, 2);
+ TEST_VRSQRTE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (NaN, 0)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+
+
+ /* Test FP variants with special input values (negative, infinity). */
+ VDUP(vector, , float, f, 32, 2, -1.0f);
+ VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, float, f, 32, 2);
+ TEST_VRSQRTE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (negative, infinity)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+
+ /* Test FP variants with special input values (-0, -infinity). */
+ VDUP(vector, , float, f, 32, 2, -0.0f);
+ VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+
+ /* Apply the operator. */
+ TEST_VRSQRTE(, float, f, 32, 2);
+ TEST_VRSQRTE(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (-0, -infinity)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+}
+
+int main (void)
+{
+ exec_vrsqrte ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (2 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests Christophe Lyon
` (16 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
new file mode 100644
index 0000000..5159406
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
@@ -0,0 +1,99 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0x11 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x22 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x44 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0x55, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x88 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0x55, 0xf7 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0xfff3 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x4204cccd };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0x99 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xaa, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xbb };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0, 0xcc };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xdd, 0xff };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xee, 0xfff7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xff, 0xfffffff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0, 0x11 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xdd, 0xff };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xee, 0xfff7 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0x41333333 };
+
+#define TEST_MSG "VSET_LANE/VSET_LANEQ"
+void exec_vset_lane (void)
+{
+ /* vec=vset_lane(val, vec, lane), then store the result. */
+#define TEST_VSET_LANE(Q, T1, T2, W, N, V, L) \
+ VECT_VAR(vector, T1, W, N) = \
+ vset##Q##_lane_##T2##W(V, \
+ VECT_VAR(vector, T1, W, N), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ /* Choose value and lane arbitrarily. */
+ TEST_VSET_LANE(, int, s, 8, 8, 0x11, 7);
+ TEST_VSET_LANE(, int, s, 16, 4, 0x22, 3);
+ TEST_VSET_LANE(, int, s, 32, 2, 0x33, 1);
+ TEST_VSET_LANE(, int, s, 64, 1, 0x44, 0);
+ TEST_VSET_LANE(, uint, u, 8, 8, 0x55, 6);
+ TEST_VSET_LANE(, uint, u, 16, 4, 0x66, 2);
+ TEST_VSET_LANE(, uint, u, 32, 2, 0x77, 1);
+ TEST_VSET_LANE(, uint, u, 64, 1, 0x88, 0);
+ TEST_VSET_LANE(, poly, p, 8, 8, 0x55, 6);
+ TEST_VSET_LANE(, poly, p, 16, 4, 0x66, 2);
+ TEST_VSET_LANE(, float, f, 32, 2, 33.2f, 1);
+
+ TEST_VSET_LANE(q, int, s, 8, 16, 0x99, 15);
+ TEST_VSET_LANE(q, int, s, 16, 8, 0xAA, 5);
+ TEST_VSET_LANE(q, int, s, 32, 4, 0xBB, 3);
+ TEST_VSET_LANE(q, int, s, 64, 2, 0xCC, 1);
+ TEST_VSET_LANE(q, uint, u, 8, 16, 0xDD, 14);
+ TEST_VSET_LANE(q, uint, u, 16, 8, 0xEE, 6);
+ TEST_VSET_LANE(q, uint, u, 32, 4, 0xFF, 2);
+ TEST_VSET_LANE(q, uint, u, 64, 2, 0x11, 1);
+ TEST_VSET_LANE(q, poly, p, 8, 16, 0xDD, 14);
+ TEST_VSET_LANE(q, poly, p, 16, 8, 0xEE, 6);
+ TEST_VSET_LANE(q, float, f, 32, 4, 11.2f, 3);
+
+ CHECK_RESULTS(TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vset_lane ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-05-27 20:16 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests Christophe Lyon
` (18 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
new file mode 100644
index 0000000..26644ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
@@ -0,0 +1,578 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results for vst2, chunk 0. */
+VECT_VAR_DECL(expected_st2_0,int,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st2_0,uint,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st2_0,poly,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_st2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0x0, 0x0 };
+
+/* Expected results for vst2, chunk 1. */
+VECT_VAR_DECL(expected_st2_1,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,hfloat,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st2_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results for vst3, chunk 0. */
+VECT_VAR_DECL(expected_st3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st3_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_st3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0x0 };
+VECT_VAR_DECL(expected_st3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0x0 };
+
+/* Expected results for vst3, chunk 1. */
+VECT_VAR_DECL(expected_st3_1,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,int,32,2) [] = { 0xfffffff2, 0x0 };
+VECT_VAR_DECL(expected_st3_1,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,uint,32,2) [] = { 0xfffffff2, 0x0 };
+VECT_VAR_DECL(expected_st3_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,hfloat,32,2) [] = { 0xc1600000, 0x0 };
+VECT_VAR_DECL(expected_st3_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results for vst3, chunk 2. */
+VECT_VAR_DECL(expected_st3_2,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,hfloat,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st3_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results for vst4, chunk 0. */
+VECT_VAR_DECL(expected_st4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_st4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st4_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_st4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_st4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_st4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_st4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_st4_0,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_st4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0xc1500000 };
+
+/* Expected results for vst4, chunk 1. */
+VECT_VAR_DECL(expected_st4_1,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_st4_1,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_st4_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
+VECT_VAR_DECL(expected_st4_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results for vst4, chunk 2. */
+VECT_VAR_DECL(expected_st4_2,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Expected results for vst4, chunk 3. */
+VECT_VAR_DECL(expected_st4_3,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,hfloat,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_st4_3,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+/* Declare additional input buffers as needed. */
+/* Input buffers for vld2_lane. */
+VECT_VAR_DECL_INIT(buffer_vld2_lane, int, 8, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, int, 16, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, int, 32, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, int, 64, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 8, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 16, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2);
+VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2);
+
+/* Input buffers for vld3_lane. */
+VECT_VAR_DECL_INIT(buffer_vld3_lane, int, 8, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, int, 16, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, int, 32, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, int, 64, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 8, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 16, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3);
+VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3);
+
+/* Input buffers for vld4_lane. */
+VECT_VAR_DECL_INIT(buffer_vld4_lane, int, 8, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, int, 16, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, int, 32, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, int, 64, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 8, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 16, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4);
+VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4);
+
+void exec_vstX_lane (void)
+{
+ /* In this case, input variables are arrays of vectors. */
+#define DECL_VSTX_LANE(T1, W, N, X) \
+ VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
+ VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X); \
+ VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
+
+ /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result. */
+ /* We also use another extra input buffer (buffer_src), which we
+ fill with 0xAA, and which it used to load a vector from which we
+ read a given lane. */
+#define TEST_VSTX_LANE(Q, T1, T2, W, N, X, L) \
+ memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, \
+ sizeof(VECT_VAR(buffer_src, T1, W, N))); \
+ memset (VECT_VAR(result_bis_##X, T1, W, N), 0, \
+ sizeof(VECT_VAR(result_bis_##X, T1, W, N))); \
+ \
+ VECT_ARRAY_VAR(vector_src, T1, W, N, X) = \
+ vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N)); \
+ \
+ VECT_ARRAY_VAR(vector, T1, W, N, X) = \
+ /* Use dedicated init buffer, of size X. */ \
+ vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X), \
+ VECT_ARRAY_VAR(vector_src, T1, W, N, X), \
+ L); \
+ vst##X##Q##_lane_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
+ VECT_ARRAY_VAR(vector, T1, W, N, X), \
+ L); \
+ memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ /* Overwrite "result" with the contents of "result_bis"[Y]. */
+#define TEST_EXTRA_CHUNK(T1, W, N, X, Y) \
+ memcpy(VECT_VAR(result, T1, W, N), \
+ &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ /* We need all variants in 64 bits, but there is no 64x2 variant,
+ nor 128 bits vectors of int8/uint8/poly8. */
+#define DECL_ALL_VSTX_LANE(X) \
+ DECL_VSTX_LANE(int, 8, 8, X); \
+ DECL_VSTX_LANE(int, 16, 4, X); \
+ DECL_VSTX_LANE(int, 32, 2, X); \
+ DECL_VSTX_LANE(uint, 8, 8, X); \
+ DECL_VSTX_LANE(uint, 16, 4, X); \
+ DECL_VSTX_LANE(uint, 32, 2, X); \
+ DECL_VSTX_LANE(poly, 8, 8, X); \
+ DECL_VSTX_LANE(poly, 16, 4, X); \
+ DECL_VSTX_LANE(float, 32, 2, X); \
+ DECL_VSTX_LANE(int, 16, 8, X); \
+ DECL_VSTX_LANE(int, 32, 4, X); \
+ DECL_VSTX_LANE(uint, 16, 8, X); \
+ DECL_VSTX_LANE(uint, 32, 4, X); \
+ DECL_VSTX_LANE(poly, 16, 8, X); \
+ DECL_VSTX_LANE(float, 32, 4, X)
+
+#define DUMMY_ARRAY(V, T, W, N, L) VECT_VAR_DECL(V,T,W,N)[N*L]
+
+ /* Use the same lanes regardless of the size of the array (X), for
+ simplicity. */
+#define TEST_ALL_VSTX_LANE(X) \
+ TEST_VSTX_LANE(, int, s, 8, 8, X, 7); \
+ TEST_VSTX_LANE(, int, s, 16, 4, X, 2); \
+ TEST_VSTX_LANE(, int, s, 32, 2, X, 0); \
+ TEST_VSTX_LANE(, float, f, 32, 2, X, 0); \
+ TEST_VSTX_LANE(, uint, u, 8, 8, X, 4); \
+ TEST_VSTX_LANE(, uint, u, 16, 4, X, 3); \
+ TEST_VSTX_LANE(, uint, u, 32, 2, X, 1); \
+ TEST_VSTX_LANE(, poly, p, 8, 8, X, 4); \
+ TEST_VSTX_LANE(, poly, p, 16, 4, X, 3); \
+ TEST_VSTX_LANE(q, int, s, 16, 8, X, 6); \
+ TEST_VSTX_LANE(q, int, s, 32, 4, X, 2); \
+ TEST_VSTX_LANE(q, uint, u, 16, 8, X, 5); \
+ TEST_VSTX_LANE(q, uint, u, 32, 4, X, 0); \
+ TEST_VSTX_LANE(q, poly, p, 16, 8, X, 5); \
+ TEST_VSTX_LANE(q, float, f, 32, 4, X, 2)
+
+#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
+ TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
+ TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(float, 32, 2, X, Y); \
+ TEST_EXTRA_CHUNK(int, 16, 8, X, Y); \
+ TEST_EXTRA_CHUNK(int, 32, 4, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 16, 8, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 32, 4, X, Y); \
+ TEST_EXTRA_CHUNK(poly, 16, 8, X, Y); \
+ TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
+
+ /* Declare the temporary buffers / variables. */
+ DECL_ALL_VSTX_LANE(2);
+ DECL_ALL_VSTX_LANE(3);
+ DECL_ALL_VSTX_LANE(4);
+
+ /* Define dummy input arrays, large enough for x4 vectors. */
+ DUMMY_ARRAY(buffer_src, int, 8, 8, 4);
+ DUMMY_ARRAY(buffer_src, int, 16, 4, 4);
+ DUMMY_ARRAY(buffer_src, int, 32, 2, 4);
+ DUMMY_ARRAY(buffer_src, uint, 8, 8, 4);
+ DUMMY_ARRAY(buffer_src, uint, 16, 4, 4);
+ DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
+ DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
+ DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
+ DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
+ DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
+ DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
+ DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
+ DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
+ DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
+ DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
+
+ /* Check vst2_lane/vst2q_lane. */
+ clean_results ();
+#define TEST_MSG "VST2_LANE/VST2Q_LANE"
+ TEST_ALL_VSTX_LANE(2);
+
+#define CMT " (chunk 0)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st2_0, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st2_0, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st2_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_0, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_0, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_0, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_0, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(2, 1);
+#undef CMT
+#define CMT " chunk 1"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st2_1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st2_1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st2_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_1, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_1, CMT);
+
+
+ /* Check vst3_lane/vst3q_lane. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VST3_LANE/VST3Q_LANE"
+ TEST_ALL_VSTX_LANE(3);
+
+#undef CMT
+#define CMT " (chunk 0)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st3_0, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st3_0, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st3_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_0, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_0, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_0, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_0, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(3, 1);
+
+#undef CMT
+#define CMT " (chunk 1)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st3_1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st3_1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st3_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_1, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_1, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(3, 2);
+
+#undef CMT
+#define CMT " (chunk 2)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st3_2, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st3_2, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st3_2, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_2, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_2, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_2, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_2, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_2, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_2, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_2, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_2, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_2, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_2, CMT);
+
+
+ /* Check vst4_lane/vst4q_lane. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VST4_LANE/VST4Q_LANE"
+ TEST_ALL_VSTX_LANE(4);
+
+#undef CMT
+#define CMT " (chunk 0)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_0, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_0, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_0, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_0, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_0, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_0, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_0, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_0, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_0, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_0, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(4, 1);
+
+#undef CMT
+#define CMT " (chunk 1)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_1, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_1, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_1, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(4, 2);
+
+#undef CMT
+#define CMT " (chunk 2)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_2, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_2, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_2, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_2, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_2, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_2, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_2, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_2, CMT);
+
+ TEST_ALL_EXTRA_CHUNKS(4, 3);
+
+#undef CMT
+#define CMT " (chunk 3)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_st4_3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_st4_3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_st4_3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_3, CMT);
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_3, CMT);
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_3, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_3, CMT);
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_3, CMT);
+}
+
+int main (void)
+{
+ exec_vstX_lane ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (6 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests Christophe Lyon
` (12 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
new file mode 100644
index 0000000..4531026
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
@@ -0,0 +1,118 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+#include <math.h>
+
+/* Expected results. */
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2796b84, 0xc2796b84 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc0e4a3d8, 0xc0e4a3d8,
+ 0xc0e4a3d8, 0xc0e4a3d8 };
+
+/* Expected results with input=NaN. */
+VECT_VAR_DECL(expected_nan,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+
+/* Expected results with FP special inputs values (infinity, 0). */
+VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 0x3fc00000, 0x3fc00000 };
+
+/* Expected results with only FP special inputs values (infinity,
+ 0). */
+VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x3fc00000, 0x3fc00000 };
+VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 0x3fc00000, 0x3fc00000 };
+
+#define TEST_MSG "VRSQRTS/VRSQRTSQ"
+void exec_vrsqrts(void)
+{
+ int i;
+
+ /* Basic test: y=vrsqrts(x), then store the result. */
+#define TEST_VRSQRTS(Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrsqrts##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ /* No need for integer variants. */
+ DECL_VARIABLE(vector, float, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 4);
+
+ DECL_VARIABLE(vector2, float, 32, 2);
+ DECL_VARIABLE(vector2, float, 32, 4);
+
+ DECL_VARIABLE(vector_res, float, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 4);
+
+ clean_results ();
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector, , float, f, 32, 2, 12.9f);
+ VDUP(vector, q, float, f, 32, 4, 9.1f);
+
+ VDUP(vector2, , float, f, 32, 2, 9.9f);
+ VDUP(vector2, q, float, f, 32, 4, 1.9f);
+
+ /* Apply the operator. */
+ TEST_VRSQRTS(, float, f, 32, 2);
+ TEST_VRSQRTS(q, float, f, 32, 4);
+
+#define CMT ""
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+
+
+ /* Test FP variants with special input values (NaN). */
+ VDUP(vector, , float, f, 32, 2, NAN);
+ VDUP(vector2, q, float, f, 32, 4, NAN);
+
+ /* Apply the operator. */
+ TEST_VRSQRTS(, float, f, 32, 2);
+ TEST_VRSQRTS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (NAN) and normal values"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_nan, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, CMT);
+
+
+ /* Test FP variants with special input values (infinity, 0). */
+ VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ /* Restore a normal value in vector2. */
+ VDUP(vector2, q, float, f, 32, 4, 3.2f);
+
+ /* Apply the operator. */
+ TEST_VRSQRTS(, float, f, 32, 2);
+ TEST_VRSQRTS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " FP special (infinity, 0) and normal values"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+
+
+ /* Test FP variants with only special input values (infinity, 0). */
+ VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ VDUP(vector2, , float, f, 32, 2, -0.0f);
+ VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+
+ /* Apply the operator. */
+ TEST_VRSQRTS(, float, f, 32, 2);
+ TEST_VRSQRTS(q, float, f, 32, 4);
+
+#undef CMT
+#define CMT " only FP special (infinity, 0)"
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+}
+
+int main (void)
+{
+ exec_vrsqrts ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-05-27 20:16 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests Christophe Lyon
@ 2015-05-27 20:17 ` Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests Christophe Lyon
` (17 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:17 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
new file mode 100644
index 0000000..0557efd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
@@ -0,0 +1,289 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results for vtbl1. */
+VECT_VAR_DECL(expected_vtbl1,int,8,8) [] = { 0x0, 0xf2, 0xf2, 0xf2,
+ 0x0, 0x0, 0xf2, 0xf2 };
+VECT_VAR_DECL(expected_vtbl1,uint,8,8) [] = { 0x0, 0xf3, 0xf3, 0xf3,
+ 0x0, 0x0, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected_vtbl1,poly,8,8) [] = { 0x0, 0xf3, 0xf3, 0xf3,
+ 0x0, 0x0, 0xf3, 0xf3 };
+
+/* Expected results for vtbl2. */
+VECT_VAR_DECL(expected_vtbl2,int,8,8) [] = { 0xf6, 0xf3, 0xf3, 0xf3,
+ 0x0, 0x0, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected_vtbl2,uint,8,8) [] = { 0xf6, 0xf5, 0xf5, 0xf5,
+ 0x0, 0x0, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected_vtbl2,poly,8,8) [] = { 0xf6, 0xf5, 0xf5, 0xf5,
+ 0x0, 0x0, 0xf5, 0xf5 };
+
+/* Expected results for vtbl3. */
+VECT_VAR_DECL(expected_vtbl3,int,8,8) [] = { 0xf8, 0xf4, 0xf4, 0xf4,
+ 0xff, 0x0, 0xf4, 0xf4 };
+VECT_VAR_DECL(expected_vtbl3,uint,8,8) [] = { 0xf8, 0xf7, 0xf7, 0xf7,
+ 0xff, 0x0, 0xf7, 0xf7 };
+VECT_VAR_DECL(expected_vtbl3,poly,8,8) [] = { 0xf8, 0xf7, 0xf7, 0xf7,
+ 0xff, 0x0, 0xf7, 0xf7 };
+
+/* Expected results for vtbl4. */
+VECT_VAR_DECL(expected_vtbl4,int,8,8) [] = { 0xfa, 0xf5, 0xf5, 0xf5,
+ 0x3, 0x0, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected_vtbl4,uint,8,8) [] = { 0xfa, 0xf9, 0xf9, 0xf9,
+ 0x3, 0x0, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected_vtbl4,poly,8,8) [] = { 0xfa, 0xf9, 0xf9, 0xf9,
+ 0x3, 0x0, 0xf9, 0xf9 };
+
+/* Expected results for vtbx1. */
+VECT_VAR_DECL(expected_vtbx1,int,8,8) [] = { 0x33, 0xf2, 0xf2, 0xf2,
+ 0x33, 0x33, 0xf2, 0xf2 };
+VECT_VAR_DECL(expected_vtbx1,uint,8,8) [] = { 0xcc, 0xf3, 0xf3, 0xf3,
+ 0xcc, 0xcc, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected_vtbx1,poly,8,8) [] = { 0xcc, 0xf3, 0xf3, 0xf3,
+ 0xcc, 0xcc, 0xf3, 0xf3 };
+
+/* Expected results for vtbx2. */
+VECT_VAR_DECL(expected_vtbx2,int,8,8) [] = { 0xf6, 0xf3, 0xf3, 0xf3,
+ 0x33, 0x33, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected_vtbx2,uint,8,8) [] = { 0xf6, 0xf5, 0xf5, 0xf5,
+ 0xcc, 0xcc, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected_vtbx2,poly,8,8) [] = { 0xf6, 0xf5, 0xf5, 0xf5,
+ 0xcc, 0xcc, 0xf5, 0xf5 };
+
+/* Expected results for vtbx3. */
+VECT_VAR_DECL(expected_vtbx3,int,8,8) [] = { 0xf8, 0xf4, 0xf4, 0xf4,
+ 0xff, 0x33, 0xf4, 0xf4 };
+VECT_VAR_DECL(expected_vtbx3,uint,8,8) [] = { 0xf8, 0xf7, 0xf7, 0xf7,
+ 0xff, 0xcc, 0xf7, 0xf7 };
+VECT_VAR_DECL(expected_vtbx3,poly,8,8) [] = { 0xf8, 0xf7, 0xf7, 0xf7,
+ 0xff, 0xcc, 0xf7, 0xf7 };
+
+/* Expected results for vtbx4. */
+VECT_VAR_DECL(expected_vtbx4,int,8,8) [] = { 0xfa, 0xf5, 0xf5, 0xf5,
+ 0x3, 0x33, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected_vtbx4,uint,8,8) [] = { 0xfa, 0xf9, 0xf9, 0xf9,
+ 0x3, 0xcc, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected_vtbx4,poly,8,8) [] = { 0xfa, 0xf9, 0xf9, 0xf9,
+ 0x3, 0xcc, 0xf9, 0xf9 };
+
+void exec_vtbX (void)
+{
+ int i;
+
+ /* In this case, input variables are arrays of vectors. */
+#define DECL_VTBX(T1, W, N, X) \
+ VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(table_vector, T1, W, N, X)
+
+ /* The vtbl1 variant is different from vtbl{2,3,4} because it takes a
+ vector as 1st param, instead of an array of vectors. */
+#define TEST_VTBL1(T1, T2, T3, W, N) \
+ VECT_VAR(table_vector, T1, W, N) = \
+ vld1##_##T2##W((T1##W##_t *)lookup_table); \
+ \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vtbl1_##T2##W(VECT_VAR(table_vector, T1, W, N), \
+ VECT_VAR(vector, T3, W, N)); \
+ vst1_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N));
+
+#define TEST_VTBLX(T1, T2, T3, W, N, X) \
+ VECT_ARRAY_VAR(table_vector, T1, W, N, X) = \
+ vld##X##_##T2##W((T1##W##_t *)lookup_table); \
+ \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vtbl##X##_##T2##W(VECT_ARRAY_VAR(table_vector, T1, W, N, X), \
+ VECT_VAR(vector, T3, W, N)); \
+ vst1_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N));
+
+ /* We need to define a lookup table. */
+ uint8_t lookup_table[32];
+
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, poly, 8, 8);
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, poly, 8, 8);
+
+ /* For vtbl1. */
+ DECL_VARIABLE(table_vector, int, 8, 8);
+ DECL_VARIABLE(table_vector, uint, 8, 8);
+ DECL_VARIABLE(table_vector, poly, 8, 8);
+
+ /* For vtbx*. */
+ DECL_VARIABLE(default_vector, int, 8, 8);
+ DECL_VARIABLE(default_vector, uint, 8, 8);
+ DECL_VARIABLE(default_vector, poly, 8, 8);
+
+ /* We need only 8 bits variants. */
+#define DECL_ALL_VTBLX(X) \
+ DECL_VTBX(int, 8, 8, X); \
+ DECL_VTBX(uint, 8, 8, X); \
+ DECL_VTBX(poly, 8, 8, X)
+
+#define TEST_ALL_VTBL1() \
+ TEST_VTBL1(int, s, int, 8, 8); \
+ TEST_VTBL1(uint, u, uint, 8, 8); \
+ TEST_VTBL1(poly, p, uint, 8, 8)
+
+#define TEST_ALL_VTBLX(X) \
+ TEST_VTBLX(int, s, int, 8, 8, X); \
+ TEST_VTBLX(uint, u, uint, 8, 8, X); \
+ TEST_VTBLX(poly, p, uint, 8, 8, X)
+
+ /* Declare the temporary buffers / variables. */
+ DECL_ALL_VTBLX(2);
+ DECL_ALL_VTBLX(3);
+ DECL_ALL_VTBLX(4);
+
+ /* Fill the lookup table. */
+ for (i=0; i<32; i++) {
+ lookup_table[i] = i-15;
+ }
+
+ /* Choose init value arbitrarily, will be used as table index. */
+ VDUP(vector, , int, s, 8, 8, 1);
+ VDUP(vector, , uint, u, 8, 8, 2);
+ VDUP(vector, , poly, p, 8, 8, 2);
+
+ /* To ensure coverage, add some indexes larger than 8,16 and 32
+ except: lane 0 (by 6), lane 1 (by 8) and lane 2 (by 9). */
+ VSET_LANE(vector, , int, s, 8, 8, 0, 10);
+ VSET_LANE(vector, , int, s, 8, 8, 4, 20);
+ VSET_LANE(vector, , int, s, 8, 8, 5, 40);
+ VSET_LANE(vector, , uint, u, 8, 8, 0, 10);
+ VSET_LANE(vector, , uint, u, 8, 8, 4, 20);
+ VSET_LANE(vector, , uint, u, 8, 8, 5, 40);
+ VSET_LANE(vector, , poly, p, 8, 8, 0, 10);
+ VSET_LANE(vector, , poly, p, 8, 8, 4, 20);
+ VSET_LANE(vector, , poly, p, 8, 8, 5, 40);
+
+
+ /* Check vtbl1. */
+ clean_results ();
+#define TEST_MSG "VTBL1"
+ TEST_ALL_VTBL1();
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl1, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl1, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl1, "");
+
+ /* Check vtbl2. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBL2"
+ TEST_ALL_VTBLX(2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl2, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl2, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl2, "");
+
+ /* Check vtbl3. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBL3"
+ TEST_ALL_VTBLX(3);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl3, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl3, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl3, "");
+
+ /* Check vtbl4. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBL4"
+ TEST_ALL_VTBLX(4);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl4, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl4, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl4, "");
+
+
+ /* Now test VTBX. */
+
+ /* The vtbx1 variant is different from vtbx{2,3,4} because it takes a
+ vector as 1st param, instead of an array of vectors. */
+#define TEST_VTBX1(T1, T2, T3, W, N) \
+ VECT_VAR(table_vector, T1, W, N) = \
+ vld1##_##T2##W((T1##W##_t *)lookup_table); \
+ \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vtbx1_##T2##W(VECT_VAR(default_vector, T1, W, N), \
+ VECT_VAR(table_vector, T1, W, N), \
+ VECT_VAR(vector, T3, W, N)); \
+ vst1_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N));
+
+#define TEST_VTBXX(T1, T2, T3, W, N, X) \
+ VECT_ARRAY_VAR(table_vector, T1, W, N, X) = \
+ vld##X##_##T2##W((T1##W##_t *)lookup_table); \
+ \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vtbx##X##_##T2##W(VECT_VAR(default_vector, T1, W, N), \
+ VECT_ARRAY_VAR(table_vector, T1, W, N, X), \
+ VECT_VAR(vector, T3, W, N)); \
+ vst1_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N));
+
+#define TEST_ALL_VTBX1() \
+ TEST_VTBX1(int, s, int, 8, 8); \
+ TEST_VTBX1(uint, u, uint, 8, 8); \
+ TEST_VTBX1(poly, p, uint, 8, 8)
+
+#define TEST_ALL_VTBXX(X) \
+ TEST_VTBXX(int, s, int, 8, 8, X); \
+ TEST_VTBXX(uint, u, uint, 8, 8, X); \
+ TEST_VTBXX(poly, p, uint, 8, 8, X)
+
+ /* Choose init value arbitrarily, will be used as default value. */
+ VDUP(default_vector, , int, s, 8, 8, 0x33);
+ VDUP(default_vector, , uint, u, 8, 8, 0xCC);
+ VDUP(default_vector, , poly, p, 8, 8, 0xCC);
+
+ /* Check vtbx1. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBX1"
+ TEST_ALL_VTBX1();
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx1, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx1, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx1, "");
+
+ /* Check vtbx2. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBX2"
+ TEST_ALL_VTBXX(2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx2, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx2, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx2, "");
+
+ /* Check vtbx3. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBX3"
+ TEST_ALL_VTBXX(3);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx3, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx3, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx3, "");
+
+ /* Check vtbx4. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VTBX4"
+ TEST_ALL_VTBXX(4);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx4, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx4, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx4, "");
+}
+
+int main (void)
+{
+ exec_vtbX ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (15 preceding siblings ...)
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests Christophe Lyon
@ 2015-05-27 20:26 ` Christophe Lyon
2015-05-27 20:30 ` [Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests Christophe Lyon
` (3 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:26 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c
new file mode 100644
index 0000000..3c00497
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c
@@ -0,0 +1,117 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffd };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff3, 0xfffffff4 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff,
+ 0x0, 0x1, 0x2, 0x3,
+ 0x4, 0x5, 0x6, 0x7 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffc, 0xfffffffd,
+ 0xfffffffe, 0xffffffff };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc,
+ 0xd, 0xe, 0xf, 0x10,
+ 0x11, 0x12, 0x13, 0x14 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff,
+ 0x0, 0x1, 0x2, 0x3 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff3, 0xfffffff4,
+ 0xfffffff5, 0xfffffff6 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+
+#define TEST_MSG "VSRA_N"
+void exec_vsra_n (void)
+{
+ /* Basic test: y=vsra_n(x,v), then store the result. */
+#define TEST_VSRA_N(Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose arbitrary initialization values. */
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , int, s, 64, 1, 0x44);
+ VDUP(vector2, , uint, u, 8, 8, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x66);
+ VDUP(vector2, , uint, u, 32, 2, 0x77);
+ VDUP(vector2, , uint, u, 64, 1, 0x88);
+
+ VDUP(vector2, q, int, s, 8, 16, 0x11);
+ VDUP(vector2, q, int, s, 16, 8, 0x22);
+ VDUP(vector2, q, int, s, 32, 4, 0x33);
+ VDUP(vector2, q, int, s, 64, 2, 0x44);
+ VDUP(vector2, q, uint, u, 8, 16, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x66);
+ VDUP(vector2, q, uint, u, 32, 4, 0x77);
+ VDUP(vector2, q, uint, u, 64, 2, 0x88);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSRA_N(, int, s, 8, 8, 1);
+ TEST_VSRA_N(, int, s, 16, 4, 12);
+ TEST_VSRA_N(, int, s, 32, 2, 2);
+ TEST_VSRA_N(, int, s, 64, 1, 32);
+ TEST_VSRA_N(, uint, u, 8, 8, 2);
+ TEST_VSRA_N(, uint, u, 16, 4, 3);
+ TEST_VSRA_N(, uint, u, 32, 2, 5);
+ TEST_VSRA_N(, uint, u, 64, 1, 33);
+
+ TEST_VSRA_N(q, int, s, 8, 16, 1);
+ TEST_VSRA_N(q, int, s, 16, 8, 12);
+ TEST_VSRA_N(q, int, s, 32, 4, 2);
+ TEST_VSRA_N(q, int, s, 64, 2, 32);
+ TEST_VSRA_N(q, uint, u, 8, 16, 2);
+ TEST_VSRA_N(q, uint, u, 16, 8, 3);
+ TEST_VSRA_N(q, uint, u, 32, 4, 5);
+ TEST_VSRA_N(q, uint, u, 64, 2, 33);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vsra_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (16 preceding siblings ...)
2015-05-27 20:26 ` [Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests Christophe Lyon
@ 2015-05-27 20:30 ` Christophe Lyon
2015-05-27 20:40 ` [Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests Christophe Lyon
` (2 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:30 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
new file mode 100644
index 0000000..7f96540
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -0,0 +1,120 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results with signed input. */
+VECT_VAR_DECL(expected_signed,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_signed,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_signed,uint,32,2) [] = { 0x0, 0xffffffff };
+VECT_VAR_DECL(expected_signed,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_signed,uint,16,8) [] = { 0x0, 0xffff, 0x0, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected_signed,uint,32,4) [] = { 0x0, 0xffffffff,
+ 0x0, 0xffffffff };
+
+/* Expected results with unsigned input. */
+VECT_VAR_DECL(expected_unsigned,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_unsigned,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_unsigned,uint,32,2) [] = { 0x0, 0xffffffff };
+VECT_VAR_DECL(expected_unsigned,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
+ 0x0, 0xffff,
+ 0xffff, 0xffff,
+ 0xffff, 0xffff };
+VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
+ 0x0, 0xffffffff };
+
+#ifndef INSN_NAME
+#define INSN_NAME vtst
+#define TEST_MSG "VTST/VTSTQ"
+#endif
+
+/* We can't use the standard ref_v_binary_op.c template because vtst
+ has no 64 bits variant, and outputs are always of uint type. */
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x,x), then store the result. */
+#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, uint, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_u##W(VECT_VAR(result, uint, W, N), \
+ VECT_VAR(vector_res, uint, W, N))
+
+#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N) \
+ TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_UNSIGNED_VARIANTS(vector_res);
+
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose init value arbitrarily, will be used as comparison
+ value. */
+ VDUP(vector2, , int, s, 8, 8, 15);
+ VDUP(vector2, , int, s, 16, 4, 5);
+ VDUP(vector2, , int, s, 32, 2, 1);
+ VDUP(vector2, , uint, u, 8, 8, 15);
+ VDUP(vector2, , uint, u, 16, 4, 5);
+ VDUP(vector2, , uint, u, 32, 2, 1);
+ VDUP(vector2, q, int, s, 8, 16, 15);
+ VDUP(vector2, q, int, s, 16, 8, 5);
+ VDUP(vector2, q, int, s, 32, 4, 1);
+ VDUP(vector2, q, uint, u, 8, 16, 15);
+ VDUP(vector2, q, uint, u, 16, 8, 5);
+ VDUP(vector2, q, uint, u, 32, 4, 1);
+
+#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2) \
+ MACRO(VAR, , T1, T2, 8, 8); \
+ MACRO(VAR, , T1, T2, 16, 4); \
+ MACRO(VAR, , T1, T2, 32, 2); \
+ MACRO(VAR, q, T1, T2, 8, 16); \
+ MACRO(VAR, q, T1, T2, 16, 8); \
+ MACRO(VAR, q, T1, T2, 32, 4)
+
+ /* Split the test, as both signed and unsigned variants output their
+ result in an unsigned form (thus the same output variable is used
+ in these tests). */
+ TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME, int, s);
+
+#define CMT " (signed input)"
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_signed, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_signed, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_signed, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_signed, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_signed, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_signed, CMT);
+
+ TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME, uint, u);
+
+#undef CMT
+#define CMT " (unsigned input)"
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_unsigned, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_unsigned, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_unsigned, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
+}
+
+int main (void)
+{
+ exec_vtst ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (17 preceding siblings ...)
2015-05-27 20:30 ` [Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests Christophe Lyon
@ 2015-05-27 20:40 ` Christophe Lyon
2015-05-27 20:51 ` [Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests Christophe Lyon
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:40 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c
new file mode 100644
index 0000000..6f9ef5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c
@@ -0,0 +1,504 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x3c, 0x3c, 0x3d, 0x3d,
+ 0x3d, 0x3d, 0x3e, 0x3e };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1ffe, 0x1ffe, 0x1ffe, 0x1ffe };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x8000000, 0x8000000 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x80000000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc,
+ 0xfc, 0xfd, 0xfd, 0xfe,
+ 0xfe, 0xff, 0xff, 0x0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffc, 0xfffffffc,
+ 0xfffffffd, 0xfffffffd };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x3c, 0x3c, 0x3d, 0x3d,
+ 0x3d, 0x3d, 0x3e, 0x3e,
+ 0x3e, 0x3e, 0x3f, 0x3f,
+ 0x3f, 0x3f, 0x40, 0x40 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1ffe, 0x1ffe, 0x1ffe, 0x1ffe,
+ 0x1fff, 0x1fff, 0x1fff, 0x1fff };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x8000000, 0x8000000,
+ 0x8000000, 0x8000000 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x80000000, 0x80000000 };
+
+/* Expected results with maximum input and max shift amount. */
+VECT_VAR_DECL(expected_max_sh_max,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,64,1) [] = { 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,16,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,32,2) [] = { 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,64,1) [] = { 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,int,64,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected_max_sh_max,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,16,8) [] = { 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,32,4) [] = { 0x1, 0x1, 0x1, 0x1 };
+VECT_VAR_DECL(expected_max_sh_max,uint,64,2) [] = { 0x1, 0x1 };
+
+/* Expected results with maximum input and shift by 1. */
+VECT_VAR_DECL(expected_max_sh_1,int,8,8) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh_1,int,16,4) [] = { 0x4000, 0x4000,
+ 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh_1,int,32,2) [] = { 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh_1,int,64,1) [] = { 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh_1,uint,16,4) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,64,1) [] = { 0x8000000000000000 };
+VECT_VAR_DECL(expected_max_sh_1,int,8,16) [] = { 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40 };
+VECT_VAR_DECL(expected_max_sh_1,int,16,8) [] = { 0x4000, 0x4000,
+ 0x4000, 0x4000,
+ 0x4000, 0x4000,
+ 0x4000, 0x4000 };
+VECT_VAR_DECL(expected_max_sh_1,int,32,4) [] = { 0x40000000, 0x40000000,
+ 0x40000000, 0x40000000 };
+VECT_VAR_DECL(expected_max_sh_1,int,64,2) [] = { 0x4000000000000000,
+ 0x4000000000000000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_sh_1,uint,16,8) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_sh_1,uint,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+/* Expected results with maximum input and shift by 3. */
+VECT_VAR_DECL(expected_max_sh_3,int,8,8) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh_3,int,16,4) [] = { 0x1000, 0x1000,
+ 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh_3,int,32,2) [] = { 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh_3,int,64,1) [] = { 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,8,8) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh_3,uint,16,4) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,32,2) [] = { 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,64,1) [] = { 0x2000000000000000 };
+VECT_VAR_DECL(expected_max_sh_3,int,8,16) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected_max_sh_3,int,16,8) [] = { 0x1000, 0x1000,
+ 0x1000, 0x1000,
+ 0x1000, 0x1000,
+ 0x1000, 0x1000 };
+VECT_VAR_DECL(expected_max_sh_3,int,32,4) [] = { 0x10000000, 0x10000000,
+ 0x10000000, 0x10000000 };
+VECT_VAR_DECL(expected_max_sh_3,int,64,2) [] = { 0x1000000000000000,
+ 0x1000000000000000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,8,16) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_sh_3,uint,16,8) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,32,4) [] = { 0x20000000, 0x20000000,
+ 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_sh_3,uint,64,2) [] = { 0x2000000000000000,
+ 0x2000000000000000 };
+
+/* Expected results with max negative input (for signed types, shift
+ by 1. */
+VECT_VAR_DECL(expected_max_neg_sh_1,int,8,8) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,16,4) [] = { 0xc000, 0xc000,
+ 0xc000, 0xc000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,32,2) [] = { 0xc0000000, 0xc0000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,64,1) [] = { 0xc000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,16,4) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,32,2) [] = { 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,64,1) [] = { 0x8000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,8,16) [] = { 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0,
+ 0xc0, 0xc0, 0xc0, 0xc0 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,16,8) [] = { 0xc000, 0xc000,
+ 0xc000, 0xc000,
+ 0xc000, 0xc000,
+ 0xc000, 0xc000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,32,4) [] = { 0xc0000000, 0xc0000000,
+ 0xc0000000, 0xc0000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,int,64,2) [] = { 0xc000000000000000,
+ 0xc000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,16,8) [] = { 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000,
+ 0x8000, 0x8000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_max_neg_sh_1,uint,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+/* Expected results with max negative input (for signed types, shift
+ by 3. */
+VECT_VAR_DECL(expected_max_neg_sh_3,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,16,4) [] = { 0xf000, 0xf000,
+ 0xf000, 0xf000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,32,2) [] = { 0xf0000000, 0xf0000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,64,1) [] = { 0xf000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,8,8) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,16,4) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,32,2) [] = { 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,64,1) [] = { 0x2000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,16,8) [] = { 0xf000, 0xf000,
+ 0xf000, 0xf000,
+ 0xf000, 0xf000,
+ 0xf000, 0xf000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,32,4) [] = { 0xf0000000, 0xf0000000,
+ 0xf0000000, 0xf0000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,int,64,2) [] = { 0xf000000000000000,
+ 0xf000000000000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,8,16) [] = { 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,16,8) [] = { 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000,
+ 0x2000, 0x2000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,32,4) [] = { 0x20000000, 0x20000000,
+ 0x20000000, 0x20000000 };
+VECT_VAR_DECL(expected_max_neg_sh_3,uint,64,2) [] = { 0x2000000000000000,
+ 0x2000000000000000 };
+
+#define TEST_MSG "VRSHR_N"
+void exec_vrshr_n (void)
+{
+ /* Basic test: y=vrshr_n(x,v), then store the result. */
+#define TEST_VRSHR_N(Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrshr##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VRSHR_N(, int, s, 8, 8, 1);
+ TEST_VRSHR_N(, int, s, 16, 4, 12);
+ TEST_VRSHR_N(, int, s, 32, 2, 2);
+ TEST_VRSHR_N(, int, s, 64, 1, 32);
+ TEST_VRSHR_N(, uint, u, 8, 8, 2);
+ TEST_VRSHR_N(, uint, u, 16, 4, 3);
+ TEST_VRSHR_N(, uint, u, 32, 2, 5);
+ TEST_VRSHR_N(, uint, u, 64, 1, 33);
+
+ TEST_VRSHR_N(q, int, s, 8, 16, 1);
+ TEST_VRSHR_N(q, int, s, 16, 8, 12);
+ TEST_VRSHR_N(q, int, s, 32, 4, 2);
+ TEST_VRSHR_N(q, int, s, 64, 2, 32);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 2);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 3);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 5);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 33);
+
+#define CMT ""
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT);
+
+
+ /* Use maximum positive input value. */
+ VDUP(vector, , int, s, 8, 8, 0x7F);
+ VDUP(vector, , int, s, 16, 4, 0x7FFF);
+ VDUP(vector, , int, s, 32, 2, 0x7FFFFFFF);
+ VDUP(vector, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector, , uint, u, 8, 8, 0xFF);
+ VDUP(vector, , uint, u, 16, 4, 0xFFFF);
+ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
+ VDUP(vector, q, int, s, 8, 16, 0x7F);
+ VDUP(vector, q, int, s, 16, 8, 0x7FFF);
+ VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF);
+ VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
+ VDUP(vector, q, uint, u, 8, 16, 0xFF);
+ VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
+ VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
+ VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
+
+ /* Use max shift amount, to exercise saturation. */
+ TEST_VRSHR_N(, int, s, 8, 8, 8);
+ TEST_VRSHR_N(, int, s, 16, 4, 16);
+ TEST_VRSHR_N(, int, s, 32, 2, 32);
+ TEST_VRSHR_N(, int, s, 64, 1, 64);
+ TEST_VRSHR_N(, uint, u, 8, 8, 8);
+ TEST_VRSHR_N(, uint, u, 16, 4, 16);
+ TEST_VRSHR_N(, uint, u, 32, 2, 32);
+ TEST_VRSHR_N(, uint, u, 64, 1, 64);
+ TEST_VRSHR_N(q, int, s, 8, 16, 8);
+ TEST_VRSHR_N(q, int, s, 16, 8, 16);
+ TEST_VRSHR_N(q, int, s, 32, 4, 32);
+ TEST_VRSHR_N(q, int, s, 64, 2, 64);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 8);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 16);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 32);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 64);
+
+#undef CMT
+#define CMT " (overflow test: max shift amount, max positive input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_max, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_max, CMT);
+
+
+ /* Use 1 as shift amount, to exercise saturation. */
+ TEST_VRSHR_N(, int, s, 8, 8, 1);
+ TEST_VRSHR_N(, int, s, 16, 4, 1);
+ TEST_VRSHR_N(, int, s, 32, 2, 1);
+ TEST_VRSHR_N(, int, s, 64, 1, 1);
+ TEST_VRSHR_N(, uint, u, 8, 8, 1);
+ TEST_VRSHR_N(, uint, u, 16, 4, 1);
+ TEST_VRSHR_N(, uint, u, 32, 2, 1);
+ TEST_VRSHR_N(, uint, u, 64, 1, 1);
+ TEST_VRSHR_N(q, int, s, 8, 16, 1);
+ TEST_VRSHR_N(q, int, s, 16, 8, 1);
+ TEST_VRSHR_N(q, int, s, 32, 4, 1);
+ TEST_VRSHR_N(q, int, s, 64, 2, 1);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 1);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 1);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 1);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 1);
+
+#undef CMT
+#define CMT " (overflow test: shift by 1, with max input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_1, CMT);
+
+
+ /* Use 3 as shift amount, to exercise saturation. */
+ TEST_VRSHR_N(, int, s, 8, 8, 3);
+ TEST_VRSHR_N(, int, s, 16, 4, 3);
+ TEST_VRSHR_N(, int, s, 32, 2, 3);
+ TEST_VRSHR_N(, int, s, 64, 1, 3);
+ TEST_VRSHR_N(, uint, u, 8, 8, 3);
+ TEST_VRSHR_N(, uint, u, 16, 4, 3);
+ TEST_VRSHR_N(, uint, u, 32, 2, 3);
+ TEST_VRSHR_N(, uint, u, 64, 1, 3);
+ TEST_VRSHR_N(q, int, s, 8, 16, 3);
+ TEST_VRSHR_N(q, int, s, 16, 8, 3);
+ TEST_VRSHR_N(q, int, s, 32, 4, 3);
+ TEST_VRSHR_N(q, int, s, 64, 2, 3);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 3);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 3);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 3);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 3);
+
+#undef CMT
+#define CMT " (overflow test: shift by 3, with max input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_sh_3, CMT);
+
+
+ /* Use minimum negative input for signed types. */
+ VDUP(vector, , int, s, 8, 8, 0x80);
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector, , int, s, 64, 1, 0x8000000000000000LL);
+ VDUP(vector, , uint, u, 8, 8, 0xFF);
+ VDUP(vector, , uint, u, 16, 4, 0xFFFF);
+ VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
+ VDUP(vector, , uint, u, 64, 1, 0xFFFFFFFFFFFFFFFFULL);
+ VDUP(vector, q, int, s, 8, 16, 0x80);
+ VDUP(vector, q, int, s, 16, 8, 0x8000);
+ VDUP(vector, q, int, s, 32, 4, 0x80000000);
+ VDUP(vector, q, int, s, 64, 2, 0x8000000000000000LL);
+ VDUP(vector, q, uint, u, 8, 16, 0xFF);
+ VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
+ VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
+ VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
+
+
+ /* Use 1 as shift amount, to exercise saturation code. */
+ TEST_VRSHR_N(, int, s, 8, 8, 1);
+ TEST_VRSHR_N(, int, s, 16, 4, 1);
+ TEST_VRSHR_N(, int, s, 32, 2, 1);
+ TEST_VRSHR_N(, int, s, 64, 1, 1);
+ TEST_VRSHR_N(, uint, u, 8, 8, 1);
+ TEST_VRSHR_N(, uint, u, 16, 4, 1);
+ TEST_VRSHR_N(, uint, u, 32, 2, 1);
+ TEST_VRSHR_N(, uint, u, 64, 1, 1);
+ TEST_VRSHR_N(q, int, s, 8, 16, 1);
+ TEST_VRSHR_N(q, int, s, 16, 8, 1);
+ TEST_VRSHR_N(q, int, s, 32, 4, 1);
+ TEST_VRSHR_N(q, int, s, 64, 2, 1);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 1);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 1);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 1);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 1);
+
+#undef CMT
+#define CMT " (overflow test: shift by 1, with negative input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_neg_sh_1, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_neg_sh_1, CMT);
+
+
+ /* Use 3 as shift amount, to exercise saturation code. */
+ TEST_VRSHR_N(, int, s, 8, 8, 3);
+ TEST_VRSHR_N(, int, s, 16, 4, 3);
+ TEST_VRSHR_N(, int, s, 32, 2, 3);
+ TEST_VRSHR_N(, int, s, 64, 1, 3);
+ TEST_VRSHR_N(, uint, u, 8, 8, 3);
+ TEST_VRSHR_N(, uint, u, 16, 4, 3);
+ TEST_VRSHR_N(, uint, u, 32, 2, 3);
+ TEST_VRSHR_N(, uint, u, 64, 1, 3);
+ TEST_VRSHR_N(q, int, s, 8, 16, 3);
+ TEST_VRSHR_N(q, int, s, 16, 8, 3);
+ TEST_VRSHR_N(q, int, s, 32, 4, 3);
+ TEST_VRSHR_N(q, int, s, 64, 2, 3);
+ TEST_VRSHR_N(q, uint, u, 8, 16, 3);
+ TEST_VRSHR_N(q, uint, u, 16, 8, 3);
+ TEST_VRSHR_N(q, uint, u, 32, 4, 3);
+ TEST_VRSHR_N(q, uint, u, 64, 2, 3);
+
+#undef CMT
+#define CMT " (overflow test: shift by 3, with negative input)"
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_neg_sh_3, CMT);
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_neg_sh_3, CMT);
+}
+
+int main (void)
+{
+ exec_vrshr_n ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests.
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (18 preceding siblings ...)
2015-05-27 20:40 ` [Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests Christophe Lyon
@ 2015-05-27 20:51 ` Christophe Lyon
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
20 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-05-27 20:51 UTC (permalink / raw)
To: gcc-patches
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
new file mode 100644
index 0000000..3b574da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
@@ -0,0 +1,200 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results for vrev16. */
+VECT_VAR_DECL(expected_vrev16,int,8,8) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6 };
+VECT_VAR_DECL(expected_vrev16,uint,8,8) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6 };
+VECT_VAR_DECL(expected_vrev16,poly,8,8) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6 };
+VECT_VAR_DECL(expected_vrev16,int,8,16) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6,
+ 0xf9, 0xf8, 0xfb, 0xfa,
+ 0xfd, 0xfc, 0xff, 0xfe };
+VECT_VAR_DECL(expected_vrev16,uint,8,16) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6,
+ 0xf9, 0xf8, 0xfb, 0xfa,
+ 0xfd, 0xfc, 0xff, 0xfe };
+VECT_VAR_DECL(expected_vrev16,poly,8,16) [] = { 0xf1, 0xf0, 0xf3, 0xf2,
+ 0xf5, 0xf4, 0xf7, 0xf6,
+ 0xf9, 0xf8, 0xfb, 0xfa,
+ 0xfd, 0xfc, 0xff, 0xfe };
+
+/* Expected results for vrev32. */
+VECT_VAR_DECL(expected_vrev32,int,8,8) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4 };
+VECT_VAR_DECL(expected_vrev32,int,16,4) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2 };
+VECT_VAR_DECL(expected_vrev32,uint,8,8) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4 };
+VECT_VAR_DECL(expected_vrev32,uint,16,4) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2 };
+VECT_VAR_DECL(expected_vrev32,poly,8,8) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4 };
+VECT_VAR_DECL(expected_vrev32,poly,16,4) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2 };
+VECT_VAR_DECL(expected_vrev32,int,8,16) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xfb, 0xfa, 0xf9, 0xf8,
+ 0xff, 0xfe, 0xfd, 0xfc };
+VECT_VAR_DECL(expected_vrev32,int,16,8) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2,
+ 0xfff5, 0xfff4, 0xfff7, 0xfff6 };
+VECT_VAR_DECL(expected_vrev32,uint,8,16) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xfb, 0xfa, 0xf9, 0xf8,
+ 0xff, 0xfe, 0xfd, 0xfc };
+VECT_VAR_DECL(expected_vrev32,uint,16,8) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2,
+ 0xfff5, 0xfff4, 0xfff7, 0xfff6 };
+VECT_VAR_DECL(expected_vrev32,poly,8,16) [] = { 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xfb, 0xfa, 0xf9, 0xf8,
+ 0xff, 0xfe, 0xfd, 0xfc };
+VECT_VAR_DECL(expected_vrev32,poly,16,8) [] = { 0xfff1, 0xfff0, 0xfff3, 0xfff2,
+ 0xfff5, 0xfff4, 0xfff7, 0xfff6 };
+
+/* Expected results for vrev64. */
+VECT_VAR_DECL(expected_vrev64,int,8,8) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xf3, 0xf2, 0xf1, 0xf0 };
+VECT_VAR_DECL(expected_vrev64,int,16,4) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0 };
+VECT_VAR_DECL(expected_vrev64,int,32,2) [] = { 0xfffffff1, 0xfffffff0 };
+VECT_VAR_DECL(expected_vrev64,uint,8,8) [] = { 0xf7, 0xf6, 0xf5, 0xf4, 0xf3,
+ 0xf2, 0xf1, 0xf0 };
+VECT_VAR_DECL(expected_vrev64,uint,16,4) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0 };
+VECT_VAR_DECL(expected_vrev64,uint,32,2) [] = { 0xfffffff1, 0xfffffff0 };
+VECT_VAR_DECL(expected_vrev64,poly,8,8) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xf3, 0xf2, 0xf1, 0xf0 };
+VECT_VAR_DECL(expected_vrev64,poly,16,4) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0 };
+VECT_VAR_DECL(expected_vrev64,hfloat,32,2) [] = { 0xc1700000, 0xc1800000 };
+VECT_VAR_DECL(expected_vrev64,int,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xff, 0xfe, 0xfd, 0xfc,
+ 0xfb, 0xfa, 0xf9, 0xf8 };
+VECT_VAR_DECL(expected_vrev64,int,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
+ 0xfff7, 0xfff6, 0xfff5, 0xfff4 };
+VECT_VAR_DECL(expected_vrev64,int,32,4) [] = { 0xfffffff1, 0xfffffff0,
+ 0xfffffff3, 0xfffffff2 };
+VECT_VAR_DECL(expected_vrev64,uint,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xff, 0xfe, 0xfd, 0xfc,
+ 0xfb, 0xfa, 0xf9, 0xf8 };
+VECT_VAR_DECL(expected_vrev64,uint,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
+ 0xfff7, 0xfff6, 0xfff5, 0xfff4 };
+VECT_VAR_DECL(expected_vrev64,uint,32,4) [] = { 0xfffffff1, 0xfffffff0,
+ 0xfffffff3, 0xfffffff2 };
+VECT_VAR_DECL(expected_vrev64,poly,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 0xf3, 0xf2, 0xf1, 0xf0,
+ 0xff, 0xfe, 0xfd, 0xfc,
+ 0xfb, 0xfa, 0xf9, 0xf8 };
+VECT_VAR_DECL(expected_vrev64,poly,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
+ 0xfff7, 0xfff6, 0xfff5, 0xfff4 };
+VECT_VAR_DECL(expected_vrev64,hfloat,32,4) [] = { 0xc1700000, 0xc1800000,
+ 0xc1500000, 0xc1600000 };
+
+void exec_vrev (void)
+{
+ /* Basic test: y=vrev(x), then store the result. */
+#define TEST_VREV(Q, T1, T2, W, N, W2) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vrev##W2##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ /* Check vrev in each of the existing combinations. */
+#define TEST_MSG "VREV16"
+ TEST_VREV(, int, s, 8, 8, 16);
+ TEST_VREV(, uint, u, 8, 8, 16);
+ TEST_VREV(, poly, p, 8, 8, 16);
+ TEST_VREV(q, int, s, 8, 16, 16);
+ TEST_VREV(q, uint, u, 8, 16, 16);
+ TEST_VREV(q, poly, p, 8, 16, 16);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vrev16, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev16, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev16, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev16, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev16, "");
+ CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev16, "");
+
+#undef TEST_MSG
+#define TEST_MSG "VREV32"
+ TEST_VREV(, int, s, 8, 8, 32);
+ TEST_VREV(, int, s, 16, 4, 32);
+ TEST_VREV(, uint, u, 8, 8, 32);
+ TEST_VREV(, uint, u, 16, 4, 32);
+ TEST_VREV(, poly, p, 8, 8, 32);
+ TEST_VREV(, poly, p, 16, 4, 32);
+ TEST_VREV(q, int, s, 8, 16, 32);
+ TEST_VREV(q, int, s, 16, 8, 32);
+ TEST_VREV(q, uint, u, 8, 16, 32);
+ TEST_VREV(q, uint, u, 16, 8, 32);
+ TEST_VREV(q, poly, p, 8, 16, 32);
+ TEST_VREV(q, poly, p, 16, 8, 32);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_vrev32, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev32, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev32, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev32, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev32, "");
+ CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev32, "");
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev32, "");
+
+#undef TEST_MSG
+#define TEST_MSG "VREV64"
+ TEST_VREV(, int, s, 8, 8, 64);
+ TEST_VREV(, int, s, 16, 4, 64);
+ TEST_VREV(, int, s, 32, 2, 64);
+ TEST_VREV(, uint, u, 8, 8, 64);
+ TEST_VREV(, uint, u, 16, 4, 64);
+ TEST_VREV(, uint, u, 32, 2, 64);
+ TEST_VREV(, poly, p, 8, 8, 64);
+ TEST_VREV(, poly, p, 16, 4, 64);
+ TEST_VREV(q, int, s, 8, 16, 64);
+ TEST_VREV(q, int, s, 16, 8, 64);
+ TEST_VREV(q, int, s, 32, 4, 64);
+ TEST_VREV(q, uint, u, 8, 16, 64);
+ TEST_VREV(q, uint, u, 16, 8, 64);
+ TEST_VREV(q, uint, u, 32, 4, 64);
+ TEST_VREV(q, poly, p, 8, 16, 64);
+ TEST_VREV(q, poly, p, 16, 8, 64);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_vrev64, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_vrev64, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev64, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev64, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev64, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_vrev64, "");
+ CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev64, "");
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev64, "");
+
+ TEST_VREV(, float, f, 32, 2, 64);
+ TEST_VREV(q, float, f, 32, 4, 64);
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_vrev64, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_vrev64, "");
+}
+
+int main (void)
+{
+ exec_vrev ();
+ return 0;
+}
--
2.1.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
` (19 preceding siblings ...)
2015-05-27 20:51 ` [Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests Christophe Lyon
@ 2015-06-15 22:15 ` Christophe Lyon
2015-06-16 10:10 ` James Greenhalgh
2015-11-02 14:20 ` Jiong Wang
20 siblings, 2 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-06-15 22:15 UTC (permalink / raw)
To: gcc-patches
Ping?
On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> This patch series is a follow-up to the tests I already contributed,
> converted from my original testsuite.
>
> This series consists in 20 new patches, which can be committed
> independently. For vrecpe, I added the setting of the "Flush-to-Zero"
> FP flag, to force AArch64 to behave the same as ARM by default.
>
> This is the final batch, except for the vget_lane tests which I will
> submit later. This should cover the subset of AdvSIMD intrinsics
> common to ARMv7 and AArch64.
>
> Tested with qemu on arm*linux, aarch64-linux.
>
> 2015-05-27 Christophe Lyon <christophe.lyon@linaro.org>
>
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> (_ARM_FPSCR): Add FZ field.
> (clean_results): Force FZ=1 on AArch64.
> * gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
>
> Christophe Lyon (20):
> Add vrecpe tests.
> Add vrecps tests.
> Add vreinterpret tests.
> Add vrev tests.
> Add vrshl tests.
> Add vshr_n tests.
> Add vrshr_n tests.
> Add vrshrn_n tests.
> Add vrsqrte tests.
> Add vrsqrts tests.
> Add vrsra_n tests.
> Add vset_lane tests.
> Add vshll_n tests.
> Add vshl_n tests.
> Add vshrn_n tests.
> Add vsra_n tests.
> Add vst1_lane tests.
> Add vstX_lane tests.
> Add vtbX tests.
> Add vtst tests.
>
> .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 19 +-
> .../gcc.target/aarch64/advsimd-intrinsics/vrecpe.c | 154 +++++
> .../gcc.target/aarch64/advsimd-intrinsics/vrecps.c | 117 ++++
> .../aarch64/advsimd-intrinsics/vreinterpret.c | 741 +++++++++++++++++++++
> .../gcc.target/aarch64/advsimd-intrinsics/vrev.c | 200 ++++++
> .../gcc.target/aarch64/advsimd-intrinsics/vrshl.c | 627 +++++++++++++++++
> .../aarch64/advsimd-intrinsics/vrshr_n.c | 504 ++++++++++++++
> .../aarch64/advsimd-intrinsics/vrshrn_n.c | 143 ++++
> .../aarch64/advsimd-intrinsics/vrsqrte.c | 157 +++++
> .../aarch64/advsimd-intrinsics/vrsqrts.c | 118 ++++
> .../aarch64/advsimd-intrinsics/vrsra_n.c | 553 +++++++++++++++
> .../aarch64/advsimd-intrinsics/vset_lane.c | 99 +++
> .../gcc.target/aarch64/advsimd-intrinsics/vshl_n.c | 96 +++
> .../aarch64/advsimd-intrinsics/vshll_n.c | 56 ++
> .../gcc.target/aarch64/advsimd-intrinsics/vshr_n.c | 95 +++
> .../aarch64/advsimd-intrinsics/vshrn_n.c | 70 ++
> .../gcc.target/aarch64/advsimd-intrinsics/vsra_n.c | 117 ++++
> .../aarch64/advsimd-intrinsics/vst1_lane.c | 93 +++
> .../aarch64/advsimd-intrinsics/vstX_lane.c | 578 ++++++++++++++++
> .../gcc.target/aarch64/advsimd-intrinsics/vtbX.c | 289 ++++++++
> .../gcc.target/aarch64/advsimd-intrinsics/vtst.c | 120 ++++
> 21 files changed, 4940 insertions(+), 6 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
@ 2015-06-16 10:10 ` James Greenhalgh
2015-06-16 13:26 ` Christophe Lyon
2015-11-02 14:20 ` Jiong Wang
1 sibling, 1 reply; 27+ messages in thread
From: James Greenhalgh @ 2015-06-16 10:10 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On Mon, Jun 15, 2015 at 11:11:16PM +0100, Christophe Lyon wrote:
> Ping?
>
>
> On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> > This patch series is a follow-up to the tests I already contributed,
> > converted from my original testsuite.
> >
> > This series consists in 20 new patches, which can be committed
> > independently. For vrecpe, I added the setting of the "Flush-to-Zero"
> > FP flag, to force AArch64 to behave the same as ARM by default.
> >
> > This is the final batch, except for the vget_lane tests which I will
> > submit later. This should cover the subset of AdvSIMD intrinsics
> > common to ARMv7 and AArch64.
> >
> > Tested with qemu on arm*linux, aarch64-linux.
> >
> > 2015-05-27 Christophe Lyon <christophe.lyon@linaro.org>
> >
> > * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> > (_ARM_FPSCR): Add FZ field.
> > (clean_results): Force FZ=1 on AArch64.
> > * gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file.
> > * gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
> > * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
> >
This patch set is OK.
As with the last patch set, please do a quick run through of each patch
before committing and ensure that the trailing '\' characters line up,
and look for any fall-out (particularly on aarch64_be) after these are in.
Thanks,
James
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-06-16 10:10 ` James Greenhalgh
@ 2015-06-16 13:26 ` Christophe Lyon
0 siblings, 0 replies; 27+ messages in thread
From: Christophe Lyon @ 2015-06-16 13:26 UTC (permalink / raw)
To: James Greenhalgh; +Cc: gcc-patches
On 16 June 2015 at 12:08, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> On Mon, Jun 15, 2015 at 11:11:16PM +0100, Christophe Lyon wrote:
>> Ping?
>>
>>
>> On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> > This patch series is a follow-up to the tests I already contributed,
>> > converted from my original testsuite.
>> >
>> > This series consists in 20 new patches, which can be committed
>> > independently. For vrecpe, I added the setting of the "Flush-to-Zero"
>> > FP flag, to force AArch64 to behave the same as ARM by default.
>> >
>> > This is the final batch, except for the vget_lane tests which I will
>> > submit later. This should cover the subset of AdvSIMD intrinsics
>> > common to ARMv7 and AArch64.
>> >
>> > Tested with qemu on arm*linux, aarch64-linux.
>> >
>> > 2015-05-27 Christophe Lyon <christophe.lyon@linaro.org>
>> >
>> > * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
>> > (_ARM_FPSCR): Add FZ field.
>> > (clean_results): Force FZ=1 on AArch64.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
>> > * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
>> >
>
> This patch set is OK.
>
> As with the last patch set, please do a quick run through of each patch
> before committing and ensure that the trailing '\' characters line up,
> and look for any fall-out (particularly on aarch64_be) after these are in.
>
I've just re-run the tests on aarch64_be, and the vtbX one is failing
when testing vtlb3.
It does pass on armeb, so I expect the test to be correctly written to
be endianness independant.
As a reminder, there are still several other tests failing on aarch64_be:
vldX_lane
vtrn
vzip
vuzp
we have PR63652 and 63653 for these.
> Thanks,
> James
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-06-16 10:10 ` James Greenhalgh
@ 2015-11-02 14:20 ` Jiong Wang
2015-11-02 14:38 ` Christophe Lyon
1 sibling, 1 reply; 27+ messages in thread
From: Jiong Wang @ 2015-11-02 14:20 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org>
wrote:
>> * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
>>
Noticed this testcase failed on big-endian on my local test
gcc.target/aarch64/advsimd-intrinsics/vtbX.c line 188 in buffer
'expected_vtbl3') at type int8x8 index 0: got 0x0 != 0xfff8
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-11-02 14:20 ` Jiong Wang
@ 2015-11-02 14:38 ` Christophe Lyon
2015-11-02 14:47 ` Jiong Wang
0 siblings, 1 reply; 27+ messages in thread
From: Christophe Lyon @ 2015-11-02 14:38 UTC (permalink / raw)
To: Jiong Wang; +Cc: gcc-patches
On 2 November 2015 at 15:20, Jiong Wang <jiong.wang@foss.arm.com> wrote:
> On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
>>>
>
> Noticed this testcase failed on big-endian on my local test
>
> gcc.target/aarch64/advsimd-intrinsics/vtbX.c line 188 in buffer
> 'expected_vtbl3') at type int8x8 index 0: got 0x0 != 0xfff8
>
which version of trunk are you using?
This with the case indeed when I committed the tests, but I fixed
those intrinsics a few weeks ago,
as commit 228716.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
2015-11-02 14:38 ` Christophe Lyon
@ 2015-11-02 14:47 ` Jiong Wang
0 siblings, 0 replies; 27+ messages in thread
From: Jiong Wang @ 2015-11-02 14:47 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 02/11/15 14:38, Christophe Lyon wrote:
> On 2 November 2015 at 15:20, Jiong Wang <jiong.wang@foss.arm.com> wrote:
>> On 27 May 2015 at 22:15, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>>> * gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
>>>>
>> Noticed this testcase failed on big-endian on my local test
>>
>> gcc.target/aarch64/advsimd-intrinsics/vtbX.c line 188 in buffer
>> 'expected_vtbl3') at type int8x8 index 0: got 0x0 != 0xfff8
>>
> which version of trunk are you using?
>
> This with the case indeed when I committed the tests, but I fixed
> those intrinsics a few weeks ago,
> as commit 228716.
Um... I forget to update my big-endian test tree, sorry for the noise.
commit 7d1cd01c170b4730d05c1b8137d818415ae31cd8
Author: spop <spop@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed Oct 7 16:19:09 2015 +0000
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2015-11-02 14:47 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-27 20:16 [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-05-27 20:16 ` [Patch ARM-AArch64/testsuite Neon intrinsics 08/20] Add vrshrn_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 18/20] Add vstX_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 19/20] Add vtbX tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 12/20] Add vset_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 15/20] Add vshrn_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 11/20] Add vrsra_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 17/20] Add vst1_lane tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 10/20] Add vrsqrts tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 13/20] Add vshll_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 09/20] Add vrsqrte tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 03/20] Add vreinterpret tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 14/20] Add vshl_n tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 01/20] Add vrecpe tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 02/20] Add vrecps tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 05/20] Add vrshl tests Christophe Lyon
2015-05-27 20:17 ` [Patch ARM-AArch64/testsuite Neon intrinsics 06/20] Add vshr_n tests Christophe Lyon
2015-05-27 20:26 ` [Patch ARM-AArch64/testsuite Neon intrinsics 16/20] Add vsra_n tests Christophe Lyon
2015-05-27 20:30 ` [Patch ARM-AArch64/testsuite Neon intrinsics 20/20] Add vtst tests Christophe Lyon
2015-05-27 20:40 ` [Patch ARM-AArch64/testsuite Neon intrinsics 07/20] Add vrshr_n tests Christophe Lyon
2015-05-27 20:51 ` [Patch ARM-AArch64/testsuite Neon intrinsics 04/20] Add vrev tests Christophe Lyon
2015-06-15 22:15 ` [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests Christophe Lyon
2015-06-16 10:10 ` James Greenhalgh
2015-06-16 13:26 ` Christophe Lyon
2015-11-02 14:20 ` Jiong Wang
2015-11-02 14:38 ` Christophe Lyon
2015-11-02 14:47 ` Jiong Wang
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