* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
@ 2023-10-22 22:35 ` bruno at clisp dot org
2023-10-23 14:11 ` adhemerval.zanella at linaro dot org
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: bruno at clisp dot org @ 2023-10-22 22:35 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
Bruno Haible <bruno at clisp dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Host| |powerpc64-unknown-linux-gnu
--- Comment #1 from Bruno Haible <bruno at clisp dot org> ---
Seen on
- glibc 2.37 (gcc203.fsffrance.org, POWER8 CPU)
- glibc 2.36 (cfarm29.cfarm.net, POWER9 CPU)
- glibc 2.34 (gcc120.fsffrance.org, POWER10 CPU)
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* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
2023-10-22 22:35 ` [Bug math/30988] " bruno at clisp dot org
@ 2023-10-23 14:11 ` adhemerval.zanella at linaro dot org
2023-10-23 14:28 ` bruno at clisp dot org
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: adhemerval.zanella at linaro dot org @ 2023-10-23 14:11 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
Adhemerval Zanella <adhemerval.zanella at linaro dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |adhemerval.zanella at linaro dot o
| |rg
--- Comment #2 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
Indeed, this seems to be an unexpected side-effect of how we implement the GNU
extension feenableexcept and returning an error seems the best option indeed.
Maybe something like:
diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
b/sysdeps/powerpc/fpu/fesetexcept.c
index 609a148a95..e5396daf44 100644
--- a/sysdeps/powerpc/fpu/fesetexcept.c
+++ b/sysdeps/powerpc/fpu/fesetexcept.c
@@ -29,6 +29,10 @@ fesetexcept (int excepts)
/* Turn FE_INVALID into FE_INVALID_SOFTWARE. */
| (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
& FE_INVALID_SOFTWARE));
+
+ if (u.l & FPSCR_ENABLES_MASK)
+ return -1;
+
if (n.l != u.l)
{
fesetenv_register (n.fenv);
--
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* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
2023-10-22 22:35 ` [Bug math/30988] " bruno at clisp dot org
2023-10-23 14:11 ` adhemerval.zanella at linaro dot org
@ 2023-10-23 14:28 ` bruno at clisp dot org
2023-10-23 14:51 ` adhemerval.zanella at linaro dot org
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: bruno at clisp dot org @ 2023-10-23 14:28 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
--- Comment #3 from Bruno Haible <bruno at clisp dot org> ---
(In reply to Adhemerval Zanella from comment #2)
> Indeed, this seems to be an unexpected side-effect of how we implement the
> GNU extension feenableexcept
There's no better way, IMO, to implement feenableexcept. The problem
really comes from the hardware.
> Maybe something like:
>
> diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
> b/sysdeps/powerpc/fpu/fesetexcept.c
> index 609a148a95..e5396daf44 100644
> --- a/sysdeps/powerpc/fpu/fesetexcept.c
> +++ b/sysdeps/powerpc/fpu/fesetexcept.c
> @@ -29,6 +29,10 @@ fesetexcept (int excepts)
> /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */
> | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
> & FE_INVALID_SOFTWARE));
> +
> + if (u.l & FPSCR_ENABLES_MASK)
> + return -1;
> +
> if (n.l != u.l)
> {
> fesetenv_register (n.fenv);
This patch has the drawback of failing even in some situations that it could
handle. For example, if trapping on FE_DIVBYZERO is enabled and someone calls
fesetexcept (FE_INVALID), there is no reason to fail. I would therefore suggest
this patch instead:
diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
b/sysdeps/powerpc/fpu/fesetexcept.c
index 609a148a95..5137df7ba1 100644
--- a/sysdeps/powerpc/fpu/fesetexcept.c
+++ b/sysdeps/powerpc/fpu/fesetexcept.c
@@ -31,6 +31,13 @@ fesetexcept (int excepts)
& FE_INVALID_SOFTWARE));
if (n.l != u.l)
{
+ if (n.l & (exceptions >> FPSCR_EXCEPT_TO_ENABLE_SHIFT))
+ {
+ /* Setting the exception flags may trigger a trap.
+ ISO C 23 § 7.6.4.4 does not allow it. */
+ return 1;
+ }
+
fesetenv_register (n.fenv);
/* Deal with FE_INVALID_SOFTWARE not being implemented on some chips.
*/
--
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* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
` (2 preceding siblings ...)
2023-10-23 14:28 ` bruno at clisp dot org
@ 2023-10-23 14:51 ` adhemerval.zanella at linaro dot org
2023-10-23 15:05 ` bruno at clisp dot org
2023-12-19 18:36 ` adhemerval.zanella at linaro dot org
5 siblings, 0 replies; 7+ messages in thread
From: adhemerval.zanella at linaro dot org @ 2023-10-23 14:51 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
--- Comment #4 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
In fact, we are already aware of this limitation and the tests are masking off
this issue with the internal EXCEPTION_SET_FORCES_TRAP flag (set only for
powerpc). I am unsure why Joseph did not consider this a bug when he added the
tests. The fesetexceptflag has the same issue, so I think we will need
something like:
diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c
index 71b6e45b33..96f6c4752f 100644
--- a/math/test-fesetexcept-traps.c
+++ b/math/test-fesetexcept-traps.c
@@ -39,16 +39,13 @@ do_test (void)
return result;
}
- if (EXCEPTION_SET_FORCES_TRAP)
- {
- puts ("setting exceptions traps, cannot test on this architecture");
- return 77;
- }
- /* Verify fesetexcept does not cause exception traps. */
+ /* Verify fesetexcept does not cause exception traps. For architectures
+ where setting the exception might result in traps the function should
+ return a nonzero value. */
ret = fesetexcept (FE_ALL_EXCEPT);
if (ret == 0)
puts ("fesetexcept (FE_ALL_EXCEPT) succeeded");
- else
+ else if (!EXCEPTION_SET_FORCES_TRAP)
{
puts ("fesetexcept (FE_ALL_EXCEPT) failed");
if (EXCEPTION_TESTS (float))
diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c
index 9701c3c320..9b8f583ae6 100644
--- a/math/test-fexcept-traps.c
+++ b/math/test-fexcept-traps.c
@@ -63,14 +63,11 @@ do_test (void)
result = 1;
}
- if (EXCEPTION_SET_FORCES_TRAP)
- {
- puts ("setting exceptions traps, cannot test on this architecture");
- return 77;
- }
- /* The test is that this does not cause exception traps. */
+ /* The test is that this does not cause exception traps. For architectures
+ where setting the exception might result in traps the function should
+ return a nonzero value. */
ret = fesetexceptflag (&saved, FE_ALL_EXCEPT);
- if (ret != 0)
+ if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP)
{
puts ("fesetexceptflag failed");
result = 1;
diff --git a/sysdeps/powerpc/fpu/fesetexcept.c
b/sysdeps/powerpc/fpu/fesetexcept.c
index 609a148a95..2850156d3a 100644
--- a/sysdeps/powerpc/fpu/fesetexcept.c
+++ b/sysdeps/powerpc/fpu/fesetexcept.c
@@ -31,6 +31,11 @@ fesetexcept (int excepts)
& FE_INVALID_SOFTWARE));
if (n.l != u.l)
{
+ if (n.l & fenv_exceptions_to_reg (excepts))
+ /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4
+ does not allow it. */
+ return -1;
+
fesetenv_register (n.fenv);
/* Deal with FE_INVALID_SOFTWARE not being implemented on some chips.
*/
diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c
b/sysdeps/powerpc/fpu/fsetexcptflg.c
index 2b22f913c0..6517e8ea03 100644
--- a/sysdeps/powerpc/fpu/fsetexcptflg.c
+++ b/sysdeps/powerpc/fpu/fsetexcptflg.c
@@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts)
This may cause floating-point exceptions if the restored state
requests it. */
if (n.l != u.l)
- fesetenv_register (n.fenv);
+ {
+ if (n.l & fenv_exceptions_to_reg (excepts))
+ /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4
+ does not allow it. */
+ return -1;
+
+ fesetenv_register (n.fenv);
+ }
/* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */
if (flag & FE_INVALID)
--
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* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
` (3 preceding siblings ...)
2023-10-23 14:51 ` adhemerval.zanella at linaro dot org
@ 2023-10-23 15:05 ` bruno at clisp dot org
2023-12-19 18:36 ` adhemerval.zanella at linaro dot org
5 siblings, 0 replies; 7+ messages in thread
From: bruno at clisp dot org @ 2023-10-23 15:05 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
--- Comment #5 from Bruno Haible <bruno at clisp dot org> ---
(In reply to Adhemerval Zanella from comment #4)
> The fesetexceptflag has the same issue
Indeed, for fesetexceptflag ISO C § 7.6.4.5 has the same requirement.
Your patches look good.
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* [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le
2023-10-22 22:31 [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le bruno at clisp dot org
` (4 preceding siblings ...)
2023-10-23 15:05 ` bruno at clisp dot org
@ 2023-12-19 18:36 ` adhemerval.zanella at linaro dot org
5 siblings, 0 replies; 7+ messages in thread
From: adhemerval.zanella at linaro dot org @ 2023-12-19 18:36 UTC (permalink / raw)
To: glibc-bugs
https://sourceware.org/bugzilla/show_bug.cgi?id=30988
Adhemerval Zanella <adhemerval.zanella at linaro dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|unassigned at sourceware dot org |adhemerval.zanella at linaro dot o
| |rg
Target Milestone|--- |2.39
Status|UNCONFIRMED |RESOLVED
Resolution|--- |FIXED
--- Comment #6 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
Fixed on 2.39 (ecb1e7220ddc7a4845bbd1b6fd7fcf17aba566bd).
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