Re: [patch, mips] Improved memset for MIPS

[Andrew Pinski <pinskia@gmail.com>]

On Thu, Dec 12, 2013 at 4:14 PM, Steve Ellcey <sellcey@mips.com> wrote:
> On Thu, 2013-12-12 at 19:01 -0500, Carlos O'Donell wrote:
>
>> > I noticed this patch causes some performance regressions on Octeon due
>> > to having 128 byte cache lines.
>> > Changing PREFETCH_CHUNK/PREFETCH_FOR_STORE to assume 128 byte cache
>> > line gives us the performance back and improves over the original code
>> > at least 15%.
>> > That is:
>> > #  define PREFETCH_CHUNK 128
>> > #  define PREFETCH_FOR_STORE(chunk, reg) \
>> >     pref PREFETCH_STORE_HINT, (chunk)*128(reg);
>>
>> Submit a patch for that?
>>
>> We have microbenchmarks now, but the next hardest
>> part is going to be archiving data by device so that
>> the community can help track performance and point
>> out regressions like this.
>>
>> Cheers,
>> Carlos.
>
> Unless the change is under some kind of ifdef for Octeon changing this
> will probably slow down other MIPS chips.  Most of them have 32 byte
> cache lines.

I think once ifunc support has been finalized, it would be useful to
build memset optimized for Octeon but until then I think it might be
best to disable the prefetching in the generic mips code.

Thanks,
Andrew Pinski


>
> Steve Ellcey
> sellcey@mips.com
>
>