From: Dmitry Selyutin <ghostmansd@gmail.com>
To: binutils@sourceware.org
Cc: Alan Modra <amodra@gmail.com>,
Luke Kenneth Casson Leighton <luke.leighton@gmail.com>,
Dmitry Selyutin <ghostmansd@gmail.com>
Subject: [PATCH v2 2/5] ppc/svp64: support setvl instructions
Date: Tue, 21 Jun 2022 14:51:12 +0300 [thread overview]
Message-ID: <20220621115115.1068453-3-ghostmansd@gmail.com> (raw)
In-Reply-To: <20220621115115.1068453-1-ghostmansd@gmail.com>
---
gas/testsuite/gas/ppc/ppc.exp | 2 +
gas/testsuite/gas/ppc/setvl.d | 2408 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/ppc/setvl.s | 2400 ++++++++++++++++++++++++++++++++
opcodes/ppc-opc.c | 42 +
4 files changed, 4852 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/setvl.d
create mode 100644 gas/testsuite/gas/ppc/setvl.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6a..cd4dd658ce 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 0000000000..46c6d9bbc0
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,2408 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+ 0: 36 00 00 58 setvl r0,r0,1,0,0,0
+ 4: 36 01 00 58 setvl r0,r0,1,0,0,1
+ 8: b6 00 00 58 setvl r0,r0,1,0,1,0
+ c: b6 01 00 58 setvl r0,r0,1,0,1,1
+ 10: 76 00 00 58 setvl r0,r0,1,1,0,0
+ 14: 76 01 00 58 setvl r0,r0,1,1,0,1
+ 18: f6 00 00 58 setvl r0,r0,1,1,1,0
+ 1c: f6 01 00 58 setvl r0,r0,1,1,1,1
+ 20: 36 28 00 58 setvl r0,r0,21,0,0,0
+ 24: 36 29 00 58 setvl r0,r0,21,0,0,1
+ 28: b6 28 00 58 setvl r0,r0,21,0,1,0
+ 2c: b6 29 00 58 setvl r0,r0,21,0,1,1
+ 30: 76 28 00 58 setvl r0,r0,21,1,0,0
+ 34: 76 29 00 58 setvl r0,r0,21,1,0,1
+ 38: f6 28 00 58 setvl r0,r0,21,1,1,0
+ 3c: f6 29 00 58 setvl r0,r0,21,1,1,1
+ 40: 36 52 00 58 setvl r0,r0,42,0,0,0
+ 44: 36 53 00 58 setvl r0,r0,42,0,0,1
+ 48: b6 52 00 58 setvl r0,r0,42,0,1,0
+ 4c: b6 53 00 58 setvl r0,r0,42,0,1,1
+ 50: 76 52 00 58 setvl r0,r0,42,1,0,0
+ 54: 76 53 00 58 setvl r0,r0,42,1,0,1
+ 58: f6 52 00 58 setvl r0,r0,42,1,1,0
+ 5c: f6 53 00 58 setvl r0,r0,42,1,1,1
+ 60: 36 64 00 58 setvl r0,r0,51,0,0,0
+ 64: 36 65 00 58 setvl r0,r0,51,0,0,1
+ 68: b6 64 00 58 setvl r0,r0,51,0,1,0
+ 6c: b6 65 00 58 setvl r0,r0,51,0,1,1
+ 70: 76 64 00 58 setvl r0,r0,51,1,0,0
+ 74: 76 65 00 58 setvl r0,r0,51,1,0,1
+ 78: f6 64 00 58 setvl r0,r0,51,1,1,0
+ 7c: f6 65 00 58 setvl r0,r0,51,1,1,1
+ 80: 36 7c 00 58 setvl r0,r0,63,0,0,0
+ 84: 36 7d 00 58 setvl r0,r0,63,0,0,1
+ 88: b6 7c 00 58 setvl r0,r0,63,0,1,0
+ 8c: b6 7d 00 58 setvl r0,r0,63,0,1,1
+ 90: 76 7c 00 58 setvl r0,r0,63,1,0,0
+ 94: 76 7d 00 58 setvl r0,r0,63,1,0,1
+ 98: f6 7c 00 58 setvl r0,r0,63,1,1,0
+ 9c: f6 7d 00 58 setvl r0,r0,63,1,1,1
+ a0: 36 3e 00 58 setvl r0,r0,32,0,0,0
+ a4: 36 3f 00 58 setvl r0,r0,32,0,0,1
+ a8: b6 3e 00 58 setvl r0,r0,32,0,1,0
+ ac: b6 3f 00 58 setvl r0,r0,32,0,1,1
+ b0: 76 3e 00 58 setvl r0,r0,32,1,0,0
+ b4: 76 3f 00 58 setvl r0,r0,32,1,0,1
+ b8: f6 3e 00 58 setvl r0,r0,32,1,1,0
+ bc: f6 3f 00 58 setvl r0,r0,32,1,1,1
+ c0: 36 00 0a 58 setvl r0,r10,1,0,0,0
+ c4: 36 01 0a 58 setvl r0,r10,1,0,0,1
+ c8: b6 00 0a 58 setvl r0,r10,1,0,1,0
+ cc: b6 01 0a 58 setvl r0,r10,1,0,1,1
+ d0: 76 00 0a 58 setvl r0,r10,1,1,0,0
+ d4: 76 01 0a 58 setvl r0,r10,1,1,0,1
+ d8: f6 00 0a 58 setvl r0,r10,1,1,1,0
+ dc: f6 01 0a 58 setvl r0,r10,1,1,1,1
+ e0: 36 28 0a 58 setvl r0,r10,21,0,0,0
+ e4: 36 29 0a 58 setvl r0,r10,21,0,0,1
+ e8: b6 28 0a 58 setvl r0,r10,21,0,1,0
+ ec: b6 29 0a 58 setvl r0,r10,21,0,1,1
+ f0: 76 28 0a 58 setvl r0,r10,21,1,0,0
+ f4: 76 29 0a 58 setvl r0,r10,21,1,0,1
+ f8: f6 28 0a 58 setvl r0,r10,21,1,1,0
+ fc: f6 29 0a 58 setvl r0,r10,21,1,1,1
+ 100: 36 52 0a 58 setvl r0,r10,42,0,0,0
+ 104: 36 53 0a 58 setvl r0,r10,42,0,0,1
+ 108: b6 52 0a 58 setvl r0,r10,42,0,1,0
+ 10c: b6 53 0a 58 setvl r0,r10,42,0,1,1
+ 110: 76 52 0a 58 setvl r0,r10,42,1,0,0
+ 114: 76 53 0a 58 setvl r0,r10,42,1,0,1
+ 118: f6 52 0a 58 setvl r0,r10,42,1,1,0
+ 11c: f6 53 0a 58 setvl r0,r10,42,1,1,1
+ 120: 36 64 0a 58 setvl r0,r10,51,0,0,0
+ 124: 36 65 0a 58 setvl r0,r10,51,0,0,1
+ 128: b6 64 0a 58 setvl r0,r10,51,0,1,0
+ 12c: b6 65 0a 58 setvl r0,r10,51,0,1,1
+ 130: 76 64 0a 58 setvl r0,r10,51,1,0,0
+ 134: 76 65 0a 58 setvl r0,r10,51,1,0,1
+ 138: f6 64 0a 58 setvl r0,r10,51,1,1,0
+ 13c: f6 65 0a 58 setvl r0,r10,51,1,1,1
+ 140: 36 7c 0a 58 setvl r0,r10,63,0,0,0
+ 144: 36 7d 0a 58 setvl r0,r10,63,0,0,1
+ 148: b6 7c 0a 58 setvl r0,r10,63,0,1,0
+ 14c: b6 7d 0a 58 setvl r0,r10,63,0,1,1
+ 150: 76 7c 0a 58 setvl r0,r10,63,1,0,0
+ 154: 76 7d 0a 58 setvl r0,r10,63,1,0,1
+ 158: f6 7c 0a 58 setvl r0,r10,63,1,1,0
+ 15c: f6 7d 0a 58 setvl r0,r10,63,1,1,1
+ 160: 36 3e 0a 58 setvl r0,r10,32,0,0,0
+ 164: 36 3f 0a 58 setvl r0,r10,32,0,0,1
+ 168: b6 3e 0a 58 setvl r0,r10,32,0,1,0
+ 16c: b6 3f 0a 58 setvl r0,r10,32,0,1,1
+ 170: 76 3e 0a 58 setvl r0,r10,32,1,0,0
+ 174: 76 3f 0a 58 setvl r0,r10,32,1,0,1
+ 178: f6 3e 0a 58 setvl r0,r10,32,1,1,0
+ 17c: f6 3f 0a 58 setvl r0,r10,32,1,1,1
+ 180: 36 00 15 58 setvl r0,r21,1,0,0,0
+ 184: 36 01 15 58 setvl r0,r21,1,0,0,1
+ 188: b6 00 15 58 setvl r0,r21,1,0,1,0
+ 18c: b6 01 15 58 setvl r0,r21,1,0,1,1
+ 190: 76 00 15 58 setvl r0,r21,1,1,0,0
+ 194: 76 01 15 58 setvl r0,r21,1,1,0,1
+ 198: f6 00 15 58 setvl r0,r21,1,1,1,0
+ 19c: f6 01 15 58 setvl r0,r21,1,1,1,1
+ 1a0: 36 28 15 58 setvl r0,r21,21,0,0,0
+ 1a4: 36 29 15 58 setvl r0,r21,21,0,0,1
+ 1a8: b6 28 15 58 setvl r0,r21,21,0,1,0
+ 1ac: b6 29 15 58 setvl r0,r21,21,0,1,1
+ 1b0: 76 28 15 58 setvl r0,r21,21,1,0,0
+ 1b4: 76 29 15 58 setvl r0,r21,21,1,0,1
+ 1b8: f6 28 15 58 setvl r0,r21,21,1,1,0
+ 1bc: f6 29 15 58 setvl r0,r21,21,1,1,1
+ 1c0: 36 52 15 58 setvl r0,r21,42,0,0,0
+ 1c4: 36 53 15 58 setvl r0,r21,42,0,0,1
+ 1c8: b6 52 15 58 setvl r0,r21,42,0,1,0
+ 1cc: b6 53 15 58 setvl r0,r21,42,0,1,1
+ 1d0: 76 52 15 58 setvl r0,r21,42,1,0,0
+ 1d4: 76 53 15 58 setvl r0,r21,42,1,0,1
+ 1d8: f6 52 15 58 setvl r0,r21,42,1,1,0
+ 1dc: f6 53 15 58 setvl r0,r21,42,1,1,1
+ 1e0: 36 64 15 58 setvl r0,r21,51,0,0,0
+ 1e4: 36 65 15 58 setvl r0,r21,51,0,0,1
+ 1e8: b6 64 15 58 setvl r0,r21,51,0,1,0
+ 1ec: b6 65 15 58 setvl r0,r21,51,0,1,1
+ 1f0: 76 64 15 58 setvl r0,r21,51,1,0,0
+ 1f4: 76 65 15 58 setvl r0,r21,51,1,0,1
+ 1f8: f6 64 15 58 setvl r0,r21,51,1,1,0
+ 1fc: f6 65 15 58 setvl r0,r21,51,1,1,1
+ 200: 36 7c 15 58 setvl r0,r21,63,0,0,0
+ 204: 36 7d 15 58 setvl r0,r21,63,0,0,1
+ 208: b6 7c 15 58 setvl r0,r21,63,0,1,0
+ 20c: b6 7d 15 58 setvl r0,r21,63,0,1,1
+ 210: 76 7c 15 58 setvl r0,r21,63,1,0,0
+ 214: 76 7d 15 58 setvl r0,r21,63,1,0,1
+ 218: f6 7c 15 58 setvl r0,r21,63,1,1,0
+ 21c: f6 7d 15 58 setvl r0,r21,63,1,1,1
+ 220: 36 3e 15 58 setvl r0,r21,32,0,0,0
+ 224: 36 3f 15 58 setvl r0,r21,32,0,0,1
+ 228: b6 3e 15 58 setvl r0,r21,32,0,1,0
+ 22c: b6 3f 15 58 setvl r0,r21,32,0,1,1
+ 230: 76 3e 15 58 setvl r0,r21,32,1,0,0
+ 234: 76 3f 15 58 setvl r0,r21,32,1,0,1
+ 238: f6 3e 15 58 setvl r0,r21,32,1,1,0
+ 23c: f6 3f 15 58 setvl r0,r21,32,1,1,1
+ 240: 36 00 1b 58 setvl r0,r27,1,0,0,0
+ 244: 36 01 1b 58 setvl r0,r27,1,0,0,1
+ 248: b6 00 1b 58 setvl r0,r27,1,0,1,0
+ 24c: b6 01 1b 58 setvl r0,r27,1,0,1,1
+ 250: 76 00 1b 58 setvl r0,r27,1,1,0,0
+ 254: 76 01 1b 58 setvl r0,r27,1,1,0,1
+ 258: f6 00 1b 58 setvl r0,r27,1,1,1,0
+ 25c: f6 01 1b 58 setvl r0,r27,1,1,1,1
+ 260: 36 28 1b 58 setvl r0,r27,21,0,0,0
+ 264: 36 29 1b 58 setvl r0,r27,21,0,0,1
+ 268: b6 28 1b 58 setvl r0,r27,21,0,1,0
+ 26c: b6 29 1b 58 setvl r0,r27,21,0,1,1
+ 270: 76 28 1b 58 setvl r0,r27,21,1,0,0
+ 274: 76 29 1b 58 setvl r0,r27,21,1,0,1
+ 278: f6 28 1b 58 setvl r0,r27,21,1,1,0
+ 27c: f6 29 1b 58 setvl r0,r27,21,1,1,1
+ 280: 36 52 1b 58 setvl r0,r27,42,0,0,0
+ 284: 36 53 1b 58 setvl r0,r27,42,0,0,1
+ 288: b6 52 1b 58 setvl r0,r27,42,0,1,0
+ 28c: b6 53 1b 58 setvl r0,r27,42,0,1,1
+ 290: 76 52 1b 58 setvl r0,r27,42,1,0,0
+ 294: 76 53 1b 58 setvl r0,r27,42,1,0,1
+ 298: f6 52 1b 58 setvl r0,r27,42,1,1,0
+ 29c: f6 53 1b 58 setvl r0,r27,42,1,1,1
+ 2a0: 36 64 1b 58 setvl r0,r27,51,0,0,0
+ 2a4: 36 65 1b 58 setvl r0,r27,51,0,0,1
+ 2a8: b6 64 1b 58 setvl r0,r27,51,0,1,0
+ 2ac: b6 65 1b 58 setvl r0,r27,51,0,1,1
+ 2b0: 76 64 1b 58 setvl r0,r27,51,1,0,0
+ 2b4: 76 65 1b 58 setvl r0,r27,51,1,0,1
+ 2b8: f6 64 1b 58 setvl r0,r27,51,1,1,0
+ 2bc: f6 65 1b 58 setvl r0,r27,51,1,1,1
+ 2c0: 36 7c 1b 58 setvl r0,r27,63,0,0,0
+ 2c4: 36 7d 1b 58 setvl r0,r27,63,0,0,1
+ 2c8: b6 7c 1b 58 setvl r0,r27,63,0,1,0
+ 2cc: b6 7d 1b 58 setvl r0,r27,63,0,1,1
+ 2d0: 76 7c 1b 58 setvl r0,r27,63,1,0,0
+ 2d4: 76 7d 1b 58 setvl r0,r27,63,1,0,1
+ 2d8: f6 7c 1b 58 setvl r0,r27,63,1,1,0
+ 2dc: f6 7d 1b 58 setvl r0,r27,63,1,1,1
+ 2e0: 36 3e 1b 58 setvl r0,r27,32,0,0,0
+ 2e4: 36 3f 1b 58 setvl r0,r27,32,0,0,1
+ 2e8: b6 3e 1b 58 setvl r0,r27,32,0,1,0
+ 2ec: b6 3f 1b 58 setvl r0,r27,32,0,1,1
+ 2f0: 76 3e 1b 58 setvl r0,r27,32,1,0,0
+ 2f4: 76 3f 1b 58 setvl r0,r27,32,1,0,1
+ 2f8: f6 3e 1b 58 setvl r0,r27,32,1,1,0
+ 2fc: f6 3f 1b 58 setvl r0,r27,32,1,1,1
+ 300: 36 00 1f 58 setvl r0,r31,1,0,0,0
+ 304: 36 01 1f 58 setvl r0,r31,1,0,0,1
+ 308: b6 00 1f 58 setvl r0,r31,1,0,1,0
+ 30c: b6 01 1f 58 setvl r0,r31,1,0,1,1
+ 310: 76 00 1f 58 setvl r0,r31,1,1,0,0
+ 314: 76 01 1f 58 setvl r0,r31,1,1,0,1
+ 318: f6 00 1f 58 setvl r0,r31,1,1,1,0
+ 31c: f6 01 1f 58 setvl r0,r31,1,1,1,1
+ 320: 36 28 1f 58 setvl r0,r31,21,0,0,0
+ 324: 36 29 1f 58 setvl r0,r31,21,0,0,1
+ 328: b6 28 1f 58 setvl r0,r31,21,0,1,0
+ 32c: b6 29 1f 58 setvl r0,r31,21,0,1,1
+ 330: 76 28 1f 58 setvl r0,r31,21,1,0,0
+ 334: 76 29 1f 58 setvl r0,r31,21,1,0,1
+ 338: f6 28 1f 58 setvl r0,r31,21,1,1,0
+ 33c: f6 29 1f 58 setvl r0,r31,21,1,1,1
+ 340: 36 52 1f 58 setvl r0,r31,42,0,0,0
+ 344: 36 53 1f 58 setvl r0,r31,42,0,0,1
+ 348: b6 52 1f 58 setvl r0,r31,42,0,1,0
+ 34c: b6 53 1f 58 setvl r0,r31,42,0,1,1
+ 350: 76 52 1f 58 setvl r0,r31,42,1,0,0
+ 354: 76 53 1f 58 setvl r0,r31,42,1,0,1
+ 358: f6 52 1f 58 setvl r0,r31,42,1,1,0
+ 35c: f6 53 1f 58 setvl r0,r31,42,1,1,1
+ 360: 36 64 1f 58 setvl r0,r31,51,0,0,0
+ 364: 36 65 1f 58 setvl r0,r31,51,0,0,1
+ 368: b6 64 1f 58 setvl r0,r31,51,0,1,0
+ 36c: b6 65 1f 58 setvl r0,r31,51,0,1,1
+ 370: 76 64 1f 58 setvl r0,r31,51,1,0,0
+ 374: 76 65 1f 58 setvl r0,r31,51,1,0,1
+ 378: f6 64 1f 58 setvl r0,r31,51,1,1,0
+ 37c: f6 65 1f 58 setvl r0,r31,51,1,1,1
+ 380: 36 7c 1f 58 setvl r0,r31,63,0,0,0
+ 384: 36 7d 1f 58 setvl r0,r31,63,0,0,1
+ 388: b6 7c 1f 58 setvl r0,r31,63,0,1,0
+ 38c: b6 7d 1f 58 setvl r0,r31,63,0,1,1
+ 390: 76 7c 1f 58 setvl r0,r31,63,1,0,0
+ 394: 76 7d 1f 58 setvl r0,r31,63,1,0,1
+ 398: f6 7c 1f 58 setvl r0,r31,63,1,1,0
+ 39c: f6 7d 1f 58 setvl r0,r31,63,1,1,1
+ 3a0: 36 3e 1f 58 setvl r0,r31,32,0,0,0
+ 3a4: 36 3f 1f 58 setvl r0,r31,32,0,0,1
+ 3a8: b6 3e 1f 58 setvl r0,r31,32,0,1,0
+ 3ac: b6 3f 1f 58 setvl r0,r31,32,0,1,1
+ 3b0: 76 3e 1f 58 setvl r0,r31,32,1,0,0
+ 3b4: 76 3f 1f 58 setvl r0,r31,32,1,0,1
+ 3b8: f6 3e 1f 58 setvl r0,r31,32,1,1,0
+ 3bc: f6 3f 1f 58 setvl r0,r31,32,1,1,1
+ 3c0: 36 00 40 59 setvl r10,r0,1,0,0,0
+ 3c4: 36 01 40 59 setvl r10,r0,1,0,0,1
+ 3c8: b6 00 40 59 setvl r10,r0,1,0,1,0
+ 3cc: b6 01 40 59 setvl r10,r0,1,0,1,1
+ 3d0: 76 00 40 59 setvl r10,r0,1,1,0,0
+ 3d4: 76 01 40 59 setvl r10,r0,1,1,0,1
+ 3d8: f6 00 40 59 setvl r10,r0,1,1,1,0
+ 3dc: f6 01 40 59 setvl r10,r0,1,1,1,1
+ 3e0: 36 28 40 59 setvl r10,r0,21,0,0,0
+ 3e4: 36 29 40 59 setvl r10,r0,21,0,0,1
+ 3e8: b6 28 40 59 setvl r10,r0,21,0,1,0
+ 3ec: b6 29 40 59 setvl r10,r0,21,0,1,1
+ 3f0: 76 28 40 59 setvl r10,r0,21,1,0,0
+ 3f4: 76 29 40 59 setvl r10,r0,21,1,0,1
+ 3f8: f6 28 40 59 setvl r10,r0,21,1,1,0
+ 3fc: f6 29 40 59 setvl r10,r0,21,1,1,1
+ 400: 36 52 40 59 setvl r10,r0,42,0,0,0
+ 404: 36 53 40 59 setvl r10,r0,42,0,0,1
+ 408: b6 52 40 59 setvl r10,r0,42,0,1,0
+ 40c: b6 53 40 59 setvl r10,r0,42,0,1,1
+ 410: 76 52 40 59 setvl r10,r0,42,1,0,0
+ 414: 76 53 40 59 setvl r10,r0,42,1,0,1
+ 418: f6 52 40 59 setvl r10,r0,42,1,1,0
+ 41c: f6 53 40 59 setvl r10,r0,42,1,1,1
+ 420: 36 64 40 59 setvl r10,r0,51,0,0,0
+ 424: 36 65 40 59 setvl r10,r0,51,0,0,1
+ 428: b6 64 40 59 setvl r10,r0,51,0,1,0
+ 42c: b6 65 40 59 setvl r10,r0,51,0,1,1
+ 430: 76 64 40 59 setvl r10,r0,51,1,0,0
+ 434: 76 65 40 59 setvl r10,r0,51,1,0,1
+ 438: f6 64 40 59 setvl r10,r0,51,1,1,0
+ 43c: f6 65 40 59 setvl r10,r0,51,1,1,1
+ 440: 36 7c 40 59 setvl r10,r0,63,0,0,0
+ 444: 36 7d 40 59 setvl r10,r0,63,0,0,1
+ 448: b6 7c 40 59 setvl r10,r0,63,0,1,0
+ 44c: b6 7d 40 59 setvl r10,r0,63,0,1,1
+ 450: 76 7c 40 59 setvl r10,r0,63,1,0,0
+ 454: 76 7d 40 59 setvl r10,r0,63,1,0,1
+ 458: f6 7c 40 59 setvl r10,r0,63,1,1,0
+ 45c: f6 7d 40 59 setvl r10,r0,63,1,1,1
+ 460: 36 3e 40 59 setvl r10,r0,32,0,0,0
+ 464: 36 3f 40 59 setvl r10,r0,32,0,0,1
+ 468: b6 3e 40 59 setvl r10,r0,32,0,1,0
+ 46c: b6 3f 40 59 setvl r10,r0,32,0,1,1
+ 470: 76 3e 40 59 setvl r10,r0,32,1,0,0
+ 474: 76 3f 40 59 setvl r10,r0,32,1,0,1
+ 478: f6 3e 40 59 setvl r10,r0,32,1,1,0
+ 47c: f6 3f 40 59 setvl r10,r0,32,1,1,1
+ 480: 36 00 4a 59 setvl r10,r10,1,0,0,0
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+ 125c: f6 53 ff 5b setvl r31,r31,42,1,1,1
+ 1260: 36 64 ff 5b setvl r31,r31,51,0,0,0
+ 1264: 36 65 ff 5b setvl r31,r31,51,0,0,1
+ 1268: b6 64 ff 5b setvl r31,r31,51,0,1,0
+ 126c: b6 65 ff 5b setvl r31,r31,51,0,1,1
+ 1270: 76 64 ff 5b setvl r31,r31,51,1,0,0
+ 1274: 76 65 ff 5b setvl r31,r31,51,1,0,1
+ 1278: f6 64 ff 5b setvl r31,r31,51,1,1,0
+ 127c: f6 65 ff 5b setvl r31,r31,51,1,1,1
+ 1280: 36 7c ff 5b setvl r31,r31,63,0,0,0
+ 1284: 36 7d ff 5b setvl r31,r31,63,0,0,1
+ 1288: b6 7c ff 5b setvl r31,r31,63,0,1,0
+ 128c: b6 7d ff 5b setvl r31,r31,63,0,1,1
+ 1290: 76 7c ff 5b setvl r31,r31,63,1,0,0
+ 1294: 76 7d ff 5b setvl r31,r31,63,1,0,1
+ 1298: f6 7c ff 5b setvl r31,r31,63,1,1,0
+ 129c: f6 7d ff 5b setvl r31,r31,63,1,1,1
+ 12a0: 36 3e ff 5b setvl r31,r31,32,0,0,0
+ 12a4: 36 3f ff 5b setvl r31,r31,32,0,0,1
+ 12a8: b6 3e ff 5b setvl r31,r31,32,0,1,0
+ 12ac: b6 3f ff 5b setvl r31,r31,32,0,1,1
+ 12b0: 76 3e ff 5b setvl r31,r31,32,1,0,0
+ 12b4: 76 3f ff 5b setvl r31,r31,32,1,0,1
+ 12b8: f6 3e ff 5b setvl r31,r31,32,1,1,0
+ 12bc: f6 3f ff 5b setvl r31,r31,32,1,1,1
+ 12c0: 37 00 00 58 setvl\. r0,r0,1,0,0,0
+ 12c4: 37 01 00 58 setvl\. r0,r0,1,0,0,1
+ 12c8: b7 00 00 58 setvl\. r0,r0,1,0,1,0
+ 12cc: b7 01 00 58 setvl\. r0,r0,1,0,1,1
+ 12d0: 77 00 00 58 setvl\. r0,r0,1,1,0,0
+ 12d4: 77 01 00 58 setvl\. r0,r0,1,1,0,1
+ 12d8: f7 00 00 58 setvl\. r0,r0,1,1,1,0
+ 12dc: f7 01 00 58 setvl\. r0,r0,1,1,1,1
+ 12e0: 37 28 00 58 setvl\. r0,r0,21,0,0,0
+ 12e4: 37 29 00 58 setvl\. r0,r0,21,0,0,1
+ 12e8: b7 28 00 58 setvl\. r0,r0,21,0,1,0
+ 12ec: b7 29 00 58 setvl\. r0,r0,21,0,1,1
+ 12f0: 77 28 00 58 setvl\. r0,r0,21,1,0,0
+ 12f4: 77 29 00 58 setvl\. r0,r0,21,1,0,1
+ 12f8: f7 28 00 58 setvl\. r0,r0,21,1,1,0
+ 12fc: f7 29 00 58 setvl\. r0,r0,21,1,1,1
+ 1300: 37 52 00 58 setvl\. r0,r0,42,0,0,0
+ 1304: 37 53 00 58 setvl\. r0,r0,42,0,0,1
+ 1308: b7 52 00 58 setvl\. r0,r0,42,0,1,0
+ 130c: b7 53 00 58 setvl\. r0,r0,42,0,1,1
+ 1310: 77 52 00 58 setvl\. r0,r0,42,1,0,0
+ 1314: 77 53 00 58 setvl\. r0,r0,42,1,0,1
+ 1318: f7 52 00 58 setvl\. r0,r0,42,1,1,0
+ 131c: f7 53 00 58 setvl\. r0,r0,42,1,1,1
+ 1320: 37 64 00 58 setvl\. r0,r0,51,0,0,0
+ 1324: 37 65 00 58 setvl\. r0,r0,51,0,0,1
+ 1328: b7 64 00 58 setvl\. r0,r0,51,0,1,0
+ 132c: b7 65 00 58 setvl\. r0,r0,51,0,1,1
+ 1330: 77 64 00 58 setvl\. r0,r0,51,1,0,0
+ 1334: 77 65 00 58 setvl\. r0,r0,51,1,0,1
+ 1338: f7 64 00 58 setvl\. r0,r0,51,1,1,0
+ 133c: f7 65 00 58 setvl\. r0,r0,51,1,1,1
+ 1340: 37 7c 00 58 setvl\. r0,r0,63,0,0,0
+ 1344: 37 7d 00 58 setvl\. r0,r0,63,0,0,1
+ 1348: b7 7c 00 58 setvl\. r0,r0,63,0,1,0
+ 134c: b7 7d 00 58 setvl\. r0,r0,63,0,1,1
+ 1350: 77 7c 00 58 setvl\. r0,r0,63,1,0,0
+ 1354: 77 7d 00 58 setvl\. r0,r0,63,1,0,1
+ 1358: f7 7c 00 58 setvl\. r0,r0,63,1,1,0
+ 135c: f7 7d 00 58 setvl\. r0,r0,63,1,1,1
+ 1360: 37 3e 00 58 setvl\. r0,r0,32,0,0,0
+ 1364: 37 3f 00 58 setvl\. r0,r0,32,0,0,1
+ 1368: b7 3e 00 58 setvl\. r0,r0,32,0,1,0
+ 136c: b7 3f 00 58 setvl\. r0,r0,32,0,1,1
+ 1370: 77 3e 00 58 setvl\. r0,r0,32,1,0,0
+ 1374: 77 3f 00 58 setvl\. r0,r0,32,1,0,1
+ 1378: f7 3e 00 58 setvl\. r0,r0,32,1,1,0
+ 137c: f7 3f 00 58 setvl\. r0,r0,32,1,1,1
+ 1380: 37 00 0a 58 setvl\. r0,r10,1,0,0,0
+ 1384: 37 01 0a 58 setvl\. r0,r10,1,0,0,1
+ 1388: b7 00 0a 58 setvl\. r0,r10,1,0,1,0
+ 138c: b7 01 0a 58 setvl\. r0,r10,1,0,1,1
+ 1390: 77 00 0a 58 setvl\. r0,r10,1,1,0,0
+ 1394: 77 01 0a 58 setvl\. r0,r10,1,1,0,1
+ 1398: f7 00 0a 58 setvl\. r0,r10,1,1,1,0
+ 139c: f7 01 0a 58 setvl\. r0,r10,1,1,1,1
+ 13a0: 37 28 0a 58 setvl\. r0,r10,21,0,0,0
+ 13a4: 37 29 0a 58 setvl\. r0,r10,21,0,0,1
+ 13a8: b7 28 0a 58 setvl\. r0,r10,21,0,1,0
+ 13ac: b7 29 0a 58 setvl\. r0,r10,21,0,1,1
+ 13b0: 77 28 0a 58 setvl\. r0,r10,21,1,0,0
+ 13b4: 77 29 0a 58 setvl\. r0,r10,21,1,0,1
+ 13b8: f7 28 0a 58 setvl\. r0,r10,21,1,1,0
+ 13bc: f7 29 0a 58 setvl\. r0,r10,21,1,1,1
+ 13c0: 37 52 0a 58 setvl\. r0,r10,42,0,0,0
+ 13c4: 37 53 0a 58 setvl\. r0,r10,42,0,0,1
+ 13c8: b7 52 0a 58 setvl\. r0,r10,42,0,1,0
+ 13cc: b7 53 0a 58 setvl\. r0,r10,42,0,1,1
+ 13d0: 77 52 0a 58 setvl\. r0,r10,42,1,0,0
+ 13d4: 77 53 0a 58 setvl\. r0,r10,42,1,0,1
+ 13d8: f7 52 0a 58 setvl\. r0,r10,42,1,1,0
+ 13dc: f7 53 0a 58 setvl\. r0,r10,42,1,1,1
+ 13e0: 37 64 0a 58 setvl\. r0,r10,51,0,0,0
+ 13e4: 37 65 0a 58 setvl\. r0,r10,51,0,0,1
+ 13e8: b7 64 0a 58 setvl\. r0,r10,51,0,1,0
+ 13ec: b7 65 0a 58 setvl\. r0,r10,51,0,1,1
+ 13f0: 77 64 0a 58 setvl\. r0,r10,51,1,0,0
+ 13f4: 77 65 0a 58 setvl\. r0,r10,51,1,0,1
+ 13f8: f7 64 0a 58 setvl\. r0,r10,51,1,1,0
+ 13fc: f7 65 0a 58 setvl\. r0,r10,51,1,1,1
+ 1400: 37 7c 0a 58 setvl\. r0,r10,63,0,0,0
+ 1404: 37 7d 0a 58 setvl\. r0,r10,63,0,0,1
+ 1408: b7 7c 0a 58 setvl\. r0,r10,63,0,1,0
+ 140c: b7 7d 0a 58 setvl\. r0,r10,63,0,1,1
+ 1410: 77 7c 0a 58 setvl\. r0,r10,63,1,0,0
+ 1414: 77 7d 0a 58 setvl\. r0,r10,63,1,0,1
+ 1418: f7 7c 0a 58 setvl\. r0,r10,63,1,1,0
+ 141c: f7 7d 0a 58 setvl\. r0,r10,63,1,1,1
+ 1420: 37 3e 0a 58 setvl\. r0,r10,32,0,0,0
+ 1424: 37 3f 0a 58 setvl\. r0,r10,32,0,0,1
+ 1428: b7 3e 0a 58 setvl\. r0,r10,32,0,1,0
+ 142c: b7 3f 0a 58 setvl\. r0,r10,32,0,1,1
+ 1430: 77 3e 0a 58 setvl\. r0,r10,32,1,0,0
+ 1434: 77 3f 0a 58 setvl\. r0,r10,32,1,0,1
+ 1438: f7 3e 0a 58 setvl\. r0,r10,32,1,1,0
+ 143c: f7 3f 0a 58 setvl\. r0,r10,32,1,1,1
+ 1440: 37 00 15 58 setvl\. r0,r21,1,0,0,0
+ 1444: 37 01 15 58 setvl\. r0,r21,1,0,0,1
+ 1448: b7 00 15 58 setvl\. r0,r21,1,0,1,0
+ 144c: b7 01 15 58 setvl\. r0,r21,1,0,1,1
+ 1450: 77 00 15 58 setvl\. r0,r21,1,1,0,0
+ 1454: 77 01 15 58 setvl\. r0,r21,1,1,0,1
+ 1458: f7 00 15 58 setvl\. r0,r21,1,1,1,0
+ 145c: f7 01 15 58 setvl\. r0,r21,1,1,1,1
+ 1460: 37 28 15 58 setvl\. r0,r21,21,0,0,0
+ 1464: 37 29 15 58 setvl\. r0,r21,21,0,0,1
+ 1468: b7 28 15 58 setvl\. r0,r21,21,0,1,0
+ 146c: b7 29 15 58 setvl\. r0,r21,21,0,1,1
+ 1470: 77 28 15 58 setvl\. r0,r21,21,1,0,0
+ 1474: 77 29 15 58 setvl\. r0,r21,21,1,0,1
+ 1478: f7 28 15 58 setvl\. r0,r21,21,1,1,0
+ 147c: f7 29 15 58 setvl\. r0,r21,21,1,1,1
+ 1480: 37 52 15 58 setvl\. r0,r21,42,0,0,0
+ 1484: 37 53 15 58 setvl\. r0,r21,42,0,0,1
+ 1488: b7 52 15 58 setvl\. r0,r21,42,0,1,0
+ 148c: b7 53 15 58 setvl\. r0,r21,42,0,1,1
+ 1490: 77 52 15 58 setvl\. r0,r21,42,1,0,0
+ 1494: 77 53 15 58 setvl\. r0,r21,42,1,0,1
+ 1498: f7 52 15 58 setvl\. r0,r21,42,1,1,0
+ 149c: f7 53 15 58 setvl\. r0,r21,42,1,1,1
+ 14a0: 37 64 15 58 setvl\. r0,r21,51,0,0,0
+ 14a4: 37 65 15 58 setvl\. r0,r21,51,0,0,1
+ 14a8: b7 64 15 58 setvl\. r0,r21,51,0,1,0
+ 14ac: b7 65 15 58 setvl\. r0,r21,51,0,1,1
+ 14b0: 77 64 15 58 setvl\. r0,r21,51,1,0,0
+ 14b4: 77 65 15 58 setvl\. r0,r21,51,1,0,1
+ 14b8: f7 64 15 58 setvl\. r0,r21,51,1,1,0
+ 14bc: f7 65 15 58 setvl\. r0,r21,51,1,1,1
+ 14c0: 37 7c 15 58 setvl\. r0,r21,63,0,0,0
+ 14c4: 37 7d 15 58 setvl\. r0,r21,63,0,0,1
+ 14c8: b7 7c 15 58 setvl\. r0,r21,63,0,1,0
+ 14cc: b7 7d 15 58 setvl\. r0,r21,63,0,1,1
+ 14d0: 77 7c 15 58 setvl\. r0,r21,63,1,0,0
+ 14d4: 77 7d 15 58 setvl\. r0,r21,63,1,0,1
+ 14d8: f7 7c 15 58 setvl\. r0,r21,63,1,1,0
+ 14dc: f7 7d 15 58 setvl\. r0,r21,63,1,1,1
+ 14e0: 37 3e 15 58 setvl\. r0,r21,32,0,0,0
+ 14e4: 37 3f 15 58 setvl\. r0,r21,32,0,0,1
+ 14e8: b7 3e 15 58 setvl\. r0,r21,32,0,1,0
+ 14ec: b7 3f 15 58 setvl\. r0,r21,32,0,1,1
+ 14f0: 77 3e 15 58 setvl\. r0,r21,32,1,0,0
+ 14f4: 77 3f 15 58 setvl\. r0,r21,32,1,0,1
+ 14f8: f7 3e 15 58 setvl\. r0,r21,32,1,1,0
+ 14fc: f7 3f 15 58 setvl\. r0,r21,32,1,1,1
+ 1500: 37 00 1b 58 setvl\. r0,r27,1,0,0,0
+ 1504: 37 01 1b 58 setvl\. r0,r27,1,0,0,1
+ 1508: b7 00 1b 58 setvl\. r0,r27,1,0,1,0
+ 150c: b7 01 1b 58 setvl\. r0,r27,1,0,1,1
+ 1510: 77 00 1b 58 setvl\. r0,r27,1,1,0,0
+ 1514: 77 01 1b 58 setvl\. r0,r27,1,1,0,1
+ 1518: f7 00 1b 58 setvl\. r0,r27,1,1,1,0
+ 151c: f7 01 1b 58 setvl\. r0,r27,1,1,1,1
+ 1520: 37 28 1b 58 setvl\. r0,r27,21,0,0,0
+ 1524: 37 29 1b 58 setvl\. r0,r27,21,0,0,1
+ 1528: b7 28 1b 58 setvl\. r0,r27,21,0,1,0
+ 152c: b7 29 1b 58 setvl\. r0,r27,21,0,1,1
+ 1530: 77 28 1b 58 setvl\. r0,r27,21,1,0,0
+ 1534: 77 29 1b 58 setvl\. r0,r27,21,1,0,1
+ 1538: f7 28 1b 58 setvl\. r0,r27,21,1,1,0
+ 153c: f7 29 1b 58 setvl\. r0,r27,21,1,1,1
+ 1540: 37 52 1b 58 setvl\. r0,r27,42,0,0,0
+ 1544: 37 53 1b 58 setvl\. r0,r27,42,0,0,1
+ 1548: b7 52 1b 58 setvl\. r0,r27,42,0,1,0
+ 154c: b7 53 1b 58 setvl\. r0,r27,42,0,1,1
+ 1550: 77 52 1b 58 setvl\. r0,r27,42,1,0,0
+ 1554: 77 53 1b 58 setvl\. r0,r27,42,1,0,1
+ 1558: f7 52 1b 58 setvl\. r0,r27,42,1,1,0
+ 155c: f7 53 1b 58 setvl\. r0,r27,42,1,1,1
+ 1560: 37 64 1b 58 setvl\. r0,r27,51,0,0,0
+ 1564: 37 65 1b 58 setvl\. r0,r27,51,0,0,1
+ 1568: b7 64 1b 58 setvl\. r0,r27,51,0,1,0
+ 156c: b7 65 1b 58 setvl\. r0,r27,51,0,1,1
+ 1570: 77 64 1b 58 setvl\. r0,r27,51,1,0,0
+ 1574: 77 65 1b 58 setvl\. r0,r27,51,1,0,1
+ 1578: f7 64 1b 58 setvl\. r0,r27,51,1,1,0
+ 157c: f7 65 1b 58 setvl\. r0,r27,51,1,1,1
+ 1580: 37 7c 1b 58 setvl\. r0,r27,63,0,0,0
+ 1584: 37 7d 1b 58 setvl\. r0,r27,63,0,0,1
+ 1588: b7 7c 1b 58 setvl\. r0,r27,63,0,1,0
+ 158c: b7 7d 1b 58 setvl\. r0,r27,63,0,1,1
+ 1590: 77 7c 1b 58 setvl\. r0,r27,63,1,0,0
+ 1594: 77 7d 1b 58 setvl\. r0,r27,63,1,0,1
+ 1598: f7 7c 1b 58 setvl\. r0,r27,63,1,1,0
+ 159c: f7 7d 1b 58 setvl\. r0,r27,63,1,1,1
+ 15a0: 37 3e 1b 58 setvl\. r0,r27,32,0,0,0
+ 15a4: 37 3f 1b 58 setvl\. r0,r27,32,0,0,1
+ 15a8: b7 3e 1b 58 setvl\. r0,r27,32,0,1,0
+ 15ac: b7 3f 1b 58 setvl\. r0,r27,32,0,1,1
+ 15b0: 77 3e 1b 58 setvl\. r0,r27,32,1,0,0
+ 15b4: 77 3f 1b 58 setvl\. r0,r27,32,1,0,1
+ 15b8: f7 3e 1b 58 setvl\. r0,r27,32,1,1,0
+ 15bc: f7 3f 1b 58 setvl\. r0,r27,32,1,1,1
+ 15c0: 37 00 1f 58 setvl\. r0,r31,1,0,0,0
+ 15c4: 37 01 1f 58 setvl\. r0,r31,1,0,0,1
+ 15c8: b7 00 1f 58 setvl\. r0,r31,1,0,1,0
+ 15cc: b7 01 1f 58 setvl\. r0,r31,1,0,1,1
+ 15d0: 77 00 1f 58 setvl\. r0,r31,1,1,0,0
+ 15d4: 77 01 1f 58 setvl\. r0,r31,1,1,0,1
+ 15d8: f7 00 1f 58 setvl\. r0,r31,1,1,1,0
+ 15dc: f7 01 1f 58 setvl\. r0,r31,1,1,1,1
+ 15e0: 37 28 1f 58 setvl\. r0,r31,21,0,0,0
+ 15e4: 37 29 1f 58 setvl\. r0,r31,21,0,0,1
+ 15e8: b7 28 1f 58 setvl\. r0,r31,21,0,1,0
+ 15ec: b7 29 1f 58 setvl\. r0,r31,21,0,1,1
+ 15f0: 77 28 1f 58 setvl\. r0,r31,21,1,0,0
+ 15f4: 77 29 1f 58 setvl\. r0,r31,21,1,0,1
+ 15f8: f7 28 1f 58 setvl\. r0,r31,21,1,1,0
+ 15fc: f7 29 1f 58 setvl\. r0,r31,21,1,1,1
+ 1600: 37 52 1f 58 setvl\. r0,r31,42,0,0,0
+ 1604: 37 53 1f 58 setvl\. r0,r31,42,0,0,1
+ 1608: b7 52 1f 58 setvl\. r0,r31,42,0,1,0
+ 160c: b7 53 1f 58 setvl\. r0,r31,42,0,1,1
+ 1610: 77 52 1f 58 setvl\. r0,r31,42,1,0,0
+ 1614: 77 53 1f 58 setvl\. r0,r31,42,1,0,1
+ 1618: f7 52 1f 58 setvl\. r0,r31,42,1,1,0
+ 161c: f7 53 1f 58 setvl\. r0,r31,42,1,1,1
+ 1620: 37 64 1f 58 setvl\. r0,r31,51,0,0,0
+ 1624: 37 65 1f 58 setvl\. r0,r31,51,0,0,1
+ 1628: b7 64 1f 58 setvl\. r0,r31,51,0,1,0
+ 162c: b7 65 1f 58 setvl\. r0,r31,51,0,1,1
+ 1630: 77 64 1f 58 setvl\. r0,r31,51,1,0,0
+ 1634: 77 65 1f 58 setvl\. r0,r31,51,1,0,1
+ 1638: f7 64 1f 58 setvl\. r0,r31,51,1,1,0
+ 163c: f7 65 1f 58 setvl\. r0,r31,51,1,1,1
+ 1640: 37 7c 1f 58 setvl\. r0,r31,63,0,0,0
+ 1644: 37 7d 1f 58 setvl\. r0,r31,63,0,0,1
+ 1648: b7 7c 1f 58 setvl\. r0,r31,63,0,1,0
+ 164c: b7 7d 1f 58 setvl\. r0,r31,63,0,1,1
+ 1650: 77 7c 1f 58 setvl\. r0,r31,63,1,0,0
+ 1654: 77 7d 1f 58 setvl\. r0,r31,63,1,0,1
+ 1658: f7 7c 1f 58 setvl\. r0,r31,63,1,1,0
+ 165c: f7 7d 1f 58 setvl\. r0,r31,63,1,1,1
+ 1660: 37 3e 1f 58 setvl\. r0,r31,32,0,0,0
+ 1664: 37 3f 1f 58 setvl\. r0,r31,32,0,0,1
+ 1668: b7 3e 1f 58 setvl\. r0,r31,32,0,1,0
+ 166c: b7 3f 1f 58 setvl\. r0,r31,32,0,1,1
+ 1670: 77 3e 1f 58 setvl\. r0,r31,32,1,0,0
+ 1674: 77 3f 1f 58 setvl\. r0,r31,32,1,0,1
+ 1678: f7 3e 1f 58 setvl\. r0,r31,32,1,1,0
+ 167c: f7 3f 1f 58 setvl\. r0,r31,32,1,1,1
+ 1680: 37 00 40 59 setvl\. r10,r0,1,0,0,0
+ 1684: 37 01 40 59 setvl\. r10,r0,1,0,0,1
+ 1688: b7 00 40 59 setvl\. r10,r0,1,0,1,0
+ 168c: b7 01 40 59 setvl\. r10,r0,1,0,1,1
+ 1690: 77 00 40 59 setvl\. r10,r0,1,1,0,0
+ 1694: 77 01 40 59 setvl\. r10,r0,1,1,0,1
+ 1698: f7 00 40 59 setvl\. r10,r0,1,1,1,0
+ 169c: f7 01 40 59 setvl\. r10,r0,1,1,1,1
+ 16a0: 37 28 40 59 setvl\. r10,r0,21,0,0,0
+ 16a4: 37 29 40 59 setvl\. r10,r0,21,0,0,1
+ 16a8: b7 28 40 59 setvl\. r10,r0,21,0,1,0
+ 16ac: b7 29 40 59 setvl\. r10,r0,21,0,1,1
+ 16b0: 77 28 40 59 setvl\. r10,r0,21,1,0,0
+ 16b4: 77 29 40 59 setvl\. r10,r0,21,1,0,1
+ 16b8: f7 28 40 59 setvl\. r10,r0,21,1,1,0
+ 16bc: f7 29 40 59 setvl\. r10,r0,21,1,1,1
+ 16c0: 37 52 40 59 setvl\. r10,r0,42,0,0,0
+ 16c4: 37 53 40 59 setvl\. r10,r0,42,0,0,1
+ 16c8: b7 52 40 59 setvl\. r10,r0,42,0,1,0
+ 16cc: b7 53 40 59 setvl\. r10,r0,42,0,1,1
+ 16d0: 77 52 40 59 setvl\. r10,r0,42,1,0,0
+ 16d4: 77 53 40 59 setvl\. r10,r0,42,1,0,1
+ 16d8: f7 52 40 59 setvl\. r10,r0,42,1,1,0
+ 16dc: f7 53 40 59 setvl\. r10,r0,42,1,1,1
+ 16e0: 37 64 40 59 setvl\. r10,r0,51,0,0,0
+ 16e4: 37 65 40 59 setvl\. r10,r0,51,0,0,1
+ 16e8: b7 64 40 59 setvl\. r10,r0,51,0,1,0
+ 16ec: b7 65 40 59 setvl\. r10,r0,51,0,1,1
+ 16f0: 77 64 40 59 setvl\. r10,r0,51,1,0,0
+ 16f4: 77 65 40 59 setvl\. r10,r0,51,1,0,1
+ 16f8: f7 64 40 59 setvl\. r10,r0,51,1,1,0
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+ 2428: b7 28 fb 5b setvl\. r31,r27,21,0,1,0
+ 242c: b7 29 fb 5b setvl\. r31,r27,21,0,1,1
+ 2430: 77 28 fb 5b setvl\. r31,r27,21,1,0,0
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+ 2438: f7 28 fb 5b setvl\. r31,r27,21,1,1,0
+ 243c: f7 29 fb 5b setvl\. r31,r27,21,1,1,1
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+ 244c: b7 53 fb 5b setvl\. r31,r27,42,0,1,1
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+ 2458: f7 52 fb 5b setvl\. r31,r27,42,1,1,0
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+ 2470: 77 64 fb 5b setvl\. r31,r27,51,1,0,0
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+ 2498: f7 7c fb 5b setvl\. r31,r27,63,1,1,0
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+ 24c8: b7 00 ff 5b setvl\. r31,r31,1,0,1,0
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+ 24d8: f7 00 ff 5b setvl\. r31,r31,1,1,1,0
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+ 24f8: f7 28 ff 5b setvl\. r31,r31,21,1,1,0
+ 24fc: f7 29 ff 5b setvl\. r31,r31,21,1,1,1
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+ 2504: 37 53 ff 5b setvl\. r31,r31,42,0,0,1
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+ 2528: b7 64 ff 5b setvl\. r31,r31,51,0,1,0
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+ 253c: f7 65 ff 5b setvl\. r31,r31,51,1,1,1
+ 2540: 37 7c ff 5b setvl\. r31,r31,63,0,0,0
+ 2544: 37 7d ff 5b setvl\. r31,r31,63,0,0,1
+ 2548: b7 7c ff 5b setvl\. r31,r31,63,0,1,0
+ 254c: b7 7d ff 5b setvl\. r31,r31,63,0,1,1
+ 2550: 77 7c ff 5b setvl\. r31,r31,63,1,0,0
+ 2554: 77 7d ff 5b setvl\. r31,r31,63,1,0,1
+ 2558: f7 7c ff 5b setvl\. r31,r31,63,1,1,0
+ 255c: f7 7d ff 5b setvl\. r31,r31,63,1,1,1
+ 2560: 37 3e ff 5b setvl\. r31,r31,32,0,0,0
+ 2564: 37 3f ff 5b setvl\. r31,r31,32,0,0,1
+ 2568: b7 3e ff 5b setvl\. r31,r31,32,0,1,0
+ 256c: b7 3f ff 5b setvl\. r31,r31,32,0,1,1
+ 2570: 77 3e ff 5b setvl\. r31,r31,32,1,0,0
+ 2574: 77 3f ff 5b setvl\. r31,r31,32,1,0,1
+ 2578: f7 3e ff 5b setvl\. r31,r31,32,1,1,0
+ 257c: f7 3f ff 5b setvl\. r31,r31,32,1,1,1
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 0000000000..944f8afc08
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,2400 @@
+setvl 0,0,1,0,0,0
+setvl 0,0,1,0,0,1
+setvl 0,0,1,0,1,0
+setvl 0,0,1,0,1,1
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+setvl. 31,27,21,0,1,1
+setvl. 31,27,21,1,0,0
+setvl. 31,27,21,1,0,1
+setvl. 31,27,21,1,1,0
+setvl. 31,27,21,1,1,1
+setvl. 31,27,42,0,0,0
+setvl. 31,27,42,0,0,1
+setvl. 31,27,42,0,1,0
+setvl. 31,27,42,0,1,1
+setvl. 31,27,42,1,0,0
+setvl. 31,27,42,1,0,1
+setvl. 31,27,42,1,1,0
+setvl. 31,27,42,1,1,1
+setvl. 31,27,51,0,0,0
+setvl. 31,27,51,0,0,1
+setvl. 31,27,51,0,1,0
+setvl. 31,27,51,0,1,1
+setvl. 31,27,51,1,0,0
+setvl. 31,27,51,1,0,1
+setvl. 31,27,51,1,1,0
+setvl. 31,27,51,1,1,1
+setvl. 31,27,63,0,0,0
+setvl. 31,27,63,0,0,1
+setvl. 31,27,63,0,1,0
+setvl. 31,27,63,0,1,1
+setvl. 31,27,63,1,0,0
+setvl. 31,27,63,1,0,1
+setvl. 31,27,63,1,1,0
+setvl. 31,27,63,1,1,1
+setvl. 31,27,32,0,0,0
+setvl. 31,27,32,0,0,1
+setvl. 31,27,32,0,1,0
+setvl. 31,27,32,0,1,1
+setvl. 31,27,32,1,0,0
+setvl. 31,27,32,1,0,1
+setvl. 31,27,32,1,1,0
+setvl. 31,27,32,1,1,1
+setvl. 31,31,1,0,0,0
+setvl. 31,31,1,0,0,1
+setvl. 31,31,1,0,1,0
+setvl. 31,31,1,0,1,1
+setvl. 31,31,1,1,0,0
+setvl. 31,31,1,1,0,1
+setvl. 31,31,1,1,1,0
+setvl. 31,31,1,1,1,1
+setvl. 31,31,21,0,0,0
+setvl. 31,31,21,0,0,1
+setvl. 31,31,21,0,1,0
+setvl. 31,31,21,0,1,1
+setvl. 31,31,21,1,0,0
+setvl. 31,31,21,1,0,1
+setvl. 31,31,21,1,1,0
+setvl. 31,31,21,1,1,1
+setvl. 31,31,42,0,0,0
+setvl. 31,31,42,0,0,1
+setvl. 31,31,42,0,1,0
+setvl. 31,31,42,0,1,1
+setvl. 31,31,42,1,0,0
+setvl. 31,31,42,1,0,1
+setvl. 31,31,42,1,1,0
+setvl. 31,31,42,1,1,1
+setvl. 31,31,51,0,0,0
+setvl. 31,31,51,0,0,1
+setvl. 31,31,51,0,1,0
+setvl. 31,31,51,0,1,1
+setvl. 31,31,51,1,0,0
+setvl. 31,31,51,1,0,1
+setvl. 31,31,51,1,1,0
+setvl. 31,31,51,1,1,1
+setvl. 31,31,63,0,0,0
+setvl. 31,31,63,0,0,1
+setvl. 31,31,63,0,1,0
+setvl. 31,31,63,0,1,1
+setvl. 31,31,63,1,0,0
+setvl. 31,31,63,1,0,1
+setvl. 31,31,63,1,1,0
+setvl. 31,31,63,1,1,1
+setvl. 31,31,32,0,0,0
+setvl. 31,31,32,0,0,1
+setvl. 31,31,32,0,1,0
+setvl. 31,31,32,0,1,1
+setvl. 31,31,32,1,0,0
+setvl. 31,31,32,1,0,1
+setvl. 31,31,32,1,1,0
+setvl. 31,31,32,1,1,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d..0a34417820 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,26 @@ extract_thds (uint64_t insn,
return value;
}
+
+static uint64_t
+insert_svi (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value <= 0)
+ *errmsg = _("invalid SVi field");
+ return (insn | (((value - 1) & 0x3f) << 9));
+}
+
+static int64_t
+extract_svi (uint64_t insn ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 9) & 0x3f) + 1);
+}
+
\f
/* The operands table.
@@ -3825,6 +3845,18 @@ const struct powerpc_operand powerpc_operands[] =
#define HH DDD + 1
{ 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+ { 0x3f, 9, insert_svi, extract_svi, 0 },
+
+#define vf SVi + 1
+ { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+ { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+ { 0x1, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4726,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define APU_RT_MASK (APU_MASK | RT_MASK)
#define APU_RA_MASK (APU_MASK | RA_MASK)
+/* An SVL form instruction. */
+#define SVL(op, xop, rc) \
+ (OP (op) \
+ | ((((uint64_t)(xop)) & 0x1f) << 1) \
+ | (((uint64_t)(rc)) & 1))
+#define SVL_MASK SVL (0x3f, 0x1f, 1)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6763,6 +6802,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
+{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
next prev parent reply other threads:[~2022-06-21 11:53 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` Dmitry Selyutin [this message]
2022-06-21 18:25 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Peter Bergner
2022-06-21 18:39 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
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