From: Dmitry Selyutin <ghostmansd@gmail.com>
To: binutils@sourceware.org
Cc: Alan Modra <amodra@gmail.com>,
Luke Leighton <luke.leighton@gmail.com>,
Jan Beulich <jbeulich@suse.com>,
Nick Alcock <nick.alcock@oracle.com>,
Richard Earnshaw <Richard.Earnshaw@foss.arm.com>,
Andreas Schwab <schwab@linux-m68k.org>,
Dmitry Selyutin <ghostmansd@gmail.com>
Subject: [PATCH v5 7/7] ppc/svp64: support svindex instruction
Date: Sun, 26 Jun 2022 22:00:05 +0300 [thread overview]
Message-ID: <20220626190005.7727-8-ghostmansd@gmail.com> (raw)
In-Reply-To: <20220626190005.7727-1-ghostmansd@gmail.com>
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svindex
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svindex.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svindex.s | 8 ++++++++
opcodes/ppc-opc.c | 14 ++++++++++++++
4 files changed, 39 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svindex.d
create mode 100644 gas/testsuite/gas/ppc/svindex.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a182cc81d7..12b4c9dac0 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -158,3 +158,4 @@ run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
run_dump_test "svremap"
+run_dump_test "svindex"
diff --git a/gas/testsuite/gas/ppc/svindex.d b/gas/testsuite/gas/ppc/svindex.d
new file mode 100644
index 0000000000..73bda73287
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (29 00 00 58|58 00 00 29) svindex r0,0,1,0,0,0,0
+.*: (29 00 e0 5b|5b e0 00 29) svindex r31,0,1,0,0,0,0
+.*: (29 00 1f 58|58 1f 00 29) svindex r0,31,1,0,0,0,0
+.*: (29 f8 00 58|58 00 f8 29) svindex r0,0,32,0,0,0,0
+.*: (29 06 00 58|58 00 06 29) svindex r0,0,1,3,0,0,0
+.*: (29 01 00 58|58 00 01 29) svindex r0,0,1,0,1,0,0
+.*: (a9 00 00 58|58 00 00 a9) svindex r0,0,1,0,0,1,0
+.*: (69 00 00 58|58 00 00 69) svindex r0,0,1,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svindex.s b/gas/testsuite/gas/ppc/svindex.s
new file mode 100644
index 0000000000..ab256c433b
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.s
@@ -0,0 +1,8 @@
+svindex 0,0,1,0,0,0,0
+svindex 31,0,1,0,0,0,0
+svindex 0,31,1,0,0,0,0
+svindex 0,0,32,0,0,0,0
+svindex 0,0,1,3,0,0,0
+svindex 0,0,1,0,1,0,0
+svindex 0,0,1,0,0,1,0
+svindex 0,0,1,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 8e56f88a6c..84b7d90c22 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3557,6 +3557,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
#define DCTL UIMM
+#define rmm UIMM
{ 0x1f, 16, NULL, NULL, 0 },
/* The 3-bit UIMM field in a VX form instruction. */
@@ -3649,6 +3650,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RMC or CY field in a Z23 form instruction. */
#define RMC A_L + 1
#define CY RMC
+#define ew RMC
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
@@ -3837,12 +3839,15 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
#define vf SVi + 1
+#define sk vf
{ 0x1, 6, NULL, NULL, 0 },
#define vs vf + 1
+#define mm vs
{ 0x1, 7, NULL, NULL, 0 },
#define ms vs + 1
+#define yx ms
{ 0x1, 8, NULL, NULL, 0 },
#define SVLcr ms + 1
@@ -3855,6 +3860,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVzd SVyd + 1
+#define SVd SVzd
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
#define SVrm SVzd + 1
@@ -4753,6 +4759,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVRM_MASK SVRM (0x3f, 0x3f)
+/* An SVI form instruction. */
+#define SVI(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVI_MASK SVI (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6830,6 +6842,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svindex", SVI(22,41), SVI_MASK, SVP64, PPCVLE, {RS, rmm, SVd, ew, yx, mm, sk}},
+
{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
--
2.36.1
next prev parent reply other threads:[~2022-06-26 19:00 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-21 18:25 ` Peter Bergner
2022-06-21 18:39 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 19:00 ` Dmitry Selyutin [this message]
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
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