From: Dmitry Selyutin <ghostmansd@gmail.com>
To: binutils@sourceware.org
Cc: Alan Modra <amodra@gmail.com>,
Luke Kenneth Casson Leighton <luke.leighton@gmail.com>,
Dmitry Selyutin <ghostmansd@gmail.com>
Subject: [PATCH v4 2/6] ppc: introduce non-zero operand flag
Date: Thu, 23 Jun 2022 23:08:34 +0300 [thread overview]
Message-ID: <20220623200838.1247734-3-ghostmansd@gmail.com> (raw)
In-Reply-To: <20220623200838.1247734-1-ghostmansd@gmail.com>
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
---
gas/config/tc-ppc.c | 22 +++++++++++++++++++---
include/opcode/ppc.h | 7 +++++++
opcodes/ppc-dis.c | 3 +++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 76bdfb2e35..c048721ed0 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1643,10 +1643,16 @@ ppc_setup_opcodes (void)
all the 1's in the mask are contiguous. */
for (i = 0; i < num_powerpc_operands; ++i)
{
+
uint64_t mask = powerpc_operands[i].bitm;
+ unsigned long flags = powerpc_operands[i].flags;
uint64_t right_bit;
unsigned int j;
+ if ((flags & (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO)) ==
+ (PPC_OPERAND_PLUS1 | PPC_OPERAND_NONZERO))
+ as_bad ("mutually exclusive operand flags");
+
right_bit = mask & -mask;
mask += right_bit;
right_bit = mask & -mask;
@@ -1968,6 +1974,11 @@ ppc_insert_operand (uint64_t insn,
max = (max >> 1) & -right;
min = ~max & -right;
}
+ else if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ {
+ ++min;
+ ++max;
+ }
if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
max++;
@@ -2018,10 +2029,15 @@ ppc_insert_operand (uint64_t insn,
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
- else if (operand->shift >= 0)
- insn |= (val & operand->bitm) << operand->shift;
else
- insn |= (val & operand->bitm) >> -operand->shift;
+ {
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ --val;
+ if (operand->shift >= 0)
+ insn |= (val & operand->bitm) << operand->shift;
+ else
+ insn |= (val & operand->bitm) >> -operand->shift;
+ }
return insn;
}
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index d5752a42e6..df06671db4 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -463,6 +463,13 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_FCR (0x1000000)
#define PPC_OPERAND_UDI (0x2000000)
+/*
+ * Valid range of operand is 1..n rather than 0..n-1.
+ * Before encoding, the operand value is decremented.
+ * After decoding. the operand value is incremented.
+ */
+#define PPC_OPERAND_NONZERO 0x4000000
+
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
static inline int64_t
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index f61e6518f1..d5b23c8a75 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -545,6 +545,9 @@ operand_value_powerpc (const struct powerpc_operand *operand,
}
}
+ if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
+ ++value;
+
return value;
}
--
2.36.1
next prev parent reply other threads:[~2022-06-23 20:08 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-21 18:25 ` Peter Bergner
2022-06-21 18:39 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` Dmitry Selyutin [this message]
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
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