Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions

[lkcl <luke.leighton@gmail.com>]

On Mon, Aug 15, 2022 at 7:18 AM Jan Beulich <jbeulich@suse.com> wrote:

> On 25.07.2022 15:10, Dmitry Selyutin via Binutils wrote:
> > +Disassembly of section \.text:
> > +0+ <\.text>:
> > +.*:  (37 00 00 58|58 00 00 37)       setvl.  r0,r0,1,0,0,0
> Out of curiosity - was it intentional to omit a case with the last
> operand non-zero?

one for Dmitry - i believe these are all auto-generated?

> > @@ -6769,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> > +{"setvl",    SVL(22,27,0),   SVL_MASK,       SVP64,  PPCVLE, {RT, RA, SVi, vf, vs, ms}},
> > +{"setvl.",   SVL(22,27,1),   SVL_MASK,       SVP64,  PPCVLE, {RT, RA, SVi, vf, vs, ms}},

> According to the web page SETVL has a number of pseudos.

yes.

> I guess you've omitted those for simplicity in the initial submission.

and because there's a python-based (very-easy-to-hack) program
which does the same job as gas, turning SVP64 assembler into
".long xxx; v3.0opcode", and it doesn't have pseudo-ops.

> I'd like to point out though that the web page isn't really
> crystal clear as to, in particular, the Rc field's applicability
> to every one of the pseudos.

ah appreciated, i've added examples.  more will be needed now that
there's also setvl-from-CTR as well.

> (There's also a typo or two which
> makes things a little ambiguous, but there it's reasonably clear
> what is actually meant.)

appreciated.  any feedback is more than welcome.  context there:
despite now being an Open ISA the amount of attention Power is
getting is surprisingly low.  hence any assistance and feedback
is all the more precious.

l.