Re: [PATCH v6 3/7] ppc/svp64: support setvl instructions

[Jan Beulich <jbeulich@suse.com>]

On 25.07.2022 15:10, Dmitry Selyutin via Binutils wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/ppc/setvl.d
> @@ -0,0 +1,15 @@
> +#as: -mlibresoc
> +#objdump: -dr -Mlibresoc
> +
> +.*:     file format .*
> +
> +
> +Disassembly of section \.text:
> +0+ <\.text>:
> +.*:	(37 00 00 58|58 00 00 37) 	setvl.  r0,r0,1,0,0,0
> +.*:	(36 00 00 58|58 00 00 36) 	setvl   r0,r0,1,0,0,0
> +.*:	(36 00 e0 5b|5b e0 00 36) 	setvl   r31,r0,1,0,0,0
> +.*:	(36 00 1f 58|58 1f 00 36) 	setvl   r0,r31,1,0,0,0
> +.*:	(36 7e 00 58|58 00 7e 36) 	setvl   r0,r0,64,0,0,0
> +.*:	(76 00 00 58|58 00 00 76) 	setvl   r0,r0,1,1,0,0
> +.*:	(b6 00 00 58|58 00 00 b6) 	setvl   r0,r0,1,0,1,0

Out of curiosity - was it intentional to omit a case with the last
operand non-zero?

> @@ -6769,6 +6789,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"rlmi",	M(22,0),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
>  {"rlmi.",	M(22,1),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
>  
> +{"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
> +{"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
> +
>  {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
>  {"rlwnm",	M(23,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
>  {"rlnm",	M(23,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},

According to the web page SETVL has a number of pseudos. I guess
you've omitted those for simplicity in the initial submission.

I'd like to point out though that the web page isn't really
crystal clear as to, in particular, the Rc field's applicability
to every one of the pseudos. (There's also a typo or two which
makes things a little ambiguous, but there it's reasonably clear
what is actually meant.)

Jan