From: Dmitry Selyutin <ghostmansd@gmail.com>
To: binutils@sourceware.org
Cc: Alan Modra <amodra@gmail.com>,
Luke Kenneth Casson Leighton <luke.leighton@gmail.com>,
Dmitry Selyutin <ghostmansd@gmail.com>
Subject: [PATCH v3 6/6] ppc/svp64: support svremap instruction
Date: Thu, 23 Jun 2022 22:37:34 +0300 [thread overview]
Message-ID: <20220623193734.1245650-7-ghostmansd@gmail.com> (raw)
In-Reply-To: <20220623193734.1245650-1-ghostmansd@gmail.com>
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/
https://libre-soc.org/openpower/isa/simplev/
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/svremap.d | 16 ++++++++++++++++
gas/testsuite/gas/ppc/svremap.s | 8 ++++++++
opcodes/ppc-opc.c | 20 ++++++++++++++++++++
4 files changed, 45 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/svremap.d
create mode 100644 gas/testsuite/gas/ppc/svremap.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 04082439bb..a182cc81d7 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -157,3 +157,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
+run_dump_test "svremap"
diff --git a/gas/testsuite/gas/ppc/svremap.d b/gas/testsuite/gas/ppc/svremap.d
new file mode 100644
index 0000000000..18646ec37d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
+.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
+.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
+.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
+.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
+.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
+.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
+.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svremap.s b/gas/testsuite/gas/ppc/svremap.s
new file mode 100644
index 0000000000..860040afc5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svremap.s
@@ -0,0 +1,8 @@
+svremap 0,0,0,0,0,0,0
+svremap 31,0,0,0,0,0,0
+svremap 0,3,0,0,0,0,0
+svremap 0,0,3,0,0,0,0
+svremap 0,0,0,3,0,0,0
+svremap 0,0,0,0,3,0,0
+svremap 0,0,0,0,0,3,0
+svremap 0,3,0,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 33797fcab5..4e98c56f35 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2850,6 +2850,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
+#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@@ -3508,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
+#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -3621,6 +3623,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
+ /* The pst field in a SVRM form instruction. */
+#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -3658,6 +3662,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@@ -3825,6 +3830,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
+#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@@ -3853,6 +3859,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVRMf SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
+
+#define mi1 SVRMf + 1
+ { 0x3, 17, NULL, NULL, 0 },
+
+#define mi2 mi1 + 1
+ { 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4735,6 +4747,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
+/* An SVRM form instruction. */
+#define SVRM(op, xop) \
+ (OP (op) \
+ | (((uint64_t)(xop)) & 0x3f))
+#define SVRM_MASK SVRM (0x3f, 0x3f)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -6811,6 +6829,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
+{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
--
2.36.1
next prev parent reply other threads:[~2022-06-23 19:37 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 19:08 [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 1/5] svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-17 19:08 ` [PATCH 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-19 23:49 ` [PATCH 0/5] ppc/svp64: support SVP64 and its first insns Alan Modra
2022-06-21 11:55 ` Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 " Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 1/5] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 2/5] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-21 18:25 ` Peter Bergner
2022-06-21 18:39 ` Peter Bergner
2022-06-21 11:51 ` [PATCH v2 3/5] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-21 11:51 ` [PATCH v2 4/5] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-22 6:41 ` [PATCH v2 0/5] ppc/svp64: support SVP64 and its first insns Jan Beulich
2022-06-22 6:44 ` Jan Beulich
2022-06-22 6:57 ` Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 0/6] " Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 2/6] ppc: introduce non-zero operand Dmitry Selyutin
2022-06-23 19:58 ` lkcl
2022-06-23 19:37 ` [PATCH v3 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 19:37 ` [PATCH v3 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 19:37 ` Dmitry Selyutin [this message]
2022-06-23 19:45 ` [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:10 ` Dmitry Selyutin
2022-06-24 11:38 ` Draft Simple-V roadmap for Power ISA (was: [PATCH v3 0/6] ppc/svp64: support SVP64 and its first insns) lkcl
2022-06-23 20:08 ` [PATCH v4 0/6] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 1/6] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 2/6] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 3/6] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 4/6] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 5/6] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-23 20:08 ` [PATCH v4 6/6] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-06-26 18:59 ` [PATCH v5 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-06-26 19:00 ` [PATCH v5 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 1/7] ppc/svp64: support LibreSOC architecture Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 2/7] ppc: introduce non-zero operand flag Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 3/7] ppc/svp64: support setvl instructions Dmitry Selyutin
2022-08-15 6:18 ` Jan Beulich
2022-08-15 12:58 ` lkcl
2022-08-15 13:08 ` Dmitry Selyutin
2022-08-21 14:53 ` Jan Beulich
2022-08-21 16:04 ` lkcl
2022-07-25 13:10 ` [PATCH v6 4/7] ppc/svp64: support svstep instructions Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 5/7] ppc/svp64: support svshape instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 6/7] ppc/svp64: support svremap instruction Dmitry Selyutin
2022-07-25 13:10 ` [PATCH v6 7/7] ppc/svp64: support svindex instruction Dmitry Selyutin
2022-07-26 13:14 ` [PATCH v6 0/7] ppc/svp64: support SVP64 and its first insns Dmitry Selyutin
2022-07-27 4:53 ` Alan Modra
2022-07-27 6:38 ` lkcl
2022-08-11 9:14 ` Alan Modra
2022-08-11 10:48 ` [PATCH 0/5] " lkcl
2022-08-12 3:30 ` [PATCH v6 0/7] " Dmitry Selyutin
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