* [PATCH 01/10] Support Intel AVX-IFMA
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, wwwhhhyyy
From: wwwhhhyyy <hongyu.wang@intel.com>
x86: Support Intel AVX-IFMA
Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions
are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX
encoding for Intel IFMA instructions.
gas/
* NEWS: Support Intel AVX-IFMA.
* config/tc-i386.c (cpu_arch): Add avx_ifma.
* doc/c-i386.texi: Document .avx_ifma and how to
encode Intel IFMA instructions with VEX prefix.
* testsuite/gas/i386/avx-ifma.d: New file.
* testsuite/gas/i386/avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/avx-ifma.s: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-ifma.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX IFMA tests.
opcodes/
* i386-dis.c (PREFIX_VEX_0F38B4): New.
(PREFIX_VEX_0F38B5): Likewise.
(VEX_W_0F38B4_P_2): Likewise.
(VEX_W_0F38B5_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5.
(vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and
CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX_IFMA.
* i386-opc.h (CpuAVX_IFMA): New.
(i386_cpu_flags): Add cpuavx_ifma.
* i386-opc.tbl: Add Intel AVX IFMA instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 6 +-
gas/testsuite/gas/i386/avx-ifma-intel.d | 30 +
gas/testsuite/gas/i386/avx-ifma-inval.l | 2 +
gas/testsuite/gas/i386/avx-ifma-inval.s | 6 +
gas/testsuite/gas/i386/avx-ifma.d | 30 +
gas/testsuite/gas/i386/avx-ifma.s | 21 +
gas/testsuite/gas/i386/i386.exp | 6 +
gas/testsuite/gas/i386/noavx512-1.l | 24 +-
.../gas/i386/x86-64-avx-ifma-intel.d | 34 +
.../gas/i386/x86-64-avx-ifma-inval.l | 3 +
.../gas/i386/x86-64-avx-ifma-inval.s | 7 +
gas/testsuite/gas/i386/x86-64-avx-ifma.d | 34 +
gas/testsuite/gas/i386/x86-64-avx-ifma.s | 23 +
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 522 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7808 +++++++++--------
21 files changed, 4436 insertions(+), 4156 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/avx-ifma.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ifma.s
diff --git a/gas/NEWS b/gas/NEWS
index 16cb347e77..7cf65728ba 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AVX-IFMA instructions.
+
* gas now supports --compress-debug-sections=zstd to compress
debug sections with zstd.
* Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd}
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 01f84cb9a3..2fe7674884 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1094,6 +1094,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (uintr, UINTR, ANY_UINTR, false),
SUBARCH (hreset, HRESET, ANY_HRESET, false),
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
+ SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index d4f5018b6c..2d0735c169 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -194,6 +194,7 @@ accept various extension mnemonics. For example,
@code{avx512_bf16},
@code{avx_vnni},
@code{avx512_fp16},
+@code{avx_ifma},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -826,9 +827,9 @@ prefix which generates REX prefix unconditionally.
@samp{@{nooptimize@}} -- disable instruction size optimization.
@end itemize
-Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
+Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
by default. The pseudo @samp{@{vex@}} prefix can be used to encode
-mnemonics of Intel VNNI instructions with the VEX prefix.
+mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
@cindex conversion instructions, i386
@cindex i386 conversion instructions
@@ -1486,6 +1487,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
+@item @samp{.avx_ifma}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-ifma-intel.d b/gas/testsuite/gas/i386/avx-ifma-intel.d
new file mode 100644
index 0000000000..3b6bcce2a1
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-intel.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX IFMA insns (Intel disassembly)
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq xmm2,xmm4,xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq ymm2,ymm4,ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.l b/gas/testsuite/gas/i386/avx-ifma-inval.l
new file mode 100644
index 0000000000..f706972175
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.l
@@ -0,0 +1,2 @@
+.* Assembler messages:
+.*:6: Error: unsupported instruction `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/avx-ifma-inval.s b/gas/testsuite/gas/i386/avx-ifma-inval.s
new file mode 100644
index 0000000000..0697ab2215
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma-inval.s
@@ -0,0 +1,6 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2,%xmm4,%xmm2
diff --git a/gas/testsuite/gas/i386/avx-ifma.d b/gas/testsuite/gas/i386/avx-ifma.d
new file mode 100644
index 0000000000..50c24947db
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw
+#name: i386 AVX IFMA insns
+#source: avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 d2[ ]*\{vex\} vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 d2[ ]*\{vex\} vpmadd52huq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b4 d2[ ]*vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 d2[ ]*\{vex\} vpmadd52luq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b4 d2[ ]*vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 d2[ ]*\{vex\} vpmadd52luq %ymm2,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%ecx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 08 b5 d2[ ]*vpmadd52huq %xmm2,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 dd 28 b5 d2[ ]*vpmadd52huq %ymm2,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-ifma.s b/gas/testsuite/gas/i386/avx-ifma.s
new file mode 100644
index 0000000000..983b48ebcb
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ifma.s
@@ -0,0 +1,21 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm2, %xmm4, %xmm2
+ {evex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic %xmm2, %xmm4, %xmm2
+ {vex} \mnemonic (%ecx), %xmm4, %xmm2
+ \mnemonic %ymm2, %ymm4, %ymm2
+ {evex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic %ymm2, %ymm4, %ymm2
+ {vex} \mnemonic (%ecx), %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .avx_ifma
+ vpmadd52huq %xmm2, %xmm4, %xmm2
+ vpmadd52huq %ymm2, %ymm4, %ymm2
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 0ad2b6a818..3a46807e4f 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -478,6 +478,9 @@ if [gas_32_check] then {
run_list_test "avx512_bf16_vl-inval"
run_dump_test "avx-vnni"
run_list_test "avx-vnni-inval"
+ run_dump_test "avx-ifma"
+ run_dump_test "avx-ifma-intel"
+ run_list_test "avx-ifma-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1145,6 +1148,9 @@ if [gas_64_check] then {
run_list_test "x86-64-avx512_bf16_vl-inval"
run_dump_test "x86-64-avx-vnni"
run_list_test "x86-64-avx-vnni-inval"
+ run_dump_test "x86-64-avx-ifma"
+ run_dump_test "x86-64-avx-ifma-intel"
+ run_list_test "x86-64-avx-ifma-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/noavx512-1.l b/gas/testsuite/gas/i386/noavx512-1.l
index 15a6fc689b..75c28afafb 100644
--- a/gas/testsuite/gas/i386/noavx512-1.l
+++ b/gas/testsuite/gas/i386/noavx512-1.l
@@ -37,9 +37,9 @@
.*:120: Error: .*not supported.*
.*:121: Error: .*not supported.*
.*:122: Error: .*not supported.*
-.*:126: Error: .*not supported.*
-.*:127: Error: .*not supported.*
-.*:128: Error: .*not supported.*
+.*:126: Error: .*unsupported instruction.*
+.*:127: Error: .*unsupported instruction.*
+.*:128: Error: .*unsupported instruction.*
.*:135: Error: .*operand size mismatch.*
.*:136: Error: .*unsupported masking.*
.*:137: Error: .*unsupported masking.*
@@ -50,9 +50,9 @@
.*:142: Error: .*not supported.*
.*:143: Error: .*not supported.*
.*:144: Error: .*not supported.*
-.*:148: Error: .*not supported.*
-.*:149: Error: .*not supported.*
-.*:150: Error: .*not supported.*
+.*:148: Error: .*unsupported instruction.*
+.*:149: Error: .*unsupported instruction.*
+.*:150: Error: .*unsupported instruction.*
.*:151: Error: .*not supported.*
.*:157: Error: .*operand size mismatch.*
.*:158: Error: .*unsupported masking.*
@@ -64,9 +64,9 @@
.*:164: Error: .*not supported.*
.*:165: Error: .*not supported.*
.*:166: Error: .*not supported.*
-.*:170: Error: .*not supported.*
-.*:171: Error: .*not supported.*
-.*:172: Error: .*not supported.*
+.*:170: Error: .*unsupported instruction.*
+.*:171: Error: .*unsupported instruction.*
+.*:172: Error: .*unsupported instruction.*
.*:173: Error: .*not supported.*
.*:174: Error: .*not supported.*
.*:175: Error: .*not supported.*
@@ -84,9 +84,9 @@
.*:189: Error: .*bad register name.*
.*:190: Error: .*unknown vector operation.*
.*:191: Error: .*unknown vector operation.*
-.*:192: Error: .*not supported.*
-.*:193: Error: .*not supported.*
-.*:194: Error: .*not supported.*
+.*:192: Error: .*bad register name.*
+.*:193: Error: .*unknown vector operation.*
+.*:194: Error: .*unknown vector operation.*
.*:195: Error: .*not supported.*
.*:196: Error: .*not supported.*
.*:197: Error: .*not supported.*
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
new file mode 100644
index 0000000000..0b3b053e5d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-intel.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86-64 AVX IFMA insns (Intel disassembly)
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq xmm2,xmm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq xmm2,xmm4,xmm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq ymm2,ymm4,ymm12
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq ymm2,ymm4,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq ymm2,ymm4,ymm22
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq xmm2,xmm4,xmm12
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq ymm2,ymm4,ymm12
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
new file mode 100644
index 0000000000..57a7f16807
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.l
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: unsupported instruction `vpmadd52huq'
+.*:7: Error: unsupported instruction `vpmadd52huq'
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
new file mode 100644
index 0000000000..0e37bf2361
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma-inval.s
@@ -0,0 +1,7 @@
+# Check illegal in AVXIFMA instructions
+
+ .text
+ .arch .noavx512ifma
+_start:
+ vpmadd52huq %xmm2, %xmm4, %xmm2
+ vpmadd52huq %xmm22, %xmm4, %xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.d b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
new file mode 100644
index 0000000000..b1670b68b6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.d
@@ -0,0 +1,34 @@
+#as:
+#objdump: -dw
+#name: x86-64 AVX IFMA insns
+#source: x86-64-avx-ifma.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b5 d4[ ]*\{vex\} vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b5 d6[ ]*vpmadd52huq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b5 d4[ ]*\{vex\} vpmadd52huq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b5 11[ ]*\{vex\} vpmadd52huq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b5 d6[ ]*vpmadd52huq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b4 d4[ ]*vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 d9 b4 d4[ ]*\{vex\} vpmadd52luq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 d9 b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 08 b4 d6[ ]*vpmadd52luq %xmm22,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b4 d4[ ]*vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 c2 dd b4 d4[ ]*\{vex\} vpmadd52luq %ymm12,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e2 dd b4 11[ ]*\{vex\} vpmadd52luq \(%rcx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 b2 dd 28 b4 d6[ ]*vpmadd52luq %ymm22,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 08 b5 d4[ ]*vpmadd52huq %xmm12,%xmm4,%xmm2
+[ ]*[a-f0-9]+:[ ]*62 d2 dd 28 b5 d4[ ]*vpmadd52huq %ymm12,%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ifma.s b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
new file mode 100644
index 0000000000..bfc524a103
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ifma.s
@@ -0,0 +1,23 @@
+ .allow_index_reg
+
+.macro test_insn mnemonic
+ \mnemonic %xmm12, %xmm4, %xmm2
+ {evex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic %xmm12, %xmm4, %xmm2
+ {vex} \mnemonic (%rcx), %xmm4, %xmm2
+ \mnemonic %xmm22, %xmm4, %xmm2
+ \mnemonic %ymm12, %ymm4, %ymm2
+ {evex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic %ymm12, %ymm4, %ymm2
+ {vex} \mnemonic (%rcx), %ymm4, %ymm2
+ \mnemonic %ymm22, %ymm4, %ymm2
+.endm
+
+ .text
+_start:
+ test_insn vpmadd52huq
+ test_insn vpmadd52luq
+
+ .arch .avx_ifma
+ vpmadd52huq %xmm12, %xmm4, %xmm2
+ vpmadd52huq %ymm12, %ymm4, %ymm2
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 83290700c6..e736acce80 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1526,6 +1526,8 @@ enum
VEX_W_0F385E_X86_64_P_3,
VEX_W_0F3878,
VEX_W_0F3879,
+ VEX_W_0F38B4,
+ VEX_W_0F38B5,
VEX_W_0F38CF,
VEX_W_0F3A00_L_1,
VEX_W_0F3A01_L_1,
@@ -6293,8 +6295,8 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F38B4) },
+ { VEX_W_TABLE (VEX_W_0F38B5) },
{ "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* b8 */
@@ -7599,6 +7601,16 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3879 */
{ "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
+ {
+ /* VEX_W_0F38B4 */
+ { Bad_Opcode },
+ { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F38B5 */
+ { Bad_Opcode },
+ { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
+ },
{
/* VEX_W_0F38CF */
{ "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index eb3bd85079..060bb304cd 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -245,6 +245,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
{ "CPU_AVX512_FP16_FLAGS",
"CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
+ { "CPU_AVX_IFMA_FLAGS",
+ "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -370,7 +372,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI" },
+ "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
@@ -439,6 +441,8 @@ static initializer cpu_flag_init[] =
"CpuHRESET" },
{ "CPU_ANY_AVX512_FP16_FLAGS",
"CpuAVX512_FP16" },
+ { "CPU_ANY_AVX_IFMA_FLAGS",
+ "CpuAVX_IFMA" },
};
static initializer operand_type_init[] =
@@ -640,6 +644,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuTDX),
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuAVX512_FP16),
+ BITFIELD (CpuAVX_IFMA),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c033aeb8e0..8ff66d42cc 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -209,6 +209,8 @@ enum
CpuAVX_VNNI,
/* Intel AVX-512 FP16 Instructions support required. */
CpuAVX512_FP16,
+ /* Intel AVX IFMA Instructions support required. */
+ CpuAVX_IFMA,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -388,6 +390,7 @@ typedef union i386_cpu_flags
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
+ unsigned int cpuavx_ifma:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index fbd48c203a..8ce92ae390 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3263,3 +3263,10 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast
vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
// FP16 (HFNI) instructions end.
+
+// AVX_IFMA instructions.
+
+vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+
+// AVX_IFMA instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 02/10] Support Intel AVX-VNNI-INT8
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-25 6:34 ` Jan Beulich
2022-10-19 15:15 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
` (7 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Cui,Lili
From: "Cui,Lili" <lili.cui@intel.com>
gas/
* NEWS: Support Intel AVX-VNNI-INT8.
* config/tc-i386.c: Add avx_vnni_int8.
* doc/c-i386.texi: Document avx_vnni_int8.
* testsuite/gas/i386/avx-vnni-int8-intel.d: New file.
* testsuite/gas/i386/avx-vnni-int8.d: Likewise.
* testsuite/gas/i386/avx-vnni-int8.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests.
opcodes/
* i386-dis.c: (PREFIX_VEX_0F3850) New.
(PREFIX_VEX_0F3851): Likewise.
(VEX_W_0F3850_P_0): Likewise.
(VEX_W_0F3850_P_1): Likewise.
(VEX_W_0F3850_P_2): Likewise.
(VEX_W_0F3850_P_3): Likewise.
(VEX_W_0F3851_P_0): Likewise.
(VEX_W_0F3851_P_1): Likewise.
(VEX_W_0F3851_P_2): Likewise.
(VEX_W_0F3851_P_3): Likewise.
(VEX_W_0F3850): Delete.
(VEX_W_0F3851): Likewise.
(prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851.
(vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851,
delete VEX_W_0F3850 and VEX_W_0F3851.
(vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2
VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2
and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851.
* i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS
and CPU_ANY_AVX_VNNI_INT8_FLAGS.
(cpu_flags): Add CpuAVX_VNNI_INT8.
* i386-opc.h (CpuAVX_VNNI_INT8): New.
* i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/avx-vnni-int8-intel.d | 71 +
gas/testsuite/gas/i386/avx-vnni-int8.d | 71 +
gas/testsuite/gas/i386/avx-vnni-int8.s | 127 +
gas/testsuite/gas/i386/i386.exp | 4 +
.../gas/i386/x86-64-avx-vnni-int8-intel.d | 71 +
gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d | 71 +
gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s | 127 +
opcodes/i386-dis.c | 23 +-
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 524 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 11 +
opcodes/i386-tbl.h | 7876 +++++++++--------
16 files changed, 4847 insertions(+), 4145 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8-intel.d
create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.d
create mode 100644 gas/testsuite/gas/i386/avx-vnni-int8.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s
diff --git a/gas/NEWS b/gas/NEWS
index 7cf65728ba..86996be2f5 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AVX-VNNI-INT8 instructions.
+
* Add support for Intel AVX-IFMA instructions.
* gas now supports --compress-debug-sections=zstd to compress
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 2fe7674884..8329529d38 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1095,6 +1095,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (hreset, HRESET, ANY_HRESET, false),
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
+ SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 2d0735c169..f039456cf3 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -195,6 +195,7 @@ accept various extension mnemonics. For example,
@code{avx_vnni},
@code{avx512_fp16},
@code{avx_ifma},
+@code{avx_vnni_int8},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1487,7 +1488,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
-@item @samp{.avx_ifma}
+@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d
new file mode 100644
index 0000000000..1d7d162f20
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-vnni-int8-intel.d
@@ -0,0 +1,71 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX-VNNI-INT8 insns (Intel disassembly)
+#source: avx-vnni-int8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.d b/gas/testsuite/gas/i386/avx-vnni-int8.d
new file mode 100644
index 0000000000..cd4499e59f
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-vnni-int8.d
@@ -0,0 +1,71 @@
+#as:
+#objdump: -dw
+#name: i386 AVX-VNNI-INT8 insns
+#source: avx-vnni-int8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 57 50 f4\s+vpdpbssd %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 53 50 f4\s+vpdpbssd %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 57 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 50 31\s+vpdpbssd \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 50 b1 e0 0f 00 00\s+vpdpbssd 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 50 b2 00 f0 ff ff\s+vpdpbssd -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 53 50 b4 f4 00 00 00 10\s+vpdpbssd 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 50 31\s+vpdpbssd \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 50 b1 f0 07 00 00\s+vpdpbssd 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 50 b2 00 f8 ff ff\s+vpdpbssd -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 57 51 f4\s+vpdpbssds %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 53 51 f4\s+vpdpbssds %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 57 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 51 31\s+vpdpbssds \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 51 b1 e0 0f 00 00\s+vpdpbssds 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 57 51 b2 00 f0 ff ff\s+vpdpbssds -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 53 51 b4 f4 00 00 00 10\s+vpdpbssds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 51 31\s+vpdpbssds \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 51 b1 f0 07 00 00\s+vpdpbssds 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 53 51 b2 00 f8 ff ff\s+vpdpbssds -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 56 50 f4\s+vpdpbsud %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 52 50 f4\s+vpdpbsud %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 56 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 50 31\s+vpdpbsud \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 50 b1 e0 0f 00 00\s+vpdpbsud 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 50 b2 00 f0 ff ff\s+vpdpbsud -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 52 50 b4 f4 00 00 00 10\s+vpdpbsud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 50 31\s+vpdpbsud \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 50 b1 f0 07 00 00\s+vpdpbsud 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 50 b2 00 f8 ff ff\s+vpdpbsud -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 56 51 f4\s+vpdpbsuds %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 52 51 f4\s+vpdpbsuds %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 56 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 51 31\s+vpdpbsuds \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 51 b1 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 56 51 b2 00 f0 ff ff\s+vpdpbsuds -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 52 51 b4 f4 00 00 00 10\s+vpdpbsuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 51 31\s+vpdpbsuds \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 51 b1 f0 07 00 00\s+vpdpbsuds 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 52 51 b2 00 f8 ff ff\s+vpdpbsuds -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 54 50 f4\s+vpdpbuud %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 50 50 f4\s+vpdpbuud %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 54 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 50 31\s+vpdpbuud \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 50 b1 e0 0f 00 00\s+vpdpbuud 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 50 b2 00 f0 ff ff\s+vpdpbuud -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 50 50 b4 f4 00 00 00 10\s+vpdpbuud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 50 31\s+vpdpbuud \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 50 b1 f0 07 00 00\s+vpdpbuud 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 50 b2 00 f8 ff ff\s+vpdpbuud -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 54 51 f4\s+vpdpbuuds %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 50 51 f4\s+vpdpbuuds %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 54 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 51 31\s+vpdpbuuds \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 51 b1 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 54 51 b2 00 f0 ff ff\s+vpdpbuuds -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*c4 e2 50 51 b4 f4 00 00 00 10\s+vpdpbuuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 51 31\s+vpdpbuuds \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 51 b1 f0 07 00 00\s+vpdpbuuds 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 50 51 b2 00 f8 ff ff\s+vpdpbuuds -0x800\(%edx\),%xmm5,%xmm6
+#pass
diff --git a/gas/testsuite/gas/i386/avx-vnni-int8.s b/gas/testsuite/gas/i386/avx-vnni-int8.s
new file mode 100644
index 0000000000..e3cfeb6680
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-vnni-int8.s
@@ -0,0 +1,127 @@
+# Check 32bit AVX-VNNI-INT8 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpdpbssd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssd %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssd 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssd (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssd 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssd -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssd 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssd (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssd 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssd -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbssds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbssds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbssds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbsuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbsuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8
+ vpdpbuuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8
+ vpdpbuuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT8 Disp32(00f8ffff)
+
+.intel_syntax noprefix
+ vpdpbssd ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbssd xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbssd ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbssd ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssd ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssd xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbssd xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssd xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbssds ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbssds xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbssds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbssds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbssds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsud ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbsud xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbsud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbsud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbsud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbsuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbsuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbsuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbsuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuud ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbuud xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbuud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbuud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbuud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuuds ymm6, ymm5, ymm4 #AVX-VNNI-INT8
+ vpdpbuuds xmm6, xmm5, xmm4 #AVX-VNNI-INT8
+ vpdpbuuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbuuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT8
+ vpdpbuuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a46807e4f..08774c38d9 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -481,6 +481,8 @@ if [gas_32_check] then {
run_dump_test "avx-ifma"
run_dump_test "avx-ifma-intel"
run_list_test "avx-ifma-inval"
+ run_dump_test "avx-vnni-int8"
+ run_dump_test "avx-vnni-int8-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1151,6 +1153,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx-ifma"
run_dump_test "x86-64-avx-ifma-intel"
run_list_test "x86-64-avx-ifma-inval"
+ run_dump_test "x86-64-avx-vnni-int8"
+ run_dump_test "x86-64-avx-vnni-int8-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d
new file mode 100644
index 0000000000..61c01124ef
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d
@@ -0,0 +1,71 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX-VNNI-INT8 insns (Intel disassembly)
+#source: x86-64-avx-vnni-int8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds ymm10,ymm9,ymm8
+\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds xmm10,xmm9,xmm8
+\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds ymm10,ymm9,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds xmm10,xmm9,XMMWORD PTR \[rdx-0x800\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d
new file mode 100644
index 0000000000..90faed581b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.d
@@ -0,0 +1,71 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX-VNNI-INT8 insns
+#source: x86-64-avx-vnni-int8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 42 37 50 d0\s+vpdpbssd %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 33 50 d0\s+vpdpbssd %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 37 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 37 50 11\s+vpdpbssd \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 37 50 91 e0 0f 00 00\s+vpdpbssd 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 37 50 92 00 f0 ff ff\s+vpdpbssd -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 33 50 94 f5 00 00 00 10\s+vpdpbssd 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 33 50 11\s+vpdpbssd \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 33 50 91 f0 07 00 00\s+vpdpbssd 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 33 50 92 00 f8 ff ff\s+vpdpbssd -0x800\(%rdx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 37 51 d0\s+vpdpbssds %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 33 51 d0\s+vpdpbssds %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 37 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 37 51 11\s+vpdpbssds \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 37 51 91 e0 0f 00 00\s+vpdpbssds 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 37 51 92 00 f0 ff ff\s+vpdpbssds -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 33 51 94 f5 00 00 00 10\s+vpdpbssds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 33 51 11\s+vpdpbssds \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 33 51 91 f0 07 00 00\s+vpdpbssds 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 33 51 92 00 f8 ff ff\s+vpdpbssds -0x800\(%rdx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 36 50 d0\s+vpdpbsud %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 32 50 d0\s+vpdpbsud %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 36 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 36 50 11\s+vpdpbsud \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 36 50 91 e0 0f 00 00\s+vpdpbsud 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 36 50 92 00 f0 ff ff\s+vpdpbsud -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 32 50 94 f5 00 00 00 10\s+vpdpbsud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 32 50 11\s+vpdpbsud \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 32 50 91 f0 07 00 00\s+vpdpbsud 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 32 50 92 00 f8 ff ff\s+vpdpbsud -0x800\(%rdx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 36 51 d0\s+vpdpbsuds %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 32 51 d0\s+vpdpbsuds %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 36 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 36 51 11\s+vpdpbsuds \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 36 51 91 e0 0f 00 00\s+vpdpbsuds 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 36 51 92 00 f0 ff ff\s+vpdpbsuds -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 32 51 94 f5 00 00 00 10\s+vpdpbsuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 32 51 11\s+vpdpbsuds \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 32 51 91 f0 07 00 00\s+vpdpbsuds 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 32 51 92 00 f8 ff ff\s+vpdpbsuds -0x800\(%rdx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 34 50 d0\s+vpdpbuud %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 30 50 d0\s+vpdpbuud %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 34 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 34 50 11\s+vpdpbuud \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 34 50 91 e0 0f 00 00\s+vpdpbuud 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 34 50 92 00 f0 ff ff\s+vpdpbuud -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 30 50 94 f5 00 00 00 10\s+vpdpbuud 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 30 50 11\s+vpdpbuud \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 30 50 91 f0 07 00 00\s+vpdpbuud 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 30 50 92 00 f8 ff ff\s+vpdpbuud -0x800\(%rdx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 34 51 d0\s+vpdpbuuds %ymm8,%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 30 51 d0\s+vpdpbuuds %xmm8,%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 22 34 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 42 34 51 11\s+vpdpbuuds \(%r9\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 34 51 91 e0 0f 00 00\s+vpdpbuuds 0xfe0\(%rcx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 62 34 51 92 00 f0 ff ff\s+vpdpbuuds -0x1000\(%rdx\),%ymm9,%ymm10
+\s*[a-f0-9]+:\s*c4 22 30 51 94 f5 00 00 00 10\s+vpdpbuuds 0x10000000\(%rbp,%r14,8\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 42 30 51 11\s+vpdpbuuds \(%r9\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 30 51 91 f0 07 00 00\s+vpdpbuuds 0x7f0\(%rcx\),%xmm9,%xmm10
+\s*[a-f0-9]+:\s*c4 62 30 51 92 00 f8 ff ff\s+vpdpbuuds -0x800\(%rdx\),%xmm9,%xmm10
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s
new file mode 100644
index 0000000000..bc9145b26f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-int8.s
@@ -0,0 +1,127 @@
+# Check 64bit AVX-VNNI-INT8 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpdpbssd %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssd %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssd 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssd (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssd 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssd -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssd 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssd (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssd 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssd -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbssds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbssds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbssds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbsuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbsuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuud %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuud %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuud 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuud (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuud 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuud -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuud 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuud (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuud 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuud -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuuds %ymm8, %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuuds %xmm8, %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuuds 0x10000000(%rbp, %r14, 8), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuuds (%r9), %ymm9, %ymm10 #AVX-VNNI-INT8
+ vpdpbuuds 4064(%rcx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuuds -4096(%rdx), %ymm9, %ymm10 #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuuds 0x10000000(%rbp, %r14, 8), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuuds (%r9), %xmm9, %xmm10 #AVX-VNNI-INT8
+ vpdpbuuds 2032(%rcx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuuds -2048(%rdx), %xmm9, %xmm10 #AVX-VNNI-INT8 Disp32(00f8ffff)
+
+.intel_syntax noprefix
+ vpdpbssd ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbssd xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbssd ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssd ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbssd ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssd ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssd xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssd xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbssd xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssd xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbssds ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbssds xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbssds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbssds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbssds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbssds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbssds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbssds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbssds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsud ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbsud xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbsud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbsud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbsud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbsuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbsuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbsuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbsuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbsuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbsuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbsuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbsuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbsuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuud ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbuud xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbuud ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuud ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbuud ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuud ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuud xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuud xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbuud xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuud xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
+ vpdpbuuds ymm10, ymm9, ymm8 #AVX-VNNI-INT8
+ vpdpbuuds xmm10, xmm9, xmm8 #AVX-VNNI-INT8
+ vpdpbuuds ymm10, ymm9, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuuds ymm10, ymm9, YMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbuuds ymm10, ymm9, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT8 Disp32(e00f0000)
+ vpdpbuuds ymm10, ymm9, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT8 Disp32(00f0ffff)
+ vpdpbuuds xmm10, xmm9, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT8
+ vpdpbuuds xmm10, xmm9, XMMWORD PTR [r9] #AVX-VNNI-INT8
+ vpdpbuuds xmm10, xmm9, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT8 Disp32(f0070000)
+ vpdpbuuds xmm10, xmm9, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT8 Disp32(00f8ffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index e736acce80..51f1f21d2e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1128,6 +1128,8 @@ enum
PREFIX_VEX_0FF0,
PREFIX_VEX_0F3849_X86_64,
PREFIX_VEX_0F384B_X86_64,
+ PREFIX_VEX_0F3850_W_0,
+ PREFIX_VEX_0F3851_W_0,
PREFIX_VEX_0F385C_X86_64,
PREFIX_VEX_0F385E_X86_64,
PREFIX_VEX_0F38F5_L_0,
@@ -4004,6 +4006,21 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
},
+ /* PREFIX_VEX_0F3850_W_0 */
+ {
+ { "vpdpbuud", { XM, Vex, EXx }, 0 },
+ { "vpdpbsud", { XM, Vex, EXx }, 0 },
+ { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
+ { "vpdpbssd", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3851_W_0 */
+ {
+ { "vpdpbuuds", { XM, Vex, EXx }, 0 },
+ { "vpdpbsuds", { XM, Vex, EXx }, 0 },
+ { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
+ { "vpdpbssds", { XM, Vex, EXx }, 0 },
+ },
/* PREFIX_VEX_0F385C_X86_64 */
{
{ Bad_Opcode },
@@ -7547,11 +7564,11 @@ static const struct dis386 vex_w_table[][2] = {
},
{
/* VEX_W_0F3850 */
- { "%XVvpdpbusd", { XM, Vex, EXx }, PREFIX_DATA },
+ { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
},
{
- /* VEX_W_0F3851 */
- { "%XVvpdpbusds", { XM, Vex, EXx }, PREFIX_DATA },
+ /* VEX_W_0F3851_P_0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
},
{
/* VEX_W_0F3852 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 060bb304cd..27d0f8fc31 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -247,6 +247,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
{ "CPU_AVX_IFMA_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_IFMA" },
+ { "CPU_AVX_VNNI_INT8_FLAGS",
+ "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -372,7 +374,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA" },
+ "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
@@ -443,6 +445,8 @@ static initializer cpu_flag_init[] =
"CpuAVX512_FP16" },
{ "CPU_ANY_AVX_IFMA_FLAGS",
"CpuAVX_IFMA" },
+ { "CPU_ANY_AVX_VNNI_INT8_FLAGS",
+ "CpuAVX_VNNI_INT8" },
};
static initializer operand_type_init[] =
@@ -645,6 +649,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuAVX512_FP16),
BITFIELD (CpuAVX_IFMA),
+ BITFIELD (CpuAVX_VNNI_INT8),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 8ff66d42cc..e9c6785898 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -211,6 +211,8 @@ enum
CpuAVX512_FP16,
/* Intel AVX IFMA Instructions support required. */
CpuAVX_IFMA,
+ /* Intel AVX VNNI-INT8 Instructions support required. */
+ CpuAVX_VNNI_INT8,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -391,6 +393,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
unsigned int cpuavx_ifma:1;
+ unsigned int cpuavx_vnni_int8:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 8ce92ae390..358a1cffac 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3270,3 +3270,14 @@ vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexV
vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX_IFMA instructions end.
+
+// AVX_VNNI_INT8 instructions.
+
+vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+
+// AVX_VNNI_INT8 instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 02/10] Support Intel AVX-VNNI-INT8
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
@ 2022-10-25 6:34 ` Jan Beulich
0 siblings, 0 replies; 15+ messages in thread
From: Jan Beulich @ 2022-10-25 6:34 UTC (permalink / raw)
To: Haochen Jiang; +Cc: hjl.tools, Cui,Lili, binutils
On 19.10.2022 17:15, Haochen Jiang wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3270,3 +3270,14 @@ vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexV
> vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>
> // AVX_IFMA instructions end.
> +
> +// AVX_VNNI_INT8 instructions.
> +
> +vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> +
> +// AVX_VNNI_INT8 instructions end.
Like for patch 1 as a minor remark: Perhaps better insert right after the
AVX-VNNI templates, to have related things close together?
Jan
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 03/10] Support Intel AVX-NE-CONVERT
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-19 15:15 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Kong Lingling
From: Kong Lingling <lingling.kong@intel.com>
gas/ChangeLog:
* NEWS: Support Intel AVX-NE-CONVERT.
* config/tc-i386.c: Add avx_ne_convert.
* doc/c-i386.texi: Document .avx_ne_convert.
* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
* testsuite/gas/i386/avx-ne-convert.d: Ditto.
* testsuite/gas/i386/avx-ne-convert.s: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_0F3872): New.
(PREFIX_VEX_0F38B0): Ditto.
(PREFIX_VEX_0F38B1): Ditto.
(VEX_W_0F3872_P_1): Ditto.
(VEX_W_0F38B0_P_0): Ditto.
(VEX_W_0F38B0_P_1): Ditto.
(VEX_W_0F38B0_P_2): Ditto.
(VEX_W_0F38B0_P_3): Ditto.
(VEX_W_0F38B1_P_1): Ditto.
(VEX_W_0F38B1_P_2): Ditto.
(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0,
PREFIX_VEX_0F38B1.
(vex_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0_P_0,
VEX_W_0F38B0_P_1, VEX_W_0F38B0_P_2, VEX_W_0F38B0_P_3,
VEX_W_0F38B1_P_1,VEX_W_0F38B1_P_2.
* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
CPU_ANY_AVX_NE_CONVERT_FLAGS.
(cpu_flags): Add CpuAVX_NE_CONVERT.
* i386-init.h: Regenerated.
* i386-opc.h (CpuAVX_NE CONVERT): New.
(i386_cpu_flags): Add cpuavx_ne_convert.
* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/avx-ne-convert-intel.d | 170 +
gas/testsuite/gas/i386/avx-ne-convert.d | 170 +
gas/testsuite/gas/i386/avx-ne-convert.s | 167 +
gas/testsuite/gas/i386/i386.exp | 4 +
.../gas/i386/x86-64-avx-ne-convert-intel.d | 170 +
.../gas/i386/x86-64-avx-ne-convert.d | 170 +
.../gas/i386/x86-64-avx-ne-convert.s | 167 +
opcodes/i386-dis.c | 58 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 518 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 15 +
opcodes/i386-tbl.h | 7950 +++++++++--------
16 files changed, 5419 insertions(+), 4154 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-ne-convert-intel.d
create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.d
create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.s
diff --git a/gas/NEWS b/gas/NEWS
index 86996be2f5..d5e06bd1de 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AVX-NE-CONVERT instructions.
+
* Add support for Intel AVX-VNNI-INT8 instructions.
* Add support for Intel AVX-IFMA instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 8329529d38..42579bb701 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1096,6 +1096,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
+ SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index f039456cf3..f70994eca8 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -196,6 +196,7 @@ accept various extension mnemonics. For example,
@code{avx512_fp16},
@code{avx_ifma},
@code{avx_vnni_int8},
+@code{avx_ne_convert},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1488,7 +1489,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
-@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
+@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-ne-convert-intel.d b/gas/testsuite/gas/i386/avx-ne-convert-intel.d
new file mode 100644
index 0000000000..490fd9516f
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert-intel.d
@@ -0,0 +1,170 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX-NE-CONVERT insns (Intel disassembly)
+#source: avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
diff --git a/gas/testsuite/gas/i386/avx-ne-convert.d b/gas/testsuite/gas/i386/avx-ne-convert.d
new file mode 100644
index 0000000000..24f6ae09fe
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert.d
@@ -0,0 +1,170 @@
+#as:
+#objdump: -dw
+#name: i386 AVX-NE-CONVERT insns
+#source: avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
diff --git a/gas/testsuite/gas/i386/avx-ne-convert.s b/gas/testsuite/gas/i386/avx-ne-convert.s
new file mode 100644
index 0000000000..7fb866630d
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert.s
@@ -0,0 +1,167 @@
+# Check 32bit AVX-NE-CONVERT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vbcstnebf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vbcstnebf162ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vbcstnebf162ps 254(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps -256(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnebf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vbcstnebf162ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vbcstnebf162ps 254(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps -256(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vbcstnesh2ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vbcstnesh2ps 254(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps -256(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vbcstnesh2ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vbcstnesh2ps 254(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps -256(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vcvtneebf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneebf162ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vcvtneebf162ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneebf162ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneebf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneebf162ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vcvtneebf162ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneebf162ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneeph2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneeph2ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vcvtneeph2ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneeph2ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneeph2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneeph2ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vcvtneeph2ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneeph2ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneobf162ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneobf162ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vcvtneobf162ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneobf162ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneobf162ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneobf162ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vcvtneobf162ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneobf162ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneoph2ps 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneoph2ps (%ecx), %xmm6 #AVX-NE-CONVERT
+ vcvtneoph2ps 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneoph2ps -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneoph2ps 0x10000000(%esp, %esi, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneoph2ps (%ecx), %ymm6 #AVX-NE-CONVERT
+ vcvtneoph2ps 4064(%ecx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneoph2ps -4096(%edx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16x (%ecx), %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {evex} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {vex} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {vex3} vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {evex} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex3} vcvtneps2bf16x -2048(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {evex} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex3} vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {evex} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex3} vcvtneps2bf16y -4096(%edx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+
+.intel_syntax noprefix
+ vbcstnebf162ps xmm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnebf162ps xmm6, WORD PTR [ecx] #AVX-NE-CONVERT
+ vbcstnebf162ps xmm6, WORD PTR [ecx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps xmm6, WORD PTR [edx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnebf162ps ymm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnebf162ps ymm6, WORD PTR [ecx] #AVX-NE-CONVERT
+ vbcstnebf162ps ymm6, WORD PTR [ecx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps ymm6, WORD PTR [edx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps xmm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnesh2ps xmm6, WORD PTR [ecx] #AVX-NE-CONVERT
+ vbcstnesh2ps xmm6, WORD PTR [ecx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps xmm6, WORD PTR [edx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps ymm6, WORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnesh2ps ymm6, WORD PTR [ecx] #AVX-NE-CONVERT
+ vbcstnesh2ps ymm6, WORD PTR [ecx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps ymm6, WORD PTR [edx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vcvtneebf162ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneebf162ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneebf162ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneebf162ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneebf162ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneebf162ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneebf162ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneebf162ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneeph2ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneeph2ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneeph2ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneeph2ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneeph2ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneeph2ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneeph2ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneeph2ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneobf162ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneobf162ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneobf162ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneobf162ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneobf162ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneobf162ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneobf162ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneobf162ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneoph2ps xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneoph2ps xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneoph2ps xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneoph2ps xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneoph2ps ymm6, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneoph2ps ymm6, YMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneoph2ps ymm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneoph2ps ymm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx] #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [edx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [edx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 08774c38d9..d03c2187ea 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -483,6 +483,8 @@ if [gas_32_check] then {
run_list_test "avx-ifma-inval"
run_dump_test "avx-vnni-int8"
run_dump_test "avx-vnni-int8-intel"
+ run_dump_test "avx-ne-convert"
+ run_dump_test "avx-ne-convert-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1155,6 +1157,8 @@ if [gas_64_check] then {
run_list_test "x86-64-avx-ifma-inval"
run_dump_test "x86-64-avx-vnni-int8"
run_dump_test "x86-64-avx-vnni-int8-intel"
+ run_dump_test "x86-64-avx-ne-convert"
+ run_dump_test "x86-64-avx-ne-convert-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
new file mode 100644
index 0000000000..96ec69a12c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
@@ -0,0 +1,170 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX-NE-CONVERT insns (Intel disassembly)
+#source: x86-64-avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
new file mode 100644
index 0000000000..6bd8391ed5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
@@ -0,0 +1,170 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX-NE-CONVERT insns
+#source: x86-64-avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s
new file mode 100644
index 0000000000..c01a95d943
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s
@@ -0,0 +1,167 @@
+# Check 64bit AVX-NE-CONVERT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vbcstnebf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vbcstnebf162ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vbcstnebf162ps 254(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps -256(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnebf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vbcstnebf162ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vbcstnebf162ps 254(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps -256(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vbcstnesh2ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vbcstnesh2ps 254(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps -256(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vbcstnesh2ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vbcstnesh2ps 254(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps -256(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00ffffff)
+ vcvtneebf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneebf162ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vcvtneebf162ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneebf162ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneebf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneebf162ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vcvtneebf162ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneebf162ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneeph2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneeph2ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vcvtneeph2ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneeph2ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneeph2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneeph2ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vcvtneeph2ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneeph2ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneobf162ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneobf162ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vcvtneobf162ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneobf162ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneobf162ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneobf162ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vcvtneobf162ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneobf162ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneoph2ps 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneoph2ps (%r9), %xmm6 #AVX-NE-CONVERT
+ vcvtneoph2ps 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneoph2ps -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneoph2ps 0x10000000(%rbp, %r14, 8), %ymm6 #AVX-NE-CONVERT
+ vcvtneoph2ps (%r9), %ymm6 #AVX-NE-CONVERT
+ vcvtneoph2ps 4064(%rcx), %ymm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneoph2ps -4096(%rdx), %ymm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 %xmm5, %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 %ymm5, %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16x (%r9), %xmm6 #AVX-NE-CONVERT
+ vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {evex} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {vex} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ {vex3} vcvtneps2bf16x 2032(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {evex} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex3} vcvtneps2bf16x -2048(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {evex} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex3} vcvtneps2bf16y 4064(%rcx), %xmm6 #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {evex} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex3} vcvtneps2bf16y -4096(%rdx), %xmm6 #AVX-NE-CONVERT Disp32(00f0ffff)
+
+.intel_syntax noprefix
+ vbcstnebf162ps xmm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnebf162ps xmm6, WORD PTR [r9] #AVX-NE-CONVERT
+ vbcstnebf162ps xmm6, WORD PTR [rcx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps xmm6, WORD PTR [rdx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnebf162ps ymm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnebf162ps ymm6, WORD PTR [r9] #AVX-NE-CONVERT
+ vbcstnebf162ps ymm6, WORD PTR [rcx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnebf162ps ymm6, WORD PTR [rdx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps xmm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnesh2ps xmm6, WORD PTR [r9] #AVX-NE-CONVERT
+ vbcstnesh2ps xmm6, WORD PTR [rcx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps xmm6, WORD PTR [rdx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vbcstnesh2ps ymm6, WORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vbcstnesh2ps ymm6, WORD PTR [r9] #AVX-NE-CONVERT
+ vbcstnesh2ps ymm6, WORD PTR [rcx+254] #AVX-NE-CONVERT Disp32(fe000000)
+ vbcstnesh2ps ymm6, WORD PTR [rdx-256] #AVX-NE-CONVERT Disp32(00ffffff)
+ vcvtneebf162ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneebf162ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneebf162ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneebf162ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneebf162ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneebf162ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneebf162ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneebf162ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneeph2ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneeph2ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneeph2ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneeph2ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneeph2ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneeph2ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneeph2ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneeph2ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneobf162ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneobf162ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneobf162ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneobf162ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneobf162ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneobf162ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneobf162ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneobf162ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneoph2ps xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneoph2ps xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneoph2ps xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneoph2ps xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneoph2ps ymm6, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneoph2ps ymm6, YMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneoph2ps ymm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneoph2ps ymm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, xmm5 #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, ymm5 #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [r9] #AVX-NE-CONVERT
+ vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rcx+2032] #AVX-NE-CONVERT Disp32(f0070000)
+ vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {evex} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ {vex3} vcvtneps2bf16 xmm6, XMMWORD PTR [rdx-2048] #AVX-NE-CONVERT Disp32(00f8ffff)
+ vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [rcx+4064] #AVX-NE-CONVERT Disp32(e00f0000)
+ vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {evex} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
+ {vex3} vcvtneps2bf16 xmm6, YMMWORD PTR [rdx-4096] #AVX-NE-CONVERT Disp32(00f0ffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 51f1f21d2e..c83c2a91ce 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -937,6 +937,8 @@ enum
MOD_VEX_0F385E_X86_64_P_3_W_0,
MOD_VEX_0F388C,
MOD_VEX_0F388E,
+ MOD_VEX_0F38B0,
+ MOD_VEX_0F38B1,
MOD_VEX_0F3A30_L_0,
MOD_VEX_0F3A31_L_0,
MOD_VEX_0F3A32_L_0,
@@ -1132,6 +1134,9 @@ enum
PREFIX_VEX_0F3851_W_0,
PREFIX_VEX_0F385C_X86_64,
PREFIX_VEX_0F385E_X86_64,
+ PREFIX_VEX_0F3872,
+ PREFIX_VEX_0F38B0,
+ PREFIX_VEX_0F38B1,
PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0,
PREFIX_VEX_0F38F7_L_0,
@@ -1526,8 +1531,11 @@ enum
VEX_W_0F385E_X86_64_P_1,
VEX_W_0F385E_X86_64_P_2,
VEX_W_0F385E_X86_64_P_3,
+ VEX_W_0F3872_P_1,
VEX_W_0F3878,
VEX_W_0F3879,
+ VEX_W_0F38B0,
+ VEX_W_0F38B1,
VEX_W_0F38B4,
VEX_W_0F38B5,
VEX_W_0F38CF,
@@ -4035,7 +4043,31 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
{ VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
},
+
+ /* PREFIX_VEX_0F3872 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3872_P_1) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* PREFIX_VEX_0F38B0 */
+ {
+ { "vcvtneoph2ps", {XM, Mx}, 0 },
+ { "vcvtneebf162ps", {XM, Mx}, 0 },
+ { "vcvtneeph2ps", {XM, Mx}, 0 },
+ { "vcvtneobf162ps", {XM, Mx}, 0 },
+ },
+
+ /* PREFIX_VEX_0F38B1 */
+ {
+ { Bad_Opcode },
+ { "vbcstnebf162ps", {XM, Ew}, 0 },
+ { "vbcstnesh2ps", {XM, Ew}, 0 },
+ { Bad_Opcode },
+ },
+
/* PREFIX_VEX_0F38F5_L_0 */
{
{ "bzhiS", { Gdq, Edq, VexGdq }, 0 },
@@ -6238,7 +6270,7 @@ static const struct dis386 vex_table[][256] = {
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3872) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6308,8 +6340,8 @@ static const struct dis386 vex_table[][256] = {
{ "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* b0 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38B0) },
+ { MOD_TABLE (MOD_VEX_0F38B1) },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F38B4) },
@@ -7610,6 +7642,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F385E_X86_64_P_3 */
{ MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
},
+ {
+ /* VEX_W_0F3872_P_1 */
+ { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
+ },
{
/* VEX_W_0F3878 */
{ "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
@@ -7618,6 +7654,14 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3879 */
{ "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
+ {
+ /* VEX_W_0F38B0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F38B0) },
+ },
+ {
+ /* VEX_W_0F38B1 */
+ { PREFIX_TABLE (PREFIX_VEX_0F38B1) },
+ },
{
/* VEX_W_0F38B4 */
{ Bad_Opcode },
@@ -8428,6 +8472,14 @@ static const struct dis386 mod_table[][2] = {
/* MOD_VEX_0F388E */
{ "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
},
+ {
+ /* MOD_VEX_0F38B0*/
+ { VEX_W_TABLE (VEX_W_0F38B0) },
+ },
+ {
+ /* MOD_VEX_0F38B1*/
+ { VEX_W_TABLE (VEX_W_0F38B1) },
+ },
{
/* MOD_VEX_0F3A30_L_0 */
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 27d0f8fc31..e7f51bef8c 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -249,6 +249,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX2_FLAGS|CpuAVX_IFMA" },
{ "CPU_AVX_VNNI_INT8_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
+ { "CPU_AVX_NE_CONVERT_FLAGS",
+ "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -447,6 +449,8 @@ static initializer cpu_flag_init[] =
"CpuAVX_IFMA" },
{ "CPU_ANY_AVX_VNNI_INT8_FLAGS",
"CpuAVX_VNNI_INT8" },
+ { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
+ "CpuAVX_NE_CONVERT" },
};
static initializer operand_type_init[] =
@@ -650,6 +654,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512_FP16),
BITFIELD (CpuAVX_IFMA),
BITFIELD (CpuAVX_VNNI_INT8),
+ BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index e9c6785898..c5212aaf12 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -213,6 +213,8 @@ enum
CpuAVX_IFMA,
/* Intel AVX VNNI-INT8 Instructions support required. */
CpuAVX_VNNI_INT8,
+ /* Intel AVX NE CONVERT Instructions support required. */
+ CpuAVX_NE_CONVERT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -394,6 +396,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx512_fp16:1;
unsigned int cpuavx_ifma:1;
unsigned int cpuavx_vnni_int8:1;
+ unsigned int cpuavx_ne_convert:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 358a1cffac..f080b12db2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3027,6 +3027,21 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified|
// MOVEDIR instructions end.
+// AVX_NE_CONVERT instructions.
+
+vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
+vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneps2bf16, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16x, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16y, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
+
+// AVX_NE_CONVERT instructions end.
+
// AVX512_BF16 instructions.
vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 04/10] Support Intel CMPccXADD
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (2 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools
gas/ChangeLog:
* NEWS: Support Intel CMPccXADD.
* config/tc-i386.c: Add cmpccxadd.
(build_modrm_byte): Add operations for Vex.VVVV reg
on operand 0 while have memory operand.
* doc/c-i386.texi: Document .cmpccxadd.
* testsuite/gas/i386/i386.exp: Run CMPccXADD tests.
* testsuite/gas/i386/cmpccxadd-inval.s: New test.
* testsuite/gas/i386/cmpccxadd-inval.l: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto.
* testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Mdq): New.
(MOD_VEX_0F38E0_X86_64): Ditto.
(MOD_VEX_0F38E1_X86_64): Ditto.
(MOD_VEX_0F38E2_X86_64): Ditto.
(MOD_VEX_0F38E3_X86_64): Ditto.
(MOD_VEX_0F38E4_X86_64): Ditto.
(MOD_VEX_0F38E5_X86_64): Ditto.
(MOD_VEX_0F38E6_X86_64): Ditto.
(MOD_VEX_0F38E7_X86_64): Ditto.
(MOD_VEX_0F38E8_X86_64): Ditto.
(MOD_VEX_0F38E9_X86_64): Ditto.
(MOD_VEX_0F38EA_X86_64): Ditto.
(MOD_VEX_0F38EB_X86_64): Ditto.
(MOD_VEX_0F38EC_X86_64): Ditto.
(MOD_VEX_0F38ED_X86_64): Ditto.
(MOD_VEX_0F38EE_X86_64): Ditto.
(MOD_VEX_0F38EF_X86_64): Ditto.
(X86_64_VEX_0F38E0): Ditto.
(X86_64_VEX_0F38E1): Ditto.
(X86_64_VEX_0F38E2): Ditto.
(X86_64_VEX_0F38E3): Ditto.
(X86_64_VEX_0F38E4): Ditto.
(X86_64_VEX_0F38E5): Ditto.
(X86_64_VEX_0F38E6): Ditto.
(X86_64_VEX_0F38E7): Ditto.
(X86_64_VEX_0F38E8): Ditto.
(X86_64_VEX_0F38E9): Ditto.
(X86_64_VEX_0F38EA): Ditto.
(X86_64_VEX_0F38EB): Ditto.
(X86_64_VEX_0F38EC): Ditto.
(X86_64_VEX_0F38ED): Ditto.
(X86_64_VEX_0F38EE): Ditto.
(X86_64_VEX_0F38EF): Ditto.
(mod_table): Add MOD_VEX_0F38E0_X86_64, MOD_VEX_0F38E1_X86_64,
MOD_VEX_0F38E2_X86_64, MOD_VEX_0F38E3_X86_64, MOD_VEX_0F38E4_X86_64,
MOD_VEX_0F38E5_X86_64, MOD_VEX_0F38E6_X86_64, MOD_VEX_0F38E7_X86_64,
MOD_VEX_0F38E8_X86_64, MOD_VEX_0F38E9_X86_64, MOD_VEX_0F38EA_X86_64,
MOD_VEX_0F38EB_X86_64, MOD_VEX_0F38EC_X86_64, MOD_VEX_0F38ED_X86_64,
MOD_VEX_0F38EE_X86_64, MOD_VEX_0F38EF_X86_64.
(x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1,
X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4,
X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7,
X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA,
X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED,
X86_64_VEX_0F38EE, X86_64_VEX_0F38EF.
* i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and
CPU_ANY_CMPCCXADD_FLAGS.
(cpu_flags): Add CpuCMPCCXADD.
* i386-init.h: Regenerated.
* i386-opc.h (CpuCMPCCXADD): New.
(i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0.
* i386-opc.tbl: Add Intel CMPccXADD instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 7 +
gas/doc/c-i386.texi | 2 +
gas/testsuite/gas/i386/cmpccxadd-inval.l | 5 +
gas/testsuite/gas/i386/cmpccxadd-inval.s | 9 +
gas/testsuite/gas/i386/i386.exp | 3 +
.../gas/i386/x86-64-cmpccxadd-intel.d | 266 ++++
gas/testsuite/gas/i386/x86-64-cmpccxadd.d | 266 ++++
gas/testsuite/gas/i386/x86-64-cmpccxadd.s | 263 ++++
opcodes/i386-dis.c | 227 ++-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 130 +-
opcodes/i386-opc.h | 5 +-
opcodes/i386-opc.tbl | 6 +
opcodes/i386-tbl.h | 1282 ++++++++++++-----
15 files changed, 2018 insertions(+), 460 deletions(-)
create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.l
create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.d
create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.s
diff --git a/gas/NEWS b/gas/NEWS
index d5e06bd1de..9757209a9f 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel CMPccXADD instructions.
+
* Add support for Intel AVX-NE-CONVERT instructions.
* Add support for Intel AVX-VNNI-INT8 instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 42579bb701..f887074e60 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
+ SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
};
#undef SUBARCH
@@ -8568,6 +8569,12 @@ build_modrm_byte (void)
gas_assert (mem == (vex_reg + 1)
&& op < i.operands);
}
+ else if (i.tm.opcode_modifier.swapsources)
+ {
+ /* Set Vex_reg as operand 0. */
+ vex_reg = op++;
+ gas_assert(vex_reg < i.operands);
+ }
else
{
vex_reg = op + 1;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index f70994eca8..24ea55579e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -197,6 +197,7 @@ accept various extension mnemonics. For example,
@code{avx_ifma},
@code{avx_vnni_int8},
@code{avx_ne_convert},
+@code{cmpccxadd},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1490,6 +1491,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
+@item @samp{.cmpccxadd}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.l b/gas/testsuite/gas/i386/cmpccxadd-inval.l
new file mode 100644
index 0000000000..32538867aa
--- /dev/null
+++ b/gas/testsuite/gas/i386/cmpccxadd-inval.l
@@ -0,0 +1,5 @@
+.* Assembler messages:
+.*:6: Error: `cmpbexadd' is only supported in 64-bit mode
+.*:7: Error: `cmpbxadd' is only supported in 64-bit mode
+.*:8: Error: `cmplexadd' is only supported in 64-bit mode
+.*:9: Error: `cmplxadd' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.s b/gas/testsuite/gas/i386/cmpccxadd-inval.s
new file mode 100644
index 0000000000..a349628863
--- /dev/null
+++ b/gas/testsuite/gas/i386/cmpccxadd-inval.s
@@ -0,0 +1,9 @@
+# Check Illegal CMPccXADD instructions
+
+ .allow_index_reg
+ .text
+_start:
+ cmpbexadd %eax, %eax, 0x10000000(%esp, %esi, 8)
+ cmpbxadd %ebx, %ebx, (%ecx)
+ cmplexadd %eax, %eax, 508(%ecx)
+ cmplxadd %ebx, %ebx, -512(%edx)
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index d03c2187ea..fb2e2aa446 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -485,6 +485,7 @@ if [gas_32_check] then {
run_dump_test "avx-vnni-int8-intel"
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
+ run_list_test "cmpccxadd-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1159,6 +1160,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx-vnni-int8-intel"
run_dump_test "x86-64-avx-ne-convert"
run_dump_test "x86-64-avx-ne-convert-intel"
+ run_dump_test "x86-64-cmpccxadd"
+ run_dump_test "x86-64-cmpccxadd-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
new file mode 100644
index 0000000000..0b906330b7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
@@ -0,0 +1,266 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 CMPCCXADD insns (Intel disassembly)
+#source: x86-64-cmpccxadd.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
new file mode 100644
index 0000000000..b24af38d1c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
@@ -0,0 +1,266 @@
+#as:
+#objdump: -dw
+#name: x86_64 CMPCCXADD insns
+#source: x86-64-cmpccxadd.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.s b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s
new file mode 100644
index 0000000000..f2eb84a1a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s
@@ -0,0 +1,263 @@
+# Check 64bit CMPccXADD instructions
+
+ .allow_index_reg
+ .text
+_start:
+ cmpbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpbexadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpbexadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpbxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpbxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmplexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmplexadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmplexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmplexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmplexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmplexadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmplexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmplexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmplxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmplxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmplxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmplxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmplxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmplxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmplxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmplxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnbexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnbexadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnbexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnbexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnbexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnbexadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnbexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnbexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnbxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnbxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnbxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnbxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnbxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnbxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnbxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnbxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnlexadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnlexadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnlexadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnlexadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnlexadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnlexadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnlexadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnlexadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnlxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnlxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnlxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnlxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnlxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnlxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnlxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnlxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnoxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnoxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnpxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnpxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnpxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnpxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnpxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnpxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnpxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnpxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnsxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnsxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpnzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnzxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpnzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpnzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpnzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpnzxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpnzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpnzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpoxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpoxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpoxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpoxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpoxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpoxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpoxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpoxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmppxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmppxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmppxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmppxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmppxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmppxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmppxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmppxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpsxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpsxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpsxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpsxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpsxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpsxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpsxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpsxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+ cmpzxadd %eax, %ecx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpzxadd %ebx, %ecx, (%r9) #CMPCCXADD
+ cmpzxadd %eax, %ecx, 508(%rcx) #CMPCCXADD Disp32(fc010000)
+ cmpzxadd %ebx, %ecx, -512(%rdx) #CMPCCXADD Disp32(00feffff)
+ cmpzxadd %rax, %rcx, 0x10000000(%rbp, %r14, 8) #CMPCCXADD
+ cmpzxadd %rbx, %rcx, (%r9) #CMPCCXADD
+ cmpzxadd %rax, %rcx, 1016(%rcx) #CMPCCXADD Disp32(f8030000)
+ cmpzxadd %rbx, %rcx, -1024(%rdx) #CMPCCXADD Disp32(00fcffff)
+
+.intel_syntax noprefix
+ cmpbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmplexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmplexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmplexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmplexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmplexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmplexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmplexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmplexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmplxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmplxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmplxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmplxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmplxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmplxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmplxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmplxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnbexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnbexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnbexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnbexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnbexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnbexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnbexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnbexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnbxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnbxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnbxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnbxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnbxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnbxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnbxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnbxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnlexadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnlexadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnlexadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnlexadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnlexadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnlexadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnlexadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnlexadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnlxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnlxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnlxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnlxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnlxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnlxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnlxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnlxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnpxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnpxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnpxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnpxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnpxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnpxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnpxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnpxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpnzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpnzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpnzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpnzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpnzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpnzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpnzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpnzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpoxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpoxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpoxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpoxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpoxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpoxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpoxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpoxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmppxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmppxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmppxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmppxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmppxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmppxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmppxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmppxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpsxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpsxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpsxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpsxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpsxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpsxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpsxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpsxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
+ cmpzxadd DWORD PTR [rbp+r14*8+0x10000000], ecx, eax #CMPCCXADD
+ cmpzxadd DWORD PTR [r9], ecx, ebx #CMPCCXADD
+ cmpzxadd DWORD PTR [rcx+508], ecx, eax #CMPCCXADD Disp32(fc010000)
+ cmpzxadd DWORD PTR [rdx-512], ecx, ebx #CMPCCXADD Disp32(00feffff)
+ cmpzxadd QWORD PTR [rbp+r14*8+0x10000000], rcx, rax #CMPCCXADD
+ cmpzxadd QWORD PTR [r9], rcx, rbx #CMPCCXADD
+ cmpzxadd QWORD PTR [rcx+1016], rcx, rax #CMPCCXADD Disp32(f8030000)
+ cmpzxadd QWORD PTR [rdx-1024], rcx, rbx #CMPCCXADD Disp32(00fcffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index c83c2a91ce..c68fbcdbb5 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Ma { OP_M, a_mode }
#define Mb { OP_M, b_mode }
#define Md { OP_M, d_mode }
+#define Mdq { OP_M, dq_mode }
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
@@ -939,6 +940,22 @@ enum
MOD_VEX_0F388E,
MOD_VEX_0F38B0,
MOD_VEX_0F38B1,
+ MOD_VEX_0F38E0_X86_64,
+ MOD_VEX_0F38E1_X86_64,
+ MOD_VEX_0F38E2_X86_64,
+ MOD_VEX_0F38E3_X86_64,
+ MOD_VEX_0F38E4_X86_64,
+ MOD_VEX_0F38E5_X86_64,
+ MOD_VEX_0F38E6_X86_64,
+ MOD_VEX_0F38E7_X86_64,
+ MOD_VEX_0F38E8_X86_64,
+ MOD_VEX_0F38E9_X86_64,
+ MOD_VEX_0F38EA_X86_64,
+ MOD_VEX_0F38EB_X86_64,
+ MOD_VEX_0F38EC_X86_64,
+ MOD_VEX_0F38ED_X86_64,
+ MOD_VEX_0F38EE_X86_64,
+ MOD_VEX_0F38EF_X86_64,
MOD_VEX_0F3A30_L_0,
MOD_VEX_0F3A31_L_0,
MOD_VEX_0F3A32_L_0,
@@ -1281,7 +1298,23 @@ enum
X86_64_VEX_0F3849,
X86_64_VEX_0F384B,
X86_64_VEX_0F385C,
- X86_64_VEX_0F385E
+ X86_64_VEX_0F385E,
+ X86_64_VEX_0F38E0,
+ X86_64_VEX_0F38E1,
+ X86_64_VEX_0F38E2,
+ X86_64_VEX_0F38E3,
+ X86_64_VEX_0F38E4,
+ X86_64_VEX_0F38E5,
+ X86_64_VEX_0F38E6,
+ X86_64_VEX_0F38E7,
+ X86_64_VEX_0F38E8,
+ X86_64_VEX_0F38E9,
+ X86_64_VEX_0F38EA,
+ X86_64_VEX_0F38EB,
+ X86_64_VEX_0F38EC,
+ X86_64_VEX_0F38ED,
+ X86_64_VEX_0F38EE,
+ X86_64_VEX_0F38EF,
};
enum
@@ -4383,6 +4416,102 @@ static const struct dis386 x86_64_table[][2] = {
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
},
+
+ /* X86_64_VEX_0F38E0 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E0_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E1 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E1_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E2 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E2_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E3 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E3_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E4 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E4_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E5 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E5_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E6 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E6_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E7 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E7_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E8 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E8_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38E9 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38E9_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38EA */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38EA_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38EB */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38EB_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38EC */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38EC_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38ED */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38ED_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38EE */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38EE_X86_64) },
+ },
+
+ /* X86_64_VEX_0F38EF */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F38EF_X86_64) },
+ },
};
static const struct dis386 three_byte_table[][256] = {
@@ -6394,23 +6523,23 @@ static const struct dis386 vex_table[][256] = {
{ "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
{ "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
/* e0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F38E0) },
+ { X86_64_TABLE (X86_64_VEX_0F38E1) },
+ { X86_64_TABLE (X86_64_VEX_0F38E2) },
+ { X86_64_TABLE (X86_64_VEX_0F38E3) },
+ { X86_64_TABLE (X86_64_VEX_0F38E4) },
+ { X86_64_TABLE (X86_64_VEX_0F38E5) },
+ { X86_64_TABLE (X86_64_VEX_0F38E6) },
+ { X86_64_TABLE (X86_64_VEX_0F38E7) },
/* e8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F38E8) },
+ { X86_64_TABLE (X86_64_VEX_0F38E9) },
+ { X86_64_TABLE (X86_64_VEX_0F38EA) },
+ { X86_64_TABLE (X86_64_VEX_0F38EB) },
+ { X86_64_TABLE (X86_64_VEX_0F38EC) },
+ { X86_64_TABLE (X86_64_VEX_0F38ED) },
+ { X86_64_TABLE (X86_64_VEX_0F38EE) },
+ { X86_64_TABLE (X86_64_VEX_0F38EF) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
/* MOD_VEX_0F38B1*/
{ VEX_W_TABLE (VEX_W_0F38B1) },
},
+ {
+ /* MOD_VEX_0F38E0_X86_64 */
+ { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E1_X86_64 */
+ { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E2_X86_64 */
+ { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E3_X86_64 */
+ { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E4_X86_64 */
+ { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E5_X86_64 */
+ { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E6_X86_64 */
+ { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E7_X86_64 */
+ { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E8_X86_64 */
+ { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38E9_X86_64 */
+ { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38EA_X86_64 */
+ { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38EB_X86_64 */
+ { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38EC_X86_64 */
+ { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38ED_X86_64 */
+ { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38EE_X86_64 */
+ { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F38EF_X86_64 */
+ { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ },
{
/* MOD_VEX_0F3A30_L_0 */
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index e7f51bef8c..36ff8aa5ff 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -251,6 +251,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
{ "CPU_AVX_NE_CONVERT_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+ { "CPU_CMPCCXADD_FLAGS",
+ "CpuCMPCCXADD" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -451,6 +453,8 @@ static initializer cpu_flag_init[] =
"CpuAVX_VNNI_INT8" },
{ "CPU_ANY_AVX_NE_CONVERT_FLAGS",
"CpuAVX_NE_CONVERT" },
+ { "CPU_ANY_CMPCCXADD_FLAGS",
+ "CpuCMPCCXADD" },
};
static initializer operand_type_init[] =
@@ -655,6 +659,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_IFMA),
BITFIELD (CpuAVX_VNNI_INT8),
BITFIELD (CpuAVX_NE_CONVERT),
+ BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
index c5212aaf12..d29c711531 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -215,6 +215,8 @@ enum
CpuAVX_VNNI_INT8,
/* Intel AVX NE CONVERT Instructions support required. */
CpuAVX_NE_CONVERT,
+ /* Intel CMPccXADD instructions support required. */
+ CpuCMPCCXADD,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -296,7 +298,7 @@ enum
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define CpuUnused (CpuMax + 1)
+// #define CpuUnused (CpuMax + 1)
/* We can check if an instruction is available with array instead
of bitfield. */
@@ -397,6 +399,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_ifma:1;
unsigned int cpuavx_vnni_int8:1;
unsigned int cpuavx_ne_convert:1;
+ unsigned int cpucmpccxadd:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f080b12db2..0732e07d80 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3296,3 +3296,9 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX_VNNI_INT8 instructions end.
+
+// CMPCCXADD instructions.
+
+cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+
+// CMPCCXADD instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 05/10] Add handler for more i386_cpu_flags
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (3 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Kong Lingling
From: Kong Lingling <lingling.kong@intel.com>
gas/ChangeLog:
* config/tc-i386.c (cpu_flags_all_zero): Add new ARRAY_SIZE handle.
(cpu_flags_equal): Ditto.
(cpu_flags_and): Ditto.
(cpu_flags_or): Ditto.
(cpu_flags_and_not): Ditto.
---
gas/config/tc-i386.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f887074e60..81bbf22fec 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1618,6 +1618,10 @@ cpu_flags_all_zero (const union i386_cpu_flags *x)
{
switch (ARRAY_SIZE(x->array))
{
+ case 5:
+ if (x->array[4])
+ return 0;
+ /* Fall through. */
case 4:
if (x->array[3])
return 0;
@@ -1643,6 +1647,10 @@ cpu_flags_equal (const union i386_cpu_flags *x,
{
switch (ARRAY_SIZE(x->array))
{
+ case 5:
+ if (x->array[4] != y->array[4])
+ return 0;
+ /* Fall through. */
case 4:
if (x->array[3] != y->array[3])
return 0;
@@ -1675,6 +1683,9 @@ cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
{
switch (ARRAY_SIZE (x.array))
{
+ case 5:
+ x.array [4] &= y.array [4];
+ /* Fall through. */
case 4:
x.array [3] &= y.array [3];
/* Fall through. */
@@ -1698,6 +1709,9 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
{
switch (ARRAY_SIZE (x.array))
{
+ case 5:
+ x.array [4] |= y.array [4];
+ /* Fall through. */
case 4:
x.array [3] |= y.array [3];
/* Fall through. */
@@ -1721,6 +1735,9 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
{
switch (ARRAY_SIZE (x.array))
{
+ case 5:
+ x.array [4] &= ~y.array [4];
+ /* Fall through. */
case 4:
x.array [3] &= ~y.array [3];
/* Fall through. */
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 06/10] Support Intel RAO-INT
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (4 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Kong Lingling
From: Kong Lingling <lingling.kong@intel.com>
gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint.
* testsuite/gas/i386/i386.exp: Run RAOINT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (MOD_0F38FC): New.
(PREFIX_0F38FC): Ditto.
(mod_table): Add MOD_0F38FC.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and
CPU_ANY_RAOINT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAOINT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAOINT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/raoint-intel.d | 18 +
gas/testsuite/gas/i386/raoint.d | 18 +
gas/testsuite/gas/i386/raoint.s | 15 +
gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 5 +-
opcodes/i386-opc.tbl | 9 +
opcodes/i386-tbl.h | 7902 +++++++++---------
16 files changed, 4391 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/raoint.d
create mode 100644 gas/testsuite/gas/i386/raoint.s
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
diff --git a/gas/NEWS b/gas/NEWS
index 9757209a9f..f352c5ab89 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel RAO-INT instructions.
+
* Add support for Intel CMPccXADD instructions.
* Add support for Intel AVX-NE-CONVERT instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 81bbf22fec..0ca9b43610 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
+ SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 24ea55579e..e15cf7a7aa 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -198,6 +198,7 @@ accept various extension mnemonics. For example,
@code{avx_vnni_int8},
@code{avx_ne_convert},
@code{cmpccxadd},
+@code{raoint},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1491,7 +1492,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd}
+@item @samp{.cmpccxadd} @tab @samp{.raoint}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index fb2e2aa446..1eb0eabb6b 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -486,6 +486,8 @@ if [gas_32_check] then {
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
run_list_test "cmpccxadd-inval"
+ run_dump_test "raoint"
+ run_dump_test "raoint-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1162,6 +1164,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx-ne-convert-intel"
run_dump_test "x86-64-cmpccxadd"
run_dump_test "x86-64-cmpccxadd-intel"
+ run_dump_test "x86-64-raoint"
+ run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..b50d423a5f
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAOINT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
new file mode 100644
index 0000000000..2c310c5cc7
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAOINT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
new file mode 100644
index 0000000000..63398dfb82
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit AVX-NE-CONVERT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %edx, (%eax) #RAO-INT
+ aand %edx, (%eax) #RAO-INT
+ aor %edx, (%eax) #RAO-INT
+ axor %edx, (%eax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd DWORD PTR [eax], %edx #RAO-INT
+ aand DWORD PTR [eax], %edx #RAO-INT
+ aor DWORD PTR [eax], %edx #RAO-INT
+ axor DWORD PTR [eax], %edx #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..d7de4849a2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAOINT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..711fe48064
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAOINT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..28590626ca
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAOINT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %rdx, (%rax) #RAO-INT
+ aand %rdx, (%rax) #RAO-INT
+ aor %rdx, (%rax) #RAO-INT
+ axor %rdx, (%rax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd QWORD PTR [rax], %rdx #RAO-INT
+ aand QWORD PTR [rax], %rdx #RAO-INT
+ aor QWORD PTR [rax], %rdx #RAO-INT
+ axor QWORD PTR [rax], %rdx #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index c68fbcdbb5..3a990e4e63 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -887,6 +887,7 @@ enum
MOD_0F38F9,
MOD_0F38FA_PREFIX_1,
MOD_0F38FB_PREFIX_1,
+ MOD_0F38FC,
MOD_0F3A0F_PREFIX_1,
MOD_VEX_0F12_PREFIX_0,
@@ -1086,6 +1087,7 @@ enum
PREFIX_0F38F8,
PREFIX_0F38FA,
PREFIX_0F38FB,
+ PREFIX_0F38FC,
PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
@@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
+ /* PREFIX_0F38FC */
+ {
+ { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
+ { "axor", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aand", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aor", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
@@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = {
{ MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = {
{ Bad_Opcode },
{ "encodekey256", { Gd, Ed }, 0 },
},
+ {
+ /* MOD_0F38FC */
+ { PREFIX_TABLE (PREFIX_0F38FC) },
+ },
{
/* MOD_0F3A0F_PREFIX_1 */
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 36ff8aa5ff..5d75646c7e 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
{ "CPU_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_RAOINT_FLAGS",
+ "CpuRAOINT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -455,6 +457,8 @@ static initializer cpu_flag_init[] =
"CpuAVX_NE_CONVERT" },
{ "CPU_ANY_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_ANY_RAOINT_FLAGS",
+ "CpuRAOINT" },
};
static initializer operand_type_init[] =
@@ -660,6 +664,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_VNNI_INT8),
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
+ BITFIELD (CpuRAOINT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index d29c711531..cb6c372203 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -217,6 +217,8 @@ enum
CpuAVX_NE_CONVERT,
/* Intel CMPccXADD instructions support required. */
CpuCMPCCXADD,
+ /* Intel RAO INT Instructions support required. */
+ CpuRAOINT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -298,7 +300,7 @@ enum
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-// #define CpuUnused (CpuMax + 1)
+#define CpuUnused (CpuMax + 1)
/* We can check if an instruction is available with array instead
of bitfield. */
@@ -400,6 +402,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_vnni_int8:1;
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
+ unsigned int cpuraoint:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 0732e07d80..dacafe1e14 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3302,3 +3302,12 @@ vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Che
cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// CMPCCXADD instructions end.
+
+// RAOINT instructions.
+
+aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+
+// RAOINT instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 07/10] Support Intel WRMSRNS
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (5 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Hu, Lin1
From: "Hu, Lin1" <lin1.hu@intel.com>
gas/ChangeLog:
* NEWS: Support Intel WRMSRNS.
* config/tc-i386.c: Add wrmsrns.
* doc/c-i386.texi: Document .wrmsrns.
* testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
* testsuite/gas/i386/wrmsrns-intel.d: New test.
* testsuite/gas/i386/wrmsrns.d: Ditto.
* testsuite/gas/i386/wrmsrns.s: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
(rm_table): New entry for wrmsrns.
* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
and CPU_ANY_WRMSRNS_FLAGS.
(cpu_flags): Add CpuWRMSRNS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuWRMSRNS): New.
(i386_cpu_flags): Add cpuwrmsrns.
* i386-opc.tbl: Add WRMSRNS instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/wrmsrns.d | 12 +
gas/testsuite/gas/i386/wrmsrns.s | 8 +
gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/x86-64-wrmsrns.d | 12 +
opcodes/i386-dis.c | 7 +
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 6 +
opcodes/i386-tbl.h | 7859 +++++++++--------
15 files changed, 4288 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.s
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d
diff --git a/gas/NEWS b/gas/NEWS
index f352c5ab89..2d745dfc31 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel WRMSRNS instructions.
+
* Add support for Intel RAO-INT instructions.
* Add support for Intel CMPccXADD instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 0ca9b43610..a332889f71 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
+ SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index e15cf7a7aa..d8376566be 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -199,6 +199,7 @@ accept various extension mnemonics. For example,
@code{avx_ne_convert},
@code{cmpccxadd},
@code{raoint},
+@code{wrmsrns},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd} @tab @samp{.raoint}
+@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1eb0eabb6b..c924075180 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -488,6 +488,8 @@ if [gas_32_check] then {
run_list_test "cmpccxadd-inval"
run_dump_test "raoint"
run_dump_test "raoint-intel"
+ run_dump_test "wrmsrns"
+ run_dump_test "wrmsrns-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-cmpccxadd-intel"
run_dump_test "x86-64-raoint"
run_dump_test "x86-64-raoint-intel"
+ run_dump_test "x86-64-wrmsrns"
+ run_dump_test "x86-64-wrmsrns-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d
new file mode 100644
index 0000000000..83194511a5
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d
new file mode 100644
index 0000000000..e804adc501
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: i386 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s
new file mode 100644
index 0000000000..a450b0536d
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.s
@@ -0,0 +1,8 @@
+# Check WRMSRNS instructions
+
+ .text
+_start:
+ wrmsrns #WRMSRNS
+
+.intel_syntax noprefix
+ wrmsrns #WRMSRNS
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
new file mode 100644
index 0000000000..2f789ed5df
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
new file mode 100644
index 0000000000..b8535c266a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: x86_64 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 3a990e4e63..064a1bc0ce 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1000,6 +1000,7 @@ enum
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_0_MOD_3_RM_6,
PREFIX_0F01_REG_1_RM_4,
PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6,
@@ -2970,6 +2971,11 @@ static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
+ {
+ { "wrmsrns", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_1_RM_4 */
{
{ Bad_Opcode },
@@ -8733,6 +8739,7 @@ static const struct dis386 rm_table[][8] = {
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
{ "pconfig", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
},
{
/* RM_0F01_REG_1 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 5d75646c7e..0bfccdc7af 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_RAOINT_FLAGS",
"CpuRAOINT" },
+ { "CPU_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -459,6 +461,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_ANY_RAOINT_FLAGS",
"CpuRAOINT" },
+ { "CPU_ANY_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
};
static initializer operand_type_init[] =
@@ -665,6 +669,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAOINT),
+ BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index cb6c372203..90e0591ae2 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -219,6 +219,8 @@ enum
CpuCMPCCXADD,
/* Intel RAO INT Instructions support required. */
CpuRAOINT,
+ /* Intel WRMSRNS Instructions support required */
+ CpuWRMSRNS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -403,6 +405,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
unsigned int cpuraoint:1;
+ unsigned int cpuwrmsrns:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index dacafe1e14..bff32e69c2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3311,3 +3311,9 @@ aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ld
axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
// RAOINT instructions end.
+
+// WRMSRNS instruction.
+
+wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// WRMSRNS instruction end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 08/10] Support Intel MSRLIST
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (6 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Hu, Lin1
From: "Hu, Lin1" <lin1.hu@intel.com>
gas/ChangeLog:
* NEWS: Support Intel MSRLIST.
* config/tc-i386.c: Add msrlist.
* doc/c-i386.texi: Document .msrlist.
* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
* testsuite/gas/i386/msrlist-inval.l: New test.
* testsuite/gas/i386/msrlist-inval.s: Ditto.
* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
* testsuite/gas/i386/x86-64-msrlist.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
(prefix_table): New entry for msrlist.
(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
and CPU_ANY_MSRLIST_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuMSRLIST): New.
(i386_cpu_flags): Add cpumsrlist.
* i386-opc.tbl: Add MSRLIST instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 2 +
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/msrlist-inval.l | 3 +
gas/testsuite/gas/i386/msrlist-inval.s | 7 +
gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 14 +
gas/testsuite/gas/i386/x86-64-msrlist.d | 14 +
gas/testsuite/gas/i386/x86-64-msrlist.s | 11 +
opcodes/i386-dis.c | 17 +
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 516 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7872 +++++++++--------
15 files changed, 4305 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l
create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d
create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s
diff --git a/gas/NEWS b/gas/NEWS
index 2d745dfc31..3246e7e825 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel MSRLIST instructions.
+
* Add support for Intel WRMSRNS instructions.
* Add support for Intel RAO-INT instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a332889f71..c9432e4188 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
+ SUBARCH (msrlist, MSRLIST, MSRLIST, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index d8376566be..49582b29a6 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -200,6 +200,7 @@ accept various extension mnemonics. For example,
@code{cmpccxadd},
@code{raoint},
@code{wrmsrns},
+@code{msrlist},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1494,6 +1495,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
+@item @samp{.msrlist}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index c924075180..5da64b4076 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -490,6 +490,7 @@ if [gas_32_check] then {
run_dump_test "raoint-intel"
run_dump_test "wrmsrns"
run_dump_test "wrmsrns-intel"
+ run_list_test "msrlist-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1170,6 +1171,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-wrmsrns"
run_dump_test "x86-64-wrmsrns-intel"
+ run_dump_test "x86-64-msrlist"
+ run_dump_test "x86-64-msrlist-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l
new file mode 100644
index 0000000000..456f41c38f
--- /dev/null
+++ b/gas/testsuite/gas/i386/msrlist-inval.l
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
+.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s
new file mode 100644
index 0000000000..3c3258a375
--- /dev/null
+++ b/gas/testsuite/gas/i386/msrlist-inval.s
@@ -0,0 +1,7 @@
+# Check Illegal MSRLIST instructions
+
+ .allow_index_reg
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
new file mode 100644
index 0000000000..97a2a60e43
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 MSRLIST insns (Intel disassembly)
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d
new file mode 100644
index 0000000000..64beed7aa3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist.d
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw
+#name: x86_64 MSRLIST insns
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s
new file mode 100644
index 0000000000..ad57451da9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-msrlist.s
@@ -0,0 +1,11 @@
+# Check 64bit MSRLIST instructions
+
+ .allow_index_reg
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
+
+.intel_syntax noprefix
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 064a1bc0ce..0aa41bd5fb 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1281,6 +1281,8 @@ enum
X86_64_E9,
X86_64_EA,
X86_64_0F01_REG_0,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
X86_64_0F01_REG_1,
X86_64_0F01_REG_1_RM_5_PREFIX_2,
X86_64_0F01_REG_1_RM_6_PREFIX_2,
@@ -2974,6 +2976,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
{
{ "wrmsrns", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
},
/* PREFIX_0F01_REG_1_RM_4 */
@@ -4315,6 +4320,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "sgdt", { M }, 0 },
},
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
+ {
+ { Bad_Opcode },
+ { "wrmsrlist", { Skip_MODRM }, 0 },
+ },
+
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
+ {
+ { Bad_Opcode },
+ { "rdmsrlist", { Skip_MODRM }, 0 },
+ },
+
/* X86_64_0F01_REG_1 */
{
{ "sidt{Q|Q}", { M }, 0 },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 0bfccdc7af..435d67711f 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -257,6 +257,8 @@ static initializer cpu_flag_init[] =
"CpuRAOINT" },
{ "CPU_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -463,6 +465,8 @@ static initializer cpu_flag_init[] =
"CpuRAOINT" },
{ "CPU_ANY_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_ANY_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
};
static initializer operand_type_init[] =
@@ -670,6 +674,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAOINT),
BITFIELD (CpuWRMSRNS),
+ BITFIELD (CpuMSRLIST),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 90e0591ae2..75c23aaec6 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -221,6 +221,8 @@ enum
CpuRAOINT,
/* Intel WRMSRNS Instructions support required */
CpuWRMSRNS,
+ /* Intel MSRLIST Instructions support required. */
+ CpuMSRLIST,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -406,6 +408,7 @@ typedef union i386_cpu_flags
unsigned int cpucmpccxadd:1;
unsigned int cpuraoint:1;
unsigned int cpuwrmsrns:1;
+ unsigned int cpumsrlist:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index bff32e69c2..42d6423942 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3317,3 +3317,10 @@ axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_l
wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// WRMSRNS instruction end.
+
+// MSRLIST instructions.
+
+rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// MSRLIST instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/10] Support Intel AMX-FP16
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (7 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
9 siblings, 0 replies; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Cui,Lili
From: "Cui,Lili" <lili.cui@intel.com>
gas/
* NEWS: Add support for Intel AMX-FP16 instruction.
* config/tc-i386.c: Add amx_fp16.
* doc/c-i386.texi: Document .amx_fp16, noamx_fp16.
* testsuite/gas/i386/i386.exp: Add AMX-FP16 tests.
* testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test.
* testsuite/gas/i386/x86-64-amx-fp16.d: Likewise.
* testsuite/gas/i386/x86-64-amx-fp16.s: Likewise.
* testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise.
* testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise.
opcodes/
* i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New.
(VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise.
(VEX_W_0F385C_X86_64_P_3): Likewise.
(prefix_table): Add VEX_W_0F385C_X86_64_P_3.
(vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0.
(vex_w_table): Add VEX_W_0F385C_X86_64_P_3.
(mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0.
* i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS and
CPU_ANY_AMX-FP16_FLAGS.
(CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16.
(cpu_flags): Add CpuAMX-FP16.
* i386-opc.h (enum): Add CpuAMX-FP16.
(i386_cpu_flags): Add cpuamx_fp16.
* i386-opc.tbl: Add Intel AMX-FP16 instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d | 19 +
gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s | 35 +
.../gas/i386/x86-64-amx-fp16-intel.d | 13 +
gas/testsuite/gas/i386/x86-64-amx-fp16.d | 13 +
gas/testsuite/gas/i386/x86-64-amx-fp16.s | 9 +
opcodes/i386-dis.c | 18 +
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 488 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 1 +
opcodes/i386-tbl.h | 7799 +++++++++--------
15 files changed, 4286 insertions(+), 4128 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16.d
create mode 100644 gas/testsuite/gas/i386/x86-64-amx-fp16.s
diff --git a/gas/NEWS b/gas/NEWS
index 3246e7e825..961449545d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel AMX-FP16 instructions.
+
* Add support for Intel MSRLIST instructions.
* Add support for Intel WRMSRNS instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c9432e4188..906e9db9ad 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1076,6 +1076,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
+ SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
SUBARCH (movdiri, MOVDIRI, ANY_MOVDIRI, false),
SUBARCH (movdir64b, MOVDIR64B, ANY_MOVDIR64B, false),
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 49582b29a6..b739d5f32e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -203,6 +203,7 @@ accept various extension mnemonics. For example,
@code{msrlist},
@code{amx_int8},
@code{amx_bf16},
+@code{amx_fp16},
@code{amx_tile},
@code{vmx},
@code{vmfunc},
@@ -1499,7 +1500,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
-@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
+@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16} @tab @samp{.amx_tile}
@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 5da64b4076..9f5fa7f612 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1173,6 +1173,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-wrmsrns-intel"
run_dump_test "x86-64-msrlist"
run_dump_test "x86-64-msrlist-intel"
+ run_dump_test "x86-64-amx-fp16"
+ run_dump_test "x86-64-amx-fp16-intel"
+ run_dump_test "x86-64-amx-fp16-bad"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
new file mode 100644
index 0000000000..a53ebf486d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.d
@@ -0,0 +1,19 @@
+#as:
+#objdump: -drw
+#name: x86_64 Illegal AMX-FP16 insns
+#source: x86-64-amx-fp16-bad.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 d3 5c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*dc 90 90 90 90 90[ ]*fcoml.*
+[ ]*[a-f0-9]+:[ ]*c4 e2 57 5c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*dc 90 90 90 90 90[ ]*fcoml.*
+[ ]*[a-f0-9]+:[ ]*c4 62 53 5c dc[ ]*tdpfp16ps %tmm5,%tmm4,\(bad\)
+[ ]*[a-f0-9]+:[ ]*c4 c2 53 5c dc[ ]*tdpfp16ps %tmm5,\(bad\),%tmm3
+[ ]*[a-f0-9]+:[ ]*c4 e2 33 5c dc[ ]*tdpfp16ps \(bad\),%tmm4,%tmm3
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
new file mode 100644
index 0000000000..da5be1086e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-bad.s
@@ -0,0 +1,35 @@
+# Check Illegal 64bit AMX-FP16 instructions
+
+.text
+ #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.W = 1 (illegal value).
+ .byte 0xc4
+ .byte 0xe2
+ .byte 0xd3
+ .byte 0x5c
+ .byte 0xdc
+ .fill 0x05, 0x01, 0x90
+ #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.L = 1 (illegal value).
+ .byte 0xc4
+ .byte 0xe2
+ .byte 0x57
+ .byte 0x5c
+ .byte 0xdc
+ .fill 0x05, 0x01, 0x90
+ #tdpfp16ps %tmm5,%tmm4,%tmm3 set VEX.R = 0 (illegal value).
+ .byte 0xc4
+ .byte 0x62
+ .byte 0x53
+ .byte 0x5c
+ .byte 0xdc
+ #tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.B = 0 (illegal value).
+ .byte 0xc4
+ .byte 0xc2
+ .byte 0x53
+ .byte 0x5c
+ .byte 0xdc
+ #tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.VVVV = 0110 (illegal value).
+ .byte 0xc4
+ .byte 0xe2
+ .byte 0x33
+ .byte 0x5c
+ .byte 0xdc
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d b/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
new file mode 100644
index 0000000000..497898b760
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp16-intel.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -d -Mintel
+#name: x86_64 AMX-FP16 insns (Intel disassembly)
+#source: x86-64-amx-fp16.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps tmm3,tmm4,tmm5
+[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps tmm3,tmm4,tmm5
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16.d b/gas/testsuite/gas/i386/x86-64-amx-fp16.d
new file mode 100644
index 0000000000..7d3af95a4d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp16.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86_64 AMX-FP16 insns
+#source: x86-64-amx-fp16.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps %tmm5,%tmm4,%tmm3
+[ ]*[a-f0-9]+:[ ]*c4 e2 53 5c dc[ ]*tdpfp16ps %tmm5,%tmm4,%tmm3
diff --git a/gas/testsuite/gas/i386/x86-64-amx-fp16.s b/gas/testsuite/gas/i386/x86-64-amx-fp16.s
new file mode 100644
index 0000000000..5a007904ed
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amx-fp16.s
@@ -0,0 +1,9 @@
+# Check 64bit AMX-FP16 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ tdpfp16ps %tmm5, %tmm4, %tmm3
+
+.intel_syntax noprefix
+ tdpfp16ps tmm3, tmm4, tmm5
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 0aa41bd5fb..60712c7c5b 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -933,6 +933,7 @@ enum
MOD_VEX_0F384B_X86_64_P_3_W_0,
MOD_VEX_0F385A,
MOD_VEX_0F385C_X86_64_P_1_W_0,
+ MOD_VEX_0F385C_X86_64_P_3_W_0,
MOD_VEX_0F385E_X86_64_P_0_W_0,
MOD_VEX_0F385E_X86_64_P_1_W_0,
MOD_VEX_0F385E_X86_64_P_2_W_0,
@@ -1399,6 +1400,7 @@ enum
VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
VEX_LEN_0F385A_M_0,
VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
@@ -1565,6 +1567,7 @@ enum
VEX_W_0F3859,
VEX_W_0F385A_M_0_L_0,
VEX_W_0F385C_X86_64_P_1,
+ VEX_W_0F385C_X86_64_P_3,
VEX_W_0F385E_X86_64_P_0,
VEX_W_0F385E_X86_64_P_1,
VEX_W_0F385E_X86_64_P_2,
@@ -4088,6 +4091,7 @@ static const struct dis386 prefix_table[][4] = {
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
},
/* PREFIX_VEX_0F385E_X86_64 */
@@ -7120,6 +7124,11 @@ static const struct dis386 vex_len_table[][2] = {
{ "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
},
+ /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
+ {
+ { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
+ },
+
/* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
{
{ "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
@@ -7788,6 +7797,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F385C_X86_64_P_1 */
{ MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
},
+ {
+ /* VEX_W_0F385C_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
+ },
{
/* VEX_W_0F385E_X86_64_P_0 */
{ MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
@@ -8610,6 +8623,11 @@ static const struct dis386 mod_table[][2] = {
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
},
+ {
+ /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
+ },
{
/* MOD_VEX_0F385E_X86_64_P_0_W_0 */
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 435d67711f..86383ba793 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -319,6 +319,8 @@ static initializer cpu_flag_init[] =
"CPU_AMX_TILE_FLAGS|CpuAMX_INT8" },
{ "CPU_AMX_BF16_FLAGS",
"CPU_AMX_TILE_FLAGS|CpuAMX_BF16" },
+ { "CPU_AMX_FP16_FLAGS",
+ "CPU_AMX_TILE_FLAGS|CpuAMX_FP16" },
{ "CPU_AMX_TILE_FLAGS",
"CpuAMX_TILE" },
{ "CPU_MOVDIRI_FLAGS",
@@ -425,8 +427,10 @@ static initializer cpu_flag_init[] =
"CpuAMX_INT8" },
{ "CPU_ANY_AMX_BF16_FLAGS",
"CpuAMX_BF16" },
+ { "CPU_ANY_AMX_FP16_FLAGS",
+ "CpuAMX_FP16" },
{ "CPU_ANY_AMX_TILE_FLAGS",
- "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16" },
+ "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16|CpuAMX_FP16" },
{ "CPU_ANY_AVX_VNNI_FLAGS",
"CpuAVX_VNNI" },
{ "CPU_ANY_MOVDIRI_FLAGS",
@@ -692,6 +696,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCLDEMOTE),
BITFIELD (CpuAMX_INT8),
BITFIELD (CpuAMX_BF16),
+ BITFIELD (CpuAMX_FP16),
BITFIELD (CpuAMX_TILE),
BITFIELD (CpuMOVDIRI),
BITFIELD (CpuMOVDIR64B),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 75c23aaec6..b548769d75 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -240,6 +240,8 @@ enum
CpuAMX_INT8,
/* AMX-BF16 instructions required */
CpuAMX_BF16,
+ /* AMX-FP16 instructions required */
+ CpuAMX_FP16,
/* AMX-TILE instructions required */
CpuAMX_TILE,
/* GFNI instructions required */
@@ -418,6 +420,7 @@ typedef union i386_cpu_flags
unsigned int cpushstk:1;
unsigned int cpuamx_int8:1;
unsigned int cpuamx_bf16:1;
+ unsigned int cpuamx_fp16:1;
unsigned int cpuamx_tile:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 42d6423942..6057664193 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3113,6 +3113,7 @@ ldtilecfg, 0x49, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|No_bSuf|N
sttilecfg, 0x6649, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
tdpbf16ps, 0xf35c, None, CpuAMX_BF16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
+tdpfp16ps, 0xf25c, None, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
tdpbssd, 0xf25e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
tdpbuud, 0x5e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
tdpbusd, 0x665e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 10/10] Support Intel PREFETCHI
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
` (8 preceding siblings ...)
2022-10-19 15:15 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
@ 2022-10-19 15:15 ` Haochen Jiang
2022-10-25 7:11 ` Jan Beulich
9 siblings, 1 reply; 15+ messages in thread
From: Haochen Jiang @ 2022-10-19 15:15 UTC (permalink / raw)
To: binutils; +Cc: jbeulich, hjl.tools, Cui, Lili
From: "Cui, Lili" <lili.cui@intel.com>
gas/
* NEWS: Add support for Intel PREFETCHI instruction.
* config/tc-i386.c: Add prefetchi.
* doc/c-i386.texi: Document .prefetchi.
* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
* testsuite/gas/i386/x86-64-prefetchi-intel.d: New test.
* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.
* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.
opcodes/
* i386-dis.c (MOD_0F18_REG_6): New.
(MOD_0F18_REG_7): Ditto.
(X86_64_MOD_0F18_REG_6): Ditto.
(X86_64_MOD_0F18_REG_7): Ditto.
(x86_64_table): Add X86_64_MOD_0F18_REG_6 and X86_64_MOD_0F18_REG_7.
(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
(PREFETCHI_Fixup): New.
* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS and
CPU_ANY_PREFETCHI_FLAGS.
(cpu_flags): Add CpuPREFETCHI.
* i386-opc.h (CpuPREFETCHI): New.
(i386_cpu_flags): Add cpuprefetchi.
* i386-opc.tbl: Add Intel PREFETCHI instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 4 +-
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/x86-64-lfence-load.d | 2 +
gas/testsuite/gas/i386/x86-64-lfence-load.s | 2 +
.../gas/i386/x86-64-prefetchi-intel.d | 16 +
.../i386/x86-64-prefetchi-inval-register.d | 13 +
.../i386/x86-64-prefetchi-inval-register.s | 9 +
gas/testsuite/gas/i386/x86-64-prefetchi.d | 15 +
gas/testsuite/gas/i386/x86-64-prefetchi.s | 14 +
opcodes/i386-dis.c | 46 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 524 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7876 +++++++++--------
17 files changed, 4362 insertions(+), 4182 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s
diff --git a/gas/NEWS b/gas/NEWS
index 961449545d..5eb479f5a1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel PREFETCHI instructions.
+
* Add support for Intel AMX-FP16 instructions.
* Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 906e9db9ad..4312ffb4a9 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
SUBARCH (msrlist, MSRLIST, MSRLIST, false),
+ SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
};
#undef SUBARCH
@@ -4522,7 +4523,8 @@ load_insn_p (void)
{
/* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
- bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
+ bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
+ prefetchit1. */
if (i.tm.opcode_modifier.anysize)
return 0;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index b739d5f32e..08fe718de0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -201,6 +201,7 @@ accept various extension mnemonics. For example,
@code{raoint},
@code{wrmsrns},
@code{msrlist},
+@code{prefetchi},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
-@item @samp{.msrlist}
+@item @samp{.msrlist} @tab @samp{.prefetchi}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9f5fa7f612..80bd2835ca 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1209,6 +1209,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-tdx"
run_dump_test "x86-64-tsxldtrk"
run_dump_test "x86-64-hreset"
+ run_dump_test "x86-64-prefetchi"
+ run_dump_test "x86-64-prefetchi-intel"
+ run_dump_test "x86-64-prefetchi-inval-register"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
index 2af86fc93f..17c3b9f286 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
@@ -33,6 +33,8 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+ +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
index 2a3ac6b7d2..c478082416 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
@@ -20,6 +20,8 @@ _start:
prefetcht1 (%rbp)
prefetcht2 (%rbp)
prefetchw (%rbp)
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
pop %fs
popf
xlatb (%rbx)
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
new file mode 100644
index 0000000000..7f72f0a1eb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 PREFETCHI insns (Intel disassembly)
+#source: x86-64-prefetchi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
new file mode 100644
index 0000000000..b29b1ae237
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI INVAL REGISTER insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <\.text>:
+[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\)
+[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
new file mode 100644
index 0000000000..550449a0c9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
@@ -0,0 +1,9 @@
+.text
+ #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x39
+ #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x31
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d
new file mode 100644
index 0000000000..c8ab92d147
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s
new file mode 100644
index 0000000000..cc7c61e9a9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s
@@ -0,0 +1,14 @@
+# Check 64bit PREFETCHI instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
+
+ .intel_syntax noprefix
+
+ prefetchit0 BYTE PTR [rip+0x12345678]
+ prefetchit1 BYTE PTR [rip+0x12345678]
+
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 60712c7c5b..11a471dd1a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
static void MOVSXD_Fixup (instr_info *, int, int);
static void DistinctDest_Fixup (instr_info *, int, int);
+static void PREFETCHI_Fixup (instr_info *, int, int);
/* This character is used to encode style information within the output
buffers. See oappend_insert_style for more details. */
@@ -841,6 +842,8 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
+ MOD_0F18_REG_6,
+ MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
@@ -1297,6 +1300,8 @@ enum
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
+ X86_64_MOD_0F18_REG_6,
+ X86_64_MOD_0F18_REG_7,
X86_64_0F24,
X86_64_0F26,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -2768,8 +2773,8 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_3) },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
+ { MOD_TABLE (MOD_0F18_REG_6) },
+ { MOD_TABLE (MOD_0F18_REG_7) },
},
/* REG_0F1C_P_0_MOD_0 */
{
@@ -4414,6 +4419,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "psmash", { Skip_MODRM }, 0 },
},
+ /* X86_64_MOD_0F18_REG_6 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
+ /* X86_64_MOD_0F18_REG_7 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
{
/* X86_64_0F24 */
{ "movZ", { Em, Td }, 0 },
@@ -8213,6 +8230,16 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F18_REG_6 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_6) },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_7 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_7) },
+ { "nopQ", { Ev }, 0 },
+ },
{
/* MOD_0F1A_PREFIX_0 */
{ "bndldx", { Gbnd, Mv_bnd }, 0 },
@@ -14028,3 +14055,18 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
oappend (ins, "sae}");
}
+
+static void
+PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
+{
+ if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
+ {
+ if (ins->intel_syntax)
+ ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
+ else
+ ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
+ bytemode = v_mode;
+ }
+
+ OP_M (ins, bytemode, sizeflag);
+}
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 86383ba793..2ec503aebc 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
"CpuWRMSRNS" },
{ "CPU_MSRLIST_FLAGS",
"CpuMSRLIST" },
+ { "CPU_PREFETCHI_FLAGS",
+ "CpuPREFETCHI"},
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -471,6 +473,8 @@ static initializer cpu_flag_init[] =
"CpuWRMSRNS" },
{ "CPU_ANY_MSRLIST_FLAGS",
"CpuMSRLIST" },
+ { "CPU_ANY_PREFETCHI_FLAGS",
+ "CpuPREFETCHI" },
};
static initializer operand_type_init[] =
@@ -679,6 +683,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuRAOINT),
BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMSRLIST),
+ BITFIELD (CpuPREFETCHI),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index b548769d75..9252627612 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -223,6 +223,8 @@ enum
CpuWRMSRNS,
/* Intel MSRLIST Instructions support required. */
CpuMSRLIST,
+ /* PREFETCHI instruction required */
+ CpuPREFETCHI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
unsigned int cpuraoint:1;
unsigned int cpuwrmsrns:1;
unsigned int cpumsrlist:1;
+ unsigned int cpuprefetchi:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 6057664193..3d9d649c11 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3325,3 +3325,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// MSRLIST instructions end.
+
+// PREFETCHI instructions.
+
+prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+
+// PREFETCHI instructions end.
--
2.18.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 10/10] Support Intel PREFETCHI
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
@ 2022-10-25 7:11 ` Jan Beulich
2022-10-25 7:49 ` Cui, Lili
0 siblings, 1 reply; 15+ messages in thread
From: Jan Beulich @ 2022-10-25 7:11 UTC (permalink / raw)
To: Haochen Jiang, Cui, Lili; +Cc: hjl.tools, binutils
On 19.10.2022 17:15, Haochen Jiang wrote:
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> };
>
> #undef SUBARCH
> @@ -4522,7 +4523,8 @@ load_insn_p (void)
> {
> /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
> + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> + prefetchit1. */
> if (i.tm.opcode_modifier.anysize)
> return 0;
>
There's still no change in this file making sure that the new insns are
_only_ accepted with RIP-relative addressing. See my earlier comments.
Jan
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 10/10] Support Intel PREFETCHI
2022-10-25 7:11 ` Jan Beulich
@ 2022-10-25 7:49 ` Cui, Lili
2022-10-25 8:31 ` Jan Beulich
0 siblings, 1 reply; 15+ messages in thread
From: Cui, Lili @ 2022-10-25 7:49 UTC (permalink / raw)
To: Beulich, Jan, Jiang, Haochen; +Cc: hjl.tools, binutils
> On 19.10.2022 17:15, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> > SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> > SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> > SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> > + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> > };
> >
> > #undef SUBARCH
> > @@ -4522,7 +4523,8 @@ load_insn_p (void)
> > {
> > /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> > prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> > - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
> > + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> > + prefetchit1. */
> > if (i.tm.opcode_modifier.anysize)
> > return 0;
> >
>
> There's still no change in this file making sure that the new insns are _only_
> accepted with RIP-relative addressing. See my earlier comments.
>
Hi Jan,
I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.
Lili.
> Jan
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 10/10] Support Intel PREFETCHI
2022-10-25 7:49 ` Cui, Lili
@ 2022-10-25 8:31 ` Jan Beulich
0 siblings, 0 replies; 15+ messages in thread
From: Jan Beulich @ 2022-10-25 8:31 UTC (permalink / raw)
To: Cui, Lili; +Cc: hjl.tools, binutils, Jiang, Haochen
On 25.10.2022 09:49, Cui, Lili wrote:
>> On 19.10.2022 17:15, Haochen Jiang wrote:
>>> --- a/gas/config/tc-i386.c
>>> +++ b/gas/config/tc-i386.c
>>> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
>>> SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
>>> SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
>>> SUBARCH (msrlist, MSRLIST, MSRLIST, false),
>>> + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
>>> };
>>>
>>> #undef SUBARCH
>>> @@ -4522,7 +4523,8 @@ load_insn_p (void)
>>> {
>>> /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
>>> prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
>>> - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
>>> + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
>>> + prefetchit1. */
>>> if (i.tm.opcode_modifier.anysize)
>>> return 0;
>>>
>>
>> There's still no change in this file making sure that the new insns are _only_
>> accepted with RIP-relative addressing. See my earlier comments.
>>
> I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.
Personally I think a warning is too little, but if H.J. agrees with you,
then so be it.
Jan
^ permalink raw reply [flat|nested] 15+ messages in thread