[PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension.

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* [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension.
@ 2023-11-18  6:49 Jin Ma
  2023-11-18  6:53 ` [PATCH v2 01/12] " Jin Ma
                   ` (12 more replies)
  0 siblings, 13 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  6:49 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

V1 -> V2:

V2 adopted the review comments of Nelson and modified the
instructions encoding of vendor: Reuse the instruction
encoding of the "V" extension as much as possible and
remove redundant instructions encoding.

V1:

T-Head has a range of vendor-specific instructions ([2]).
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the "XTheadVector" extension, a collection of
T-Head-specific vector instructions. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the RISC-V
toolchain conventions ([1]).

Here are some things that need to be explained:
The "XTheadVector" extension is not a custom-extension, but
a non-standard non-conforming extension. The encoding space
of the "TheadVector" instructions overlaps with those of
the 'V' extension. This encoding space conflict is not on
purpose, but the result of issues in the past that have
been resolved since. Therefore, the "XTheadVector" extension
and the 'V' extension are in conflict.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
[2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

---
 bfd/elfxx-riscv.c                             |   17 +
 gas/NEWS                                      |    3 +
 gas/config/tc-riscv.c                         |    4 +
 gas/doc/c-riscv.texi                          |   11 +
 .../gas/riscv/x-thead-vector-csr-warn.d       |    3 +
 .../gas/riscv/x-thead-vector-csr-warn.l       |   16 +
 gas/testsuite/gas/riscv/x-thead-vector-csr.d  |   21 +
 gas/testsuite/gas/riscv/x-thead-vector-csr.s  |   13 +
 gas/testsuite/gas/riscv/x-thead-vector-fail.d |    3 +
 gas/testsuite/gas/riscv/x-thead-vector-fail.l |    2 +
 .../gas/riscv/x-thead-vector-zvamo.d          |   81 +
 .../gas/riscv/x-thead-vector-zvamo.s          |   74 +
 gas/testsuite/gas/riscv/x-thead-vector.d      | 1650 ++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s      | 1726 +++++++++++++++++
 include/opcode/riscv-opc.h                    |  328 ++++
 include/opcode/riscv.h                        |    2 +
 opcodes/riscv-dis.c                           |   14 +-
 opcodes/riscv-opc.c                           |  661 +++++++
 18 files changed, 4627 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s

-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 01/12] RISC-V: Add T-Head VECTOR vendor extension.
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
@ 2023-11-18  6:53 ` Jin Ma
  2023-11-18  6:58 ` [PATCH v2 02/12] RISC-V: Add CSRs for " Jin Ma
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  6:53 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions ([2]).
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the "XTheadVector" extension, a collection of
T-Head-specific vector instructions. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the RISC-V
toolchain conventions ([1]).

Here are some things that need to be explained:
The "XTheadVector" extension is not a custom-extension, but
a non-standard non-conforming extension. The encoding space
of the "TheadVector" instructions overlaps with those of
the 'V' extension. This encoding space conflict is not on
purpose, but the result of issues in the past that have
been resolved since. Therefore, the "XTheadVector" extension
and the 'V' extension are in conflict.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
[2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): The
	"XTheadVector" extension and the 'V' extension are in conflict.
	(riscv_multi_subset_supports): Likewise..
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi:
	* testsuite/gas/riscv/x-thead-vector-fail.d: New test.
	* testsuite/gas/riscv/x-thead-vector-fail.l: New test.
	* testsuite/gas/riscv/x-thead-vector.s: New test.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class):
---
 bfd/elfxx-riscv.c                             | 12 ++++++++++++
 gas/NEWS                                      |  3 +++
 gas/doc/c-riscv.texi                          |  5 +++++
 gas/testsuite/gas/riscv/x-thead-vector-fail.d |  3 +++
 gas/testsuite/gas/riscv/x-thead-vector-fail.l |  2 ++
 gas/testsuite/gas/riscv/x-thead-vector.s      |  0
 include/opcode/riscv.h                        |  1 +
 7 files changed, 26 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9acf124626..e2c3ffe4b4f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1373,6 +1373,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadvector",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -1984,6 +1985,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 	(_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension"));
       no_conflict = false;
     }
+  if (riscv_lookup_subset (rps->subset_list, "xtheadvector", &subset)
+      && riscv_lookup_subset (rps->subset_list, "v", &subset))
+    {
+      rps->error_handler
+	(_("`xtheadvector' is conflict with the `v' extension"));
+      no_conflict = false;
+    }
 
   bool support_zve = false;
   bool support_zvl = false;
@@ -2580,6 +2588,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadmempair");
     case INSN_CLASS_XTHEADSYNC:
       return riscv_subset_supports (rps, "xtheadsync");
+    case INSN_CLASS_XTHEADVECTOR:
+      return riscv_subset_supports (rps, "xtheadvector");
     case INSN_CLASS_XVENTANACONDOPS:
       return riscv_subset_supports (rps, "xventanacondops");
     default:
@@ -2824,6 +2834,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadmempair";
     case INSN_CLASS_XTHEADSYNC:
       return "xtheadsync";
+    case INSN_CLASS_XTHEADVECTOR:
+      return "xtheadvector";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/NEWS b/gas/NEWS
index 9d0fb3b63d0..53b87593f71 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -31,6 +31,9 @@
 
 * Add support for Cortex-X4 for AArch64.
 
+* Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg
+  and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual.
+
 Changes in 2.41:
 
 * Add support for the KVX instruction set.
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index b23504648bd..a7c9420bd86 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -814,6 +814,11 @@ The XTheadSync extension provides instructions for multi-processor synchronizati
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 
+@item XTheadVector
+The XTheadVector extension provides instructions for thead vector.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}.
+
 @item XVentanaCondOps
 XVentanaCondOps extension provides instructions for branchless
 sequences that perform conditional arithmetic, conditional
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.d b/gas/testsuite/gas/riscv/x-thead-vector-fail.d
new file mode 100644
index 00000000000..ac99c3f5398
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64gcv_xtheadvector
+#source: x-thead-vector.s
+#error_output: x-thead-vector-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.l b/gas/testsuite/gas/riscv/x-thead-vector-fail.l
new file mode 100644
index 00000000000..7dd88e317ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.l
@@ -0,0 +1,2 @@
+Assembler messages:
+Error: `xtheadvector' is conflict with the `v' extension
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 710a9b73189..a26ef8abf12 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -467,6 +467,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADMEMIDX,
   INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
+  INSN_CLASS_XTHEADVECTOR,
   INSN_CLASS_XVENTANACONDOPS,
 };
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 02/12] RISC-V: Add CSRs for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
  2023-11-18  6:53 ` [PATCH v2 01/12] " Jin Ma
@ 2023-11-18  6:58 ` Jin Ma
  2023-11-18  7:04 ` [PATCH v2 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
                   ` (10 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  6:58 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the CSRs for XTheadVector. Because of the
conflict between encoding and teh 'V' extension, it is implemented
by alias. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add the class for
	the CSRs of the "XTheadVector" extension.
	(riscv_csr_address): Likewise.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
---
 gas/config/tc-riscv.c                         |  4 ++++
 .../gas/riscv/x-thead-vector-csr-warn.d       |  3 +++
 .../gas/riscv/x-thead-vector-csr-warn.l       | 16 ++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector-csr.d  | 21 +++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector-csr.s  | 13 ++++++++++++
 include/opcode/riscv-opc.h                    |  7 +++++++
 opcodes/riscv-dis.c                           | 14 +++++++++++--
 7 files changed, 76 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 402c46ad753..af9a34a2185 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -91,6 +91,7 @@ enum riscv_csr_class
   CSR_CLASS_SSTC_AND_H,		/* Sstc only (with H) */
   CSR_CLASS_SSTC_32,		/* Sstc RV32 only */
   CSR_CLASS_SSTC_AND_H_32,	/* Sstc RV32 only (with H) */
+  CSR_CLASS_XTHEADVECTOR,	/* xtheadvector only */
 };
 
 /* This structure holds all restricted conditions for a CSR.  */
@@ -1104,6 +1105,9 @@ riscv_csr_address (const char *csr_name,
       break;
     case CSR_CLASS_DEBUG:
       break;
+    case CSR_CLASS_XTHEADVECTOR:
+      extension = "xtheadvector";
+      break;
     default:
       as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
     }
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
new file mode 100644
index 00000000000..17c707ddc7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
@@ -0,0 +1,3 @@
+#as: -march=rv64gc -mcsr-check
+#source: x-thead-vector-csr.s
+#warning_output: x-thead-vector-csr-warn.l
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
new file mode 100644
index 00000000000..4dd867ce2ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
@@ -0,0 +1,16 @@
+.*Assembler messages:
+.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vl,a0'
+.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vtype,a0'
+.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vlenb,a0'
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.d b/gas/testsuite/gas/riscv/x-thead-vector-csr.d
new file mode 100644
index 00000000000..75357b204cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.d
@@ -0,0 +1,21 @@
+#as: -march=rv32if_xtheadvector
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+00802573[ 	]+csrr[ 	]+a0,th.vstart
+[ 	]+[0-9a-f]+:[ 	]+00902573[ 	]+csrr[ 	]+a0,th.vxsat
+[ 	]+[0-9a-f]+:[ 	]+00a02573[ 	]+csrr[ 	]+a0,th.vxrm
+[ 	]+[0-9a-f]+:[ 	]+c2002573[ 	]+csrr[ 	]+a0,th.vl
+[ 	]+[0-9a-f]+:[ 	]+c2102573[ 	]+csrr[ 	]+a0,th.vtype
+[ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,th.vlenb
+[ 	]+[0-9a-f]+:[ 	]+00851073[ 	]+csrw[ 	]+th.vstart,a0
+[ 	]+[0-9a-f]+:[ 	]+00951073[ 	]+csrw[ 	]+th.vxsat,a0
+[ 	]+[0-9a-f]+:[ 	]+00a51073[ 	]+csrw[ 	]+th.vxrm,a0
+[ 	]+[0-9a-f]+:[ 	]+c2051073[ 	]+csrw[ 	]+th.vl,a0
+[ 	]+[0-9a-f]+:[ 	]+c2151073[ 	]+csrw[ 	]+th.vtype,a0
+[ 	]+[0-9a-f]+:[ 	]+c2251073[ 	]+csrw[ 	]+th.vlenb,a0
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.s b/gas/testsuite/gas/riscv/x-thead-vector-csr.s
new file mode 100644
index 00000000000..e11f87f1a07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.s
@@ -0,0 +1,13 @@
+	csrr a0, th.vstart
+	csrr a0, th.vxsat
+	csrr a0, th.vxrm
+	csrr a0, th.vl
+	csrr a0, th.vtype
+	csrr a0, th.vlenb
+
+	csrw th.vstart, a0
+	csrw th.vxsat, a0
+	csrw th.vxrm, a0
+	csrw th.vl, a0		# read-only CSR
+	csrw th.vtype, a0	# read-only CSR
+	csrw th.vlenb, a0	# read-only CSR
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..ed29384e825 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -4121,4 +4121,11 @@ DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
 DECLARE_CSR_ALIAS(tmexttrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Unprivileged T-Head Vector CSRs.  */
+DECLARE_CSR_ALIAS(th.vstart, CSR_VSTART, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vxsat, CSR_VXSAT, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vxrm, CSR_VXRM, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vl, CSR_VL, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vtype, CSR_VTYPE, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vlenb, CSR_VLENB, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 #endif /* DECLARE_CSR_ALIAS */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca328b4c997..2d7c154cc3d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -568,8 +568,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      }
 
 	    if (riscv_csr_hash[csr] != NULL)
-	      print (info->stream, dis_style_register, "%s",
-		     riscv_csr_hash[csr]);
+	      if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector")
+		  && (csr == CSR_VSTART
+		      || csr == CSR_VXSAT
+		      || csr == CSR_VXRM
+		      || csr == CSR_VL
+		      || csr == CSR_VTYPE
+		      || csr == CSR_VLENB))
+		print (info->stream, dis_style_register, "%s",
+		       concat ("th.", riscv_csr_hash[csr], NULL));
+	      else
+		print (info->stream, dis_style_register, "%s",
+		       riscv_csr_hash[csr]);
 	    else
 	      print (info->stream, dis_style_immediate, "0x%x", csr);
 	    break;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 03/12] RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
  2023-11-18  6:53 ` [PATCH v2 01/12] " Jin Ma
  2023-11-18  6:58 ` [PATCH v2 02/12] RISC-V: Add CSRs for " Jin Ma
@ 2023-11-18  7:04 ` Jin Ma
  2023-11-18  7:04 ` [PATCH v2 04/12] RISC-V: Add load/store " Jin Ma
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:04 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds configuration-setting instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: New test.
	* testsuite/gas/riscv/x-thead-vector.s: New test.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise..
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s |  3 +++
 opcodes/riscv-opc.c                      |  4 ++++
 3 files changed, 19 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
new file mode 100644
index 00000000000..e509ed0971b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -0,0 +1,12 @@
+#as: -march=rv32if_xtheadvector
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+th.vsetvl[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+th.vsetvli[ 	]+a0,a1,e8,m1,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+th.vsetvli[ 	]+a0,a1,2047
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index e69de29bb2d..ffea0a6f9f9 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -0,0 +1,3 @@
+	th.vsetvl a0, a1, a2
+	th.vsetvli a0, a1, 0
+	th.vsetvli a0, a1, 0x7ff
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 72d727cd77e..4c2a9b5abef 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.sync.is",       0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_IS,       MASK_TH_SYNC_IS,       match_opcode, 0},
 {"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadVector instructions.  */
+{"th.vsetvl",     0, INSN_CLASS_XTHEADVECTOR,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+{"th.vsetvli",    0, INSN_CLASS_XTHEADVECTOR,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
 {"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 04/12] RISC-V: Add load/store instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (2 preceding siblings ...)
  2023-11-18  7:04 ` [PATCH v2 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
@ 2023-11-18  7:04 ` Jin Ma
  2023-11-18  7:05 ` [PATCH v2 05/12] RISC-V: Add load/store segment " Jin Ma
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:04 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	load/store instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLBV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 132 ++++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 136 +++++++++++++++++++++++
 include/opcode/riscv-opc.h               |  33 ++++++
 opcodes/riscv-opc.c                      |  44 ++++++++
 4 files changed, 345 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index e509ed0971b..d7cb1e1a457 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -10,3 +10,135 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+th.vsetvl[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+th.vsetvli[ 	]+a0,a1,e8,m1,tu,mu
 [ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+th.vsetvli[ 	]+a0,a1,2047
+[ 	]+[0-9a-f]+:[ 	]+12050207[ 	]+th.vlb.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+12050207[ 	]+th.vlb.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+10050207[ 	]+th.vlb.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+12055207[ 	]+th.vlh.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+12055207[ 	]+th.vlh.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+10055207[ 	]+th.vlh.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+12056207[ 	]+th.vlw.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+12056207[ 	]+th.vlw.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+10056207[ 	]+th.vlw.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+th.vlbu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+th.vlbu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+th.vlbu.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+th.vlhu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+th.vlhu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00055207[ 	]+th.vlhu.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+th.vlwu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+th.vlwu.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00056207[ 	]+th.vlwu.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+th.vle.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+th.vle.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00057207[ 	]+th.vle.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+th.vsb.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+th.vsb.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00050227[ 	]+th.vsb.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+th.vsh.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+th.vsh.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00055227[ 	]+th.vsh.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+th.vsw.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+th.vsw.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00056227[ 	]+th.vsw.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+th.vse.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+th.vse.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00057227[ 	]+th.vse.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+1ab50207[ 	]+th.vlsb.v[ 	]+v4,\(a0\),a1
+[ 	]+[0-9a-f]+:[ 	]+1ab50207[ 	]+th.vlsb.v[ 	]+v4,\(a0\),a1
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+[ 	]+[0-9a-f]+:[ 	]+1ab56207[ 	]+th.vlsw.v[ 	]+v4,\(a0\),a1
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+[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+th.vlsbu.v[ 	]+v4,\(a0\),a1
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+[ 	]+[0-9a-f]+:[ 	]+1cc57227[ 	]+th.vsuxe.v[ 	]+v4,\(a0\),v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+13050207[ 	]+th.vlbff.v[ 	]+v4,\(a0\)
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+[ 	]+[0-9a-f]+:[ 	]+13055207[ 	]+th.vlhff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+13055207[ 	]+th.vlhff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+11055207[ 	]+th.vlhff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+13056207[ 	]+th.vlwff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+13056207[ 	]+th.vlwff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+11056207[ 	]+th.vlwff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+th.vlbuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+03050207[ 	]+th.vlbuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+01050207[ 	]+th.vlbuff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+03055207[ 	]+th.vlhuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+03055207[ 	]+th.vlhuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+01055207[ 	]+th.vlhuff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+03056207[ 	]+th.vlwuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+03056207[ 	]+th.vlwuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+01056207[ 	]+th.vlwuff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+03057207[ 	]+th.vleff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+03057207[ 	]+th.vleff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+01057207[ 	]+th.vleff.v[ 	]+v4,\(a0\),v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index ffea0a6f9f9..c65e9e8790c 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1,3 +1,139 @@
 	th.vsetvl a0, a1, a2
 	th.vsetvli a0, a1, 0
 	th.vsetvli a0, a1, 0x7ff
+
+	th.vlb.v v4, (a0)
+	th.vlb.v v4, 0(a0)
+	th.vlb.v v4, (a0), v0.t
+	th.vlh.v v4, (a0)
+	th.vlh.v v4, 0(a0)
+	th.vlh.v v4, (a0), v0.t
+	th.vlw.v v4, (a0)
+	th.vlw.v v4, 0(a0)
+	th.vlw.v v4, (a0), v0.t
+	th.vlbu.v v4, (a0)
+	th.vlbu.v v4, 0(a0)
+	th.vlbu.v v4, (a0), v0.t
+	th.vlhu.v v4, (a0)
+	th.vlhu.v v4, 0(a0)
+	th.vlhu.v v4, (a0), v0.t
+	th.vlwu.v v4, (a0)
+	th.vlwu.v v4, 0(a0)
+	th.vlwu.v v4, (a0), v0.t
+	th.vle.v v4, (a0)
+	th.vle.v v4, 0(a0)
+	th.vle.v v4, (a0), v0.t
+	th.vsb.v v4, (a0)
+	th.vsb.v v4, 0(a0)
+	th.vsb.v v4, (a0), v0.t
+	th.vsh.v v4, (a0)
+	th.vsh.v v4, 0(a0)
+	th.vsh.v v4, (a0), v0.t
+	th.vsw.v v4, (a0)
+	th.vsw.v v4, 0(a0)
+	th.vsw.v v4, (a0), v0.t
+	th.vse.v v4, (a0)
+	th.vse.v v4, 0(a0)
+	th.vse.v v4, (a0), v0.t
+
+	th.vlsb.v v4, (a0), a1
+	th.vlsb.v v4, 0(a0), a1
+	th.vlsb.v v4, (a0), a1, v0.t
+	th.vlsh.v v4, (a0), a1
+	th.vlsh.v v4, 0(a0), a1
+	th.vlsh.v v4, (a0), a1, v0.t
+	th.vlsw.v v4, (a0), a1
+	th.vlsw.v v4, 0(a0), a1
+	th.vlsw.v v4, (a0), a1, v0.t
+	th.vlsbu.v v4, (a0), a1
+	th.vlsbu.v v4, 0(a0), a1
+	th.vlsbu.v v4, (a0), a1, v0.t
+	th.vlshu.v v4, (a0), a1
+	th.vlshu.v v4, 0(a0), a1
+	th.vlshu.v v4, (a0), a1, v0.t
+	th.vlswu.v v4, (a0), a1
+	th.vlswu.v v4, 0(a0), a1
+	th.vlswu.v v4, (a0), a1, v0.t
+	th.vlse.v v4, (a0), a1
+	th.vlse.v v4, 0(a0), a1
+	th.vlse.v v4, (a0), a1, v0.t
+	th.vssb.v v4, (a0), a1
+	th.vssb.v v4, 0(a0), a1
+	th.vssb.v v4, (a0), a1, v0.t
+	th.vssh.v v4, (a0), a1
+	th.vssh.v v4, 0(a0), a1
+	th.vssh.v v4, (a0), a1, v0.t
+	th.vssw.v v4, (a0), a1
+	th.vssw.v v4, 0(a0), a1
+	th.vssw.v v4, (a0), a1, v0.t
+	th.vsse.v v4, (a0), a1
+	th.vsse.v v4, 0(a0), a1
+	th.vsse.v v4, (a0), a1, v0.t
+
+	th.vlxb.v v4, (a0), v12
+	th.vlxb.v v4, 0(a0), v12
+	th.vlxb.v v4, (a0), v12, v0.t
+	th.vlxh.v v4, (a0), v12
+	th.vlxh.v v4, 0(a0), v12
+	th.vlxh.v v4, (a0), v12, v0.t
+	th.vlxw.v v4, (a0), v12
+	th.vlxw.v v4, 0(a0), v12
+	th.vlxw.v v4, (a0), v12, v0.t
+	th.vlxbu.v v4, (a0), v12
+	th.vlxbu.v v4, 0(a0), v12
+	th.vlxbu.v v4, (a0), v12, v0.t
+	th.vlxhu.v v4, (a0), v12
+	th.vlxhu.v v4, 0(a0), v12
+	th.vlxhu.v v4, (a0), v12, v0.t
+	th.vlxwu.v v4, (a0), v12
+	th.vlxwu.v v4, 0(a0), v12
+	th.vlxwu.v v4, (a0), v12, v0.t
+	th.vlxe.v v4, (a0), v12
+	th.vlxe.v v4, 0(a0), v12
+	th.vlxe.v v4, (a0), v12, v0.t
+	th.vsxb.v v4, (a0), v12
+	th.vsxb.v v4, 0(a0), v12
+	th.vsxb.v v4, (a0), v12, v0.t
+	th.vsxh.v v4, (a0), v12
+	th.vsxh.v v4, 0(a0), v12
+	th.vsxh.v v4, (a0), v12, v0.t
+	th.vsxw.v v4, (a0), v12
+	th.vsxw.v v4, 0(a0), v12
+	th.vsxw.v v4, (a0), v12, v0.t
+	th.vsxe.v v4, (a0), v12
+	th.vsxe.v v4, 0(a0), v12
+	th.vsxe.v v4, (a0), v12, v0.t
+	th.vsuxb.v v4, (a0), v12
+	th.vsuxb.v v4, 0(a0), v12
+	th.vsuxb.v v4, (a0), v12, v0.t
+	th.vsuxh.v v4, (a0), v12
+	th.vsuxh.v v4, 0(a0), v12
+	th.vsuxh.v v4, (a0), v12, v0.t
+	th.vsuxw.v v4, (a0), v12
+	th.vsuxw.v v4, 0(a0), v12
+	th.vsuxw.v v4, (a0), v12, v0.t
+	th.vsuxe.v v4, (a0), v12
+	th.vsuxe.v v4, 0(a0), v12
+	th.vsuxe.v v4, (a0), v12, v0.t
+
+	th.vlbff.v v4, (a0)
+	th.vlbff.v v4, 0(a0)
+	th.vlbff.v v4, (a0), v0.t
+	th.vlhff.v v4, (a0)
+	th.vlhff.v v4, 0(a0)
+	th.vlhff.v v4, (a0), v0.t
+	th.vlwff.v v4, (a0)
+	th.vlwff.v v4, 0(a0)
+	th.vlwff.v v4, (a0), v0.t
+	th.vlbuff.v v4, (a0)
+	th.vlbuff.v v4, 0(a0)
+	th.vlbuff.v v4, (a0), v0.t
+	th.vlhuff.v v4, (a0)
+	th.vlhuff.v v4, 0(a0)
+	th.vlhuff.v v4, (a0), v0.t
+	th.vlwuff.v v4, (a0)
+	th.vlwuff.v v4, 0(a0)
+	th.vlwuff.v v4, (a0), v0.t
+	th.vleff.v v4, (a0)
+	th.vleff.v v4, 0(a0)
+	th.vleff.v v4, (a0), v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ed29384e825..792958b8925 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2648,6 +2648,39 @@
 #define MASK_TH_SYNC_IS 0xffffffff
 #define MATCH_TH_SYNC_S 0x0190000b
 #define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific (T-Head) XTheadVector instructions.  */
+#define MATCH_TH_VLBV  0x10000007
+#define MASK_TH_VLBV   0xfdf0707f
+#define MATCH_TH_VLHV  0x10005007
+#define MASK_TH_VLHV   0xfdf0707f
+#define MATCH_TH_VLWV  0x10006007
+#define MASK_TH_VLWV   0xfdf0707f
+#define MATCH_TH_VLSBV    0x18000007
+#define MASK_TH_VLSBV     0xfc00707f
+#define MATCH_TH_VLSHV    0x18005007
+#define MASK_TH_VLSHV     0xfc00707f
+#define MATCH_TH_VLSWV    0x18006007
+#define MASK_TH_VLSWV     0xfc00707f
+#define MATCH_TH_VLXBV    0x1c000007
+#define MASK_TH_VLXBV     0xfc00707f
+#define MATCH_TH_VLXHV    0x1c005007
+#define MASK_TH_VLXHV     0xfc00707f
+#define MATCH_TH_VLXWV    0x1c006007
+#define MASK_TH_VLXWV     0xfc00707f
+#define MATCH_TH_VSUXBV   0x1c000027
+#define MASK_TH_VSUXBV    0xfc00707f
+#define MATCH_TH_VSUXHV   0x1c005027
+#define MASK_TH_VSUXHV    0xfc00707f
+#define MATCH_TH_VSUXWV   0x1c006027
+#define MASK_TH_VSUXWV    0xfc00707f
+#define MATCH_TH_VSUXEV   0x1c007027
+#define MASK_TH_VSUXEV    0xfc00707f
+#define MATCH_TH_VLBFFV  0x11000007
+#define MASK_TH_VLBFFV   0xfdf0707f
+#define MATCH_TH_VLHFFV  0x11005007
+#define MASK_TH_VLHFFV   0xfdf0707f
+#define MATCH_TH_VLWFFV  0x11006007
+#define MASK_TH_VLWFFV   0xfdf0707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4c2a9b5abef..54c1e8a62d9 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2237,6 +2237,50 @@ const struct riscv_opcode riscv_opcodes[] =
 /* Vendor-specific (T-Head) XTheadVector instructions.  */
 {"th.vsetvl",     0, INSN_CLASS_XTHEADVECTOR,  "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
 {"th.vsetvli",    0, INSN_CLASS_XTHEADVECTOR,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+{"th.vlb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBV, MASK_TH_VLBV, match_opcode, INSN_DREF },
+{"th.vlh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHV, MASK_TH_VLHV, match_opcode, INSN_DREF },
+{"th.vlw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWV, MASK_TH_VLWV, match_opcode, INSN_DREF },
+{"th.vlbu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
+{"th.vlhu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
+{"th.vlwu.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
+{"th.vle.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
+{"th.vsb.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
+{"th.vsh.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
+{"th.vsw.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
+{"th.vse.v",      0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
+{"th.vlsb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSBV, MASK_TH_VLSBV, match_opcode, INSN_DREF },
+{"th.vlsh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSHV, MASK_TH_VLSHV, match_opcode, INSN_DREF },
+{"th.vlsw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSWV, MASK_TH_VLSWV, match_opcode, INSN_DREF },
+{"th.vlsbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
+{"th.vlshu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
+{"th.vlswu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
+{"th.vlse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
+{"th.vssb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
+{"th.vssh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
+{"th.vssw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
+{"th.vsse.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
+{"th.vlxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXBV, MASK_TH_VLXBV, match_opcode, INSN_DREF },
+{"th.vlxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXHV, MASK_TH_VLXHV, match_opcode, INSN_DREF },
+{"th.vlxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXWV, MASK_TH_VLXWV, match_opcode, INSN_DREF },
+{"th.vlxbu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF },
+{"th.vlxhu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"th.vlxwu.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF },
+{"th.vlxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF },
+{"th.vsxb.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF },
+{"th.vsxh.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF },
+{"th.vsxw.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF },
+{"th.vsxe.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF },
+{"th.vsuxb.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXBV, MASK_TH_VSUXBV, match_opcode, INSN_DREF },
+{"th.vsuxh.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXHV, MASK_TH_VSUXHV, match_opcode, INSN_DREF },
+{"th.vsuxw.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXWV, MASK_TH_VSUXWV, match_opcode, INSN_DREF },
+{"th.vsuxe.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VSUXEV, MASK_TH_VSUXEV, match_opcode, INSN_DREF },
+{"th.vlbff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLBFFV, MASK_TH_VLBFFV, match_opcode, INSN_DREF },
+{"th.vlhff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLHFFV, MASK_TH_VLHFFV, match_opcode, INSN_DREF },
+{"th.vlwff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLWFFV, MASK_TH_VLWFFV, match_opcode, INSN_DREF },
+{"th.vlbuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+{"th.vlhuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+{"th.vlwuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
+{"th.vleff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 05/12] RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (3 preceding siblings ...)
  2023-11-18  7:04 ` [PATCH v2 04/12] RISC-V: Add load/store " Jin Ma
@ 2023-11-18  7:05 ` Jin Ma
  2023-11-18  7:06 ` [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
                   ` (7 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:05 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore it
makes sense to group them into smaller chunks in form of vendor
extensions.

This patch adds provides load/store segment instructions for T-Head VECTOR
vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector
extension, but belongs to the "XTheadVector" extension. The 'th' prefix
and the "XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add test.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 840 ++++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 868 +++++++++++++++++++++++
 include/opcode/riscv-opc.h               | 169 +++++
 opcodes/riscv-opc.c                      | 280 ++++++++
 4 files changed, 2157 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index d7cb1e1a457..90ea839457a 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -142,3 +142,843 @@ Disassembly of section .text:
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+[ 	]+[0-9a-f]+:[ 	]+a1057207[ 	]+th.vlseg6eff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+d3050207[ 	]+th.vlseg7bff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d3050207[ 	]+th.vlseg7bff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d1050207[ 	]+th.vlseg7bff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+d3055207[ 	]+th.vlseg7hff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d3055207[ 	]+th.vlseg7hff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d1055207[ 	]+th.vlseg7hff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+d3056207[ 	]+th.vlseg7wff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d3056207[ 	]+th.vlseg7wff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+d1056207[ 	]+th.vlseg7wff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+c3050207[ 	]+th.vlseg7buff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c3050207[ 	]+th.vlseg7buff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c1050207[ 	]+th.vlseg7buff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+c3055207[ 	]+th.vlseg7huff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c3055207[ 	]+th.vlseg7huff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c1055207[ 	]+th.vlseg7huff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+c3056207[ 	]+th.vlseg7wuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c3056207[ 	]+th.vlseg7wuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c1056207[ 	]+th.vlseg7wuff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+c3057207[ 	]+th.vlseg7eff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c3057207[ 	]+th.vlseg7eff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+c1057207[ 	]+th.vlseg7eff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+f3050207[ 	]+th.vlseg8bff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f3050207[ 	]+th.vlseg8bff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f1050207[ 	]+th.vlseg8bff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+f3055207[ 	]+th.vlseg8hff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f3055207[ 	]+th.vlseg8hff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f1055207[ 	]+th.vlseg8hff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+f3056207[ 	]+th.vlseg8wff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f3056207[ 	]+th.vlseg8wff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+f1056207[ 	]+th.vlseg8wff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+e3050207[ 	]+th.vlseg8buff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e3050207[ 	]+th.vlseg8buff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e1050207[ 	]+th.vlseg8buff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+e3055207[ 	]+th.vlseg8huff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e3055207[ 	]+th.vlseg8huff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e1055207[ 	]+th.vlseg8huff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+e3056207[ 	]+th.vlseg8wuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e3056207[ 	]+th.vlseg8wuff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e1056207[ 	]+th.vlseg8wuff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+e1057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\),v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index c65e9e8790c..d356c016c2f 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -137,3 +137,871 @@
 	th.vleff.v v4, (a0)
 	th.vleff.v v4, 0(a0)
 	th.vleff.v v4, (a0), v0.t
+
+	th.vlseg2b.v v4, (a0)
+	th.vlseg2b.v v4, 0(a0)
+	th.vlseg2b.v v4, (a0), v0.t
+	th.vlseg2h.v v4, (a0)
+	th.vlseg2h.v v4, 0(a0)
+	th.vlseg2h.v v4, (a0), v0.t
+	th.vlseg2w.v v4, (a0)
+	th.vlseg2w.v v4, 0(a0)
+	th.vlseg2w.v v4, (a0), v0.t
+	th.vlseg2bu.v v4, (a0)
+	th.vlseg2bu.v v4, 0(a0)
+	th.vlseg2bu.v v4, (a0), v0.t
+	th.vlseg2hu.v v4, (a0)
+	th.vlseg2hu.v v4, 0(a0)
+	th.vlseg2hu.v v4, (a0), v0.t
+	th.vlseg2wu.v v4, (a0)
+	th.vlseg2wu.v v4, 0(a0)
+	th.vlseg2wu.v v4, (a0), v0.t
+	th.vlseg2e.v v4, (a0)
+	th.vlseg2e.v v4, 0(a0)
+	th.vlseg2e.v v4, (a0), v0.t
+	th.vsseg2b.v v4, (a0)
+	th.vsseg2b.v v4, 0(a0)
+	th.vsseg2b.v v4, (a0), v0.t
+	th.vsseg2h.v v4, (a0)
+	th.vsseg2h.v v4, 0(a0)
+	th.vsseg2h.v v4, (a0), v0.t
+	th.vsseg2w.v v4, (a0)
+	th.vsseg2w.v v4, 0(a0)
+	th.vsseg2w.v v4, (a0), v0.t
+	th.vsseg2e.v v4, (a0)
+	th.vsseg2e.v v4, 0(a0)
+	th.vsseg2e.v v4, (a0), v0.t
+
+	th.vlseg3b.v v4, (a0)
+	th.vlseg3b.v v4, 0(a0)
+	th.vlseg3b.v v4, (a0), v0.t
+	th.vlseg3h.v v4, (a0)
+	th.vlseg3h.v v4, 0(a0)
+	th.vlseg3h.v v4, (a0), v0.t
+	th.vlseg3w.v v4, (a0)
+	th.vlseg3w.v v4, 0(a0)
+	th.vlseg3w.v v4, (a0), v0.t
+	th.vlseg3bu.v v4, (a0)
+	th.vlseg3bu.v v4, 0(a0)
+	th.vlseg3bu.v v4, (a0), v0.t
+	th.vlseg3hu.v v4, (a0)
+	th.vlseg3hu.v v4, 0(a0)
+	th.vlseg3hu.v v4, (a0), v0.t
+	th.vlseg3wu.v v4, (a0)
+	th.vlseg3wu.v v4, 0(a0)
+	th.vlseg3wu.v v4, (a0), v0.t
+	th.vlseg3e.v v4, (a0)
+	th.vlseg3e.v v4, 0(a0)
+	th.vlseg3e.v v4, (a0), v0.t
+	th.vsseg3b.v v4, (a0)
+	th.vsseg3b.v v4, 0(a0)
+	th.vsseg3b.v v4, (a0), v0.t
+	th.vsseg3h.v v4, (a0)
+	th.vsseg3h.v v4, 0(a0)
+	th.vsseg3h.v v4, (a0), v0.t
+	th.vsseg3w.v v4, (a0)
+	th.vsseg3w.v v4, 0(a0)
+	th.vsseg3w.v v4, (a0), v0.t
+	th.vsseg3e.v v4, (a0)
+	th.vsseg3e.v v4, 0(a0)
+	th.vsseg3e.v v4, (a0), v0.t
+
+	th.vlseg4b.v v4, (a0)
+	th.vlseg4b.v v4, 0(a0)
+	th.vlseg4b.v v4, (a0), v0.t
+	th.vlseg4h.v v4, (a0)
+	th.vlseg4h.v v4, 0(a0)
+	th.vlseg4h.v v4, (a0), v0.t
+	th.vlseg4w.v v4, (a0)
+	th.vlseg4w.v v4, 0(a0)
+	th.vlseg4w.v v4, (a0), v0.t
+	th.vlseg4bu.v v4, (a0)
+	th.vlseg4bu.v v4, 0(a0)
+	th.vlseg4bu.v v4, (a0), v0.t
+	th.vlseg4hu.v v4, (a0)
+	th.vlseg4hu.v v4, 0(a0)
+	th.vlseg4hu.v v4, (a0), v0.t
+	th.vlseg4wu.v v4, (a0)
+	th.vlseg4wu.v v4, 0(a0)
+	th.vlseg4wu.v v4, (a0), v0.t
+	th.vlseg4e.v v4, (a0)
+	th.vlseg4e.v v4, 0(a0)
+	th.vlseg4e.v v4, (a0), v0.t
+	th.vsseg4b.v v4, (a0)
+	th.vsseg4b.v v4, 0(a0)
+	th.vsseg4b.v v4, (a0), v0.t
+	th.vsseg4h.v v4, (a0)
+	th.vsseg4h.v v4, 0(a0)
+	th.vsseg4h.v v4, (a0), v0.t
+	th.vsseg4w.v v4, (a0)
+	th.vsseg4w.v v4, 0(a0)
+	th.vsseg4w.v v4, (a0), v0.t
+	th.vsseg4e.v v4, (a0)
+	th.vsseg4e.v v4, 0(a0)
+	th.vsseg4e.v v4, (a0), v0.t
+
+	th.vlseg5b.v v4, (a0)
+	th.vlseg5b.v v4, 0(a0)
+	th.vlseg5b.v v4, (a0), v0.t
+	th.vlseg5h.v v4, (a0)
+	th.vlseg5h.v v4, 0(a0)
+	th.vlseg5h.v v4, (a0), v0.t
+	th.vlseg5w.v v4, (a0)
+	th.vlseg5w.v v4, 0(a0)
+	th.vlseg5w.v v4, (a0), v0.t
+	th.vlseg5bu.v v4, (a0)
+	th.vlseg5bu.v v4, 0(a0)
+	th.vlseg5bu.v v4, (a0), v0.t
+	th.vlseg5hu.v v4, (a0)
+	th.vlseg5hu.v v4, 0(a0)
+	th.vlseg5hu.v v4, (a0), v0.t
+	th.vlseg5wu.v v4, (a0)
+	th.vlseg5wu.v v4, 0(a0)
+	th.vlseg5wu.v v4, (a0), v0.t
+	th.vlseg5e.v v4, (a0)
+	th.vlseg5e.v v4, 0(a0)
+	th.vlseg5e.v v4, (a0), v0.t
+	th.vsseg5b.v v4, (a0)
+	th.vsseg5b.v v4, 0(a0)
+	th.vsseg5b.v v4, (a0), v0.t
+	th.vsseg5h.v v4, (a0)
+	th.vsseg5h.v v4, 0(a0)
+	th.vsseg5h.v v4, (a0), v0.t
+	th.vsseg5w.v v4, (a0)
+	th.vsseg5w.v v4, 0(a0)
+	th.vsseg5w.v v4, (a0), v0.t
+	th.vsseg5e.v v4, (a0)
+	th.vsseg5e.v v4, 0(a0)
+	th.vsseg5e.v v4, (a0), v0.t
+
+	th.vlseg6b.v v4, (a0)
+	th.vlseg6b.v v4, 0(a0)
+	th.vlseg6b.v v4, (a0), v0.t
+	th.vlseg6h.v v4, (a0)
+	th.vlseg6h.v v4, 0(a0)
+	th.vlseg6h.v v4, (a0), v0.t
+	th.vlseg6w.v v4, (a0)
+	th.vlseg6w.v v4, 0(a0)
+	th.vlseg6w.v v4, (a0), v0.t
+	th.vlseg6bu.v v4, (a0)
+	th.vlseg6bu.v v4, 0(a0)
+	th.vlseg6bu.v v4, (a0), v0.t
+	th.vlseg6hu.v v4, (a0)
+	th.vlseg6hu.v v4, 0(a0)
+	th.vlseg6hu.v v4, (a0), v0.t
+	th.vlseg6wu.v v4, (a0)
+	th.vlseg6wu.v v4, 0(a0)
+	th.vlseg6wu.v v4, (a0), v0.t
+	th.vlseg6e.v v4, (a0)
+	th.vlseg6e.v v4, 0(a0)
+	th.vlseg6e.v v4, (a0), v0.t
+	th.vsseg6b.v v4, (a0)
+	th.vsseg6b.v v4, 0(a0)
+	th.vsseg6b.v v4, (a0), v0.t
+	th.vsseg6h.v v4, (a0)
+	th.vsseg6h.v v4, 0(a0)
+	th.vsseg6h.v v4, (a0), v0.t
+	th.vsseg6w.v v4, (a0)
+	th.vsseg6w.v v4, 0(a0)
+	th.vsseg6w.v v4, (a0), v0.t
+	th.vsseg6e.v v4, (a0)
+	th.vsseg6e.v v4, 0(a0)
+	th.vsseg6e.v v4, (a0), v0.t
+
+	th.vlseg7b.v v4, (a0)
+	th.vlseg7b.v v4, 0(a0)
+	th.vlseg7b.v v4, (a0), v0.t
+	th.vlseg7h.v v4, (a0)
+	th.vlseg7h.v v4, 0(a0)
+	th.vlseg7h.v v4, (a0), v0.t
+	th.vlseg7w.v v4, (a0)
+	th.vlseg7w.v v4, 0(a0)
+	th.vlseg7w.v v4, (a0), v0.t
+	th.vlseg7bu.v v4, (a0)
+	th.vlseg7bu.v v4, 0(a0)
+	th.vlseg7bu.v v4, (a0), v0.t
+	th.vlseg7hu.v v4, (a0)
+	th.vlseg7hu.v v4, 0(a0)
+	th.vlseg7hu.v v4, (a0), v0.t
+	th.vlseg7wu.v v4, (a0)
+	th.vlseg7wu.v v4, 0(a0)
+	th.vlseg7wu.v v4, (a0), v0.t
+	th.vlseg7e.v v4, (a0)
+	th.vlseg7e.v v4, 0(a0)
+	th.vlseg7e.v v4, (a0), v0.t
+	th.vsseg7b.v v4, (a0)
+	th.vsseg7b.v v4, 0(a0)
+	th.vsseg7b.v v4, (a0), v0.t
+	th.vsseg7h.v v4, (a0)
+	th.vsseg7h.v v4, 0(a0)
+	th.vsseg7h.v v4, (a0), v0.t
+	th.vsseg7w.v v4, (a0)
+	th.vsseg7w.v v4, 0(a0)
+	th.vsseg7w.v v4, (a0), v0.t
+	th.vsseg7e.v v4, (a0)
+	th.vsseg7e.v v4, 0(a0)
+	th.vsseg7e.v v4, (a0), v0.t
+
+	th.vlseg8b.v v4, (a0)
+	th.vlseg8b.v v4, 0(a0)
+	th.vlseg8b.v v4, (a0), v0.t
+	th.vlseg8h.v v4, (a0)
+	th.vlseg8h.v v4, 0(a0)
+	th.vlseg8h.v v4, (a0), v0.t
+	th.vlseg8w.v v4, (a0)
+	th.vlseg8w.v v4, 0(a0)
+	th.vlseg8w.v v4, (a0), v0.t
+	th.vlseg8bu.v v4, (a0)
+	th.vlseg8bu.v v4, 0(a0)
+	th.vlseg8bu.v v4, (a0), v0.t
+	th.vlseg8hu.v v4, (a0)
+	th.vlseg8hu.v v4, 0(a0)
+	th.vlseg8hu.v v4, (a0), v0.t
+	th.vlseg8wu.v v4, (a0)
+	th.vlseg8wu.v v4, 0(a0)
+	th.vlseg8wu.v v4, (a0), v0.t
+	th.vlseg8e.v v4, (a0)
+	th.vlseg8e.v v4, 0(a0)
+	th.vlseg8e.v v4, (a0), v0.t
+	th.vsseg8b.v v4, (a0)
+	th.vsseg8b.v v4, 0(a0)
+	th.vsseg8b.v v4, (a0), v0.t
+	th.vsseg8h.v v4, (a0)
+	th.vsseg8h.v v4, 0(a0)
+	th.vsseg8h.v v4, (a0), v0.t
+	th.vsseg8w.v v4, (a0)
+	th.vsseg8w.v v4, 0(a0)
+	th.vsseg8w.v v4, (a0), v0.t
+	th.vsseg8e.v v4, (a0)
+	th.vsseg8e.v v4, 0(a0)
+	th.vsseg8e.v v4, (a0), v0.t
+
+	th.vlsseg2b.v v4, (a0), a1
+	th.vlsseg2b.v v4, 0(a0), a1
+	th.vlsseg2b.v v4, (a0), a1, v0.t
+	th.vlsseg2h.v v4, (a0), a1
+	th.vlsseg2h.v v4, 0(a0), a1
+	th.vlsseg2h.v v4, (a0), a1, v0.t
+	th.vlsseg2w.v v4, (a0), a1
+	th.vlsseg2w.v v4, 0(a0), a1
+	th.vlsseg2w.v v4, (a0), a1, v0.t
+	th.vlsseg2bu.v v4, (a0), a1
+	th.vlsseg2bu.v v4, 0(a0), a1
+	th.vlsseg2bu.v v4, (a0), a1, v0.t
+	th.vlsseg2hu.v v4, (a0), a1
+	th.vlsseg2hu.v v4, 0(a0), a1
+	th.vlsseg2hu.v v4, (a0), a1, v0.t
+	th.vlsseg2wu.v v4, (a0), a1
+	th.vlsseg2wu.v v4, 0(a0), a1
+	th.vlsseg2wu.v v4, (a0), a1, v0.t
+	th.vlsseg2e.v v4, (a0), a1
+	th.vlsseg2e.v v4, 0(a0), a1
+	th.vlsseg2e.v v4, (a0), a1, v0.t
+	th.vssseg2b.v v4, (a0), a1
+	th.vssseg2b.v v4, 0(a0), a1
+	th.vssseg2b.v v4, (a0), a1, v0.t
+	th.vssseg2h.v v4, (a0), a1
+	th.vssseg2h.v v4, 0(a0), a1
+	th.vssseg2h.v v4, (a0), a1, v0.t
+	th.vssseg2w.v v4, (a0), a1
+	th.vssseg2w.v v4, 0(a0), a1
+	th.vssseg2w.v v4, (a0), a1, v0.t
+	th.vssseg2e.v v4, (a0), a1
+	th.vssseg2e.v v4, 0(a0), a1
+	th.vssseg2e.v v4, (a0), a1, v0.t
+
+	th.vlsseg3b.v v4, (a0), a1
+	th.vlsseg3b.v v4, 0(a0), a1
+	th.vlsseg3b.v v4, (a0), a1, v0.t
+	th.vlsseg3h.v v4, (a0), a1
+	th.vlsseg3h.v v4, 0(a0), a1
+	th.vlsseg3h.v v4, (a0), a1, v0.t
+	th.vlsseg3w.v v4, (a0), a1
+	th.vlsseg3w.v v4, 0(a0), a1
+	th.vlsseg3w.v v4, (a0), a1, v0.t
+	th.vlsseg3bu.v v4, (a0), a1
+	th.vlsseg3bu.v v4, 0(a0), a1
+	th.vlsseg3bu.v v4, (a0), a1, v0.t
+	th.vlsseg3hu.v v4, (a0), a1
+	th.vlsseg3hu.v v4, 0(a0), a1
+	th.vlsseg3hu.v v4, (a0), a1, v0.t
+	th.vlsseg3wu.v v4, (a0), a1
+	th.vlsseg3wu.v v4, 0(a0), a1
+	th.vlsseg3wu.v v4, (a0), a1, v0.t
+	th.vlsseg3e.v v4, (a0), a1
+	th.vlsseg3e.v v4, 0(a0), a1
+	th.vlsseg3e.v v4, (a0), a1, v0.t
+	th.vssseg3b.v v4, (a0), a1
+	th.vssseg3b.v v4, 0(a0), a1
+	th.vssseg3b.v v4, (a0), a1, v0.t
+	th.vssseg3h.v v4, (a0), a1
+	th.vssseg3h.v v4, 0(a0), a1
+	th.vssseg3h.v v4, (a0), a1, v0.t
+	th.vssseg3w.v v4, (a0), a1
+	th.vssseg3w.v v4, 0(a0), a1
+	th.vssseg3w.v v4, (a0), a1, v0.t
+	th.vssseg3e.v v4, (a0), a1
+	th.vssseg3e.v v4, 0(a0), a1
+	th.vssseg3e.v v4, (a0), a1, v0.t
+
+	th.vlsseg4b.v v4, (a0), a1
+	th.vlsseg4b.v v4, 0(a0), a1
+	th.vlsseg4b.v v4, (a0), a1, v0.t
+	th.vlsseg4h.v v4, (a0), a1
+	th.vlsseg4h.v v4, 0(a0), a1
+	th.vlsseg4h.v v4, (a0), a1, v0.t
+	th.vlsseg4w.v v4, (a0), a1
+	th.vlsseg4w.v v4, 0(a0), a1
+	th.vlsseg4w.v v4, (a0), a1, v0.t
+	th.vlsseg4bu.v v4, (a0), a1
+	th.vlsseg4bu.v v4, 0(a0), a1
+	th.vlsseg4bu.v v4, (a0), a1, v0.t
+	th.vlsseg4hu.v v4, (a0), a1
+	th.vlsseg4hu.v v4, 0(a0), a1
+	th.vlsseg4hu.v v4, (a0), a1, v0.t
+	th.vlsseg4wu.v v4, (a0), a1
+	th.vlsseg4wu.v v4, 0(a0), a1
+	th.vlsseg4wu.v v4, (a0), a1, v0.t
+	th.vlsseg4e.v v4, (a0), a1
+	th.vlsseg4e.v v4, 0(a0), a1
+	th.vlsseg4e.v v4, (a0), a1, v0.t
+	th.vssseg4b.v v4, (a0), a1
+	th.vssseg4b.v v4, 0(a0), a1
+	th.vssseg4b.v v4, (a0), a1, v0.t
+	th.vssseg4h.v v4, (a0), a1
+	th.vssseg4h.v v4, 0(a0), a1
+	th.vssseg4h.v v4, (a0), a1, v0.t
+	th.vssseg4w.v v4, (a0), a1
+	th.vssseg4w.v v4, 0(a0), a1
+	th.vssseg4w.v v4, (a0), a1, v0.t
+	th.vssseg4e.v v4, (a0), a1
+	th.vssseg4e.v v4, 0(a0), a1
+	th.vssseg4e.v v4, (a0), a1, v0.t
+
+	th.vlsseg5b.v v4, (a0), a1
+	th.vlsseg5b.v v4, 0(a0), a1
+	th.vlsseg5b.v v4, (a0), a1, v0.t
+	th.vlsseg5h.v v4, (a0), a1
+	th.vlsseg5h.v v4, 0(a0), a1
+	th.vlsseg5h.v v4, (a0), a1, v0.t
+	th.vlsseg5w.v v4, (a0), a1
+	th.vlsseg5w.v v4, 0(a0), a1
+	th.vlsseg5w.v v4, (a0), a1, v0.t
+	th.vlsseg5bu.v v4, (a0), a1
+	th.vlsseg5bu.v v4, 0(a0), a1
+	th.vlsseg5bu.v v4, (a0), a1, v0.t
+	th.vlsseg5hu.v v4, (a0), a1
+	th.vlsseg5hu.v v4, 0(a0), a1
+	th.vlsseg5hu.v v4, (a0), a1, v0.t
+	th.vlsseg5wu.v v4, (a0), a1
+	th.vlsseg5wu.v v4, 0(a0), a1
+	th.vlsseg5wu.v v4, (a0), a1, v0.t
+	th.vlsseg5e.v v4, (a0), a1
+	th.vlsseg5e.v v4, 0(a0), a1
+	th.vlsseg5e.v v4, (a0), a1, v0.t
+	th.vssseg5b.v v4, (a0), a1
+	th.vssseg5b.v v4, 0(a0), a1
+	th.vssseg5b.v v4, (a0), a1, v0.t
+	th.vssseg5h.v v4, (a0), a1
+	th.vssseg5h.v v4, 0(a0), a1
+	th.vssseg5h.v v4, (a0), a1, v0.t
+	th.vssseg5w.v v4, (a0), a1
+	th.vssseg5w.v v4, 0(a0), a1
+	th.vssseg5w.v v4, (a0), a1, v0.t
+	th.vssseg5e.v v4, (a0), a1
+	th.vssseg5e.v v4, 0(a0), a1
+	th.vssseg5e.v v4, (a0), a1, v0.t
+
+	th.vlsseg6b.v v4, (a0), a1
+	th.vlsseg6b.v v4, 0(a0), a1
+	th.vlsseg6b.v v4, (a0), a1, v0.t
+	th.vlsseg6h.v v4, (a0), a1
+	th.vlsseg6h.v v4, 0(a0), a1
+	th.vlsseg6h.v v4, (a0), a1, v0.t
+	th.vlsseg6w.v v4, (a0), a1
+	th.vlsseg6w.v v4, 0(a0), a1
+	th.vlsseg6w.v v4, (a0), a1, v0.t
+	th.vlsseg6bu.v v4, (a0), a1
+	th.vlsseg6bu.v v4, 0(a0), a1
+	th.vlsseg6bu.v v4, (a0), a1, v0.t
+	th.vlsseg6hu.v v4, (a0), a1
+	th.vlsseg6hu.v v4, 0(a0), a1
+	th.vlsseg6hu.v v4, (a0), a1, v0.t
+	th.vlsseg6wu.v v4, (a0), a1
+	th.vlsseg6wu.v v4, 0(a0), a1
+	th.vlsseg6wu.v v4, (a0), a1, v0.t
+	th.vlsseg6e.v v4, (a0), a1
+	th.vlsseg6e.v v4, 0(a0), a1
+	th.vlsseg6e.v v4, (a0), a1, v0.t
+	th.vssseg6b.v v4, (a0), a1
+	th.vssseg6b.v v4, 0(a0), a1
+	th.vssseg6b.v v4, (a0), a1, v0.t
+	th.vssseg6h.v v4, (a0), a1
+	th.vssseg6h.v v4, 0(a0), a1
+	th.vssseg6h.v v4, (a0), a1, v0.t
+	th.vssseg6w.v v4, (a0), a1
+	th.vssseg6w.v v4, 0(a0), a1
+	th.vssseg6w.v v4, (a0), a1, v0.t
+	th.vssseg6e.v v4, (a0), a1
+	th.vssseg6e.v v4, 0(a0), a1
+	th.vssseg6e.v v4, (a0), a1, v0.t
+
+	th.vlsseg7b.v v4, (a0), a1
+	th.vlsseg7b.v v4, 0(a0), a1
+	th.vlsseg7b.v v4, (a0), a1, v0.t
+	th.vlsseg7h.v v4, (a0), a1
+	th.vlsseg7h.v v4, 0(a0), a1
+	th.vlsseg7h.v v4, (a0), a1, v0.t
+	th.vlsseg7w.v v4, (a0), a1
+	th.vlsseg7w.v v4, 0(a0), a1
+	th.vlsseg7w.v v4, (a0), a1, v0.t
+	th.vlsseg7bu.v v4, (a0), a1
+	th.vlsseg7bu.v v4, 0(a0), a1
+	th.vlsseg7bu.v v4, (a0), a1, v0.t
+	th.vlsseg7hu.v v4, (a0), a1
+	th.vlsseg7hu.v v4, 0(a0), a1
+	th.vlsseg7hu.v v4, (a0), a1, v0.t
+	th.vlsseg7wu.v v4, (a0), a1
+	th.vlsseg7wu.v v4, 0(a0), a1
+	th.vlsseg7wu.v v4, (a0), a1, v0.t
+	th.vlsseg7e.v v4, (a0), a1
+	th.vlsseg7e.v v4, 0(a0), a1
+	th.vlsseg7e.v v4, (a0), a1, v0.t
+	th.vssseg7b.v v4, (a0), a1
+	th.vssseg7b.v v4, 0(a0), a1
+	th.vssseg7b.v v4, (a0), a1, v0.t
+	th.vssseg7h.v v4, (a0), a1
+	th.vssseg7h.v v4, 0(a0), a1
+	th.vssseg7h.v v4, (a0), a1, v0.t
+	th.vssseg7w.v v4, (a0), a1
+	th.vssseg7w.v v4, 0(a0), a1
+	th.vssseg7w.v v4, (a0), a1, v0.t
+	th.vssseg7e.v v4, (a0), a1
+	th.vssseg7e.v v4, 0(a0), a1
+	th.vssseg7e.v v4, (a0), a1, v0.t
+
+	th.vlsseg8b.v v4, (a0), a1
+	th.vlsseg8b.v v4, 0(a0), a1
+	th.vlsseg8b.v v4, (a0), a1, v0.t
+	th.vlsseg8h.v v4, (a0), a1
+	th.vlsseg8h.v v4, 0(a0), a1
+	th.vlsseg8h.v v4, (a0), a1, v0.t
+	th.vlsseg8w.v v4, (a0), a1
+	th.vlsseg8w.v v4, 0(a0), a1
+	th.vlsseg8w.v v4, (a0), a1, v0.t
+	th.vlsseg8bu.v v4, (a0), a1
+	th.vlsseg8bu.v v4, 0(a0), a1
+	th.vlsseg8bu.v v4, (a0), a1, v0.t
+	th.vlsseg8hu.v v4, (a0), a1
+	th.vlsseg8hu.v v4, 0(a0), a1
+	th.vlsseg8hu.v v4, (a0), a1, v0.t
+	th.vlsseg8wu.v v4, (a0), a1
+	th.vlsseg8wu.v v4, 0(a0), a1
+	th.vlsseg8wu.v v4, (a0), a1, v0.t
+	th.vlsseg8e.v v4, (a0), a1
+	th.vlsseg8e.v v4, 0(a0), a1
+	th.vlsseg8e.v v4, (a0), a1, v0.t
+	th.vssseg8b.v v4, (a0), a1
+	th.vssseg8b.v v4, 0(a0), a1
+	th.vssseg8b.v v4, (a0), a1, v0.t
+	th.vssseg8h.v v4, (a0), a1
+	th.vssseg8h.v v4, 0(a0), a1
+	th.vssseg8h.v v4, (a0), a1, v0.t
+	th.vssseg8w.v v4, (a0), a1
+	th.vssseg8w.v v4, 0(a0), a1
+	th.vssseg8w.v v4, (a0), a1, v0.t
+	th.vssseg8e.v v4, (a0), a1
+	th.vssseg8e.v v4, 0(a0), a1
+	th.vssseg8e.v v4, (a0), a1, v0.t
+
+	th.vlxseg2b.v v4, (a0), v12
+	th.vlxseg2b.v v4, 0(a0), v12
+	th.vlxseg2b.v v4, (a0), v12, v0.t
+	th.vlxseg2h.v v4, (a0), v12
+	th.vlxseg2h.v v4, 0(a0), v12
+	th.vlxseg2h.v v4, (a0), v12, v0.t
+	th.vlxseg2w.v v4, (a0), v12
+	th.vlxseg2w.v v4, 0(a0), v12
+	th.vlxseg2w.v v4, (a0), v12, v0.t
+	th.vlxseg2bu.v v4, (a0), v12
+	th.vlxseg2bu.v v4, 0(a0), v12
+	th.vlxseg2bu.v v4, (a0), v12, v0.t
+	th.vlxseg2hu.v v4, (a0), v12
+	th.vlxseg2hu.v v4, 0(a0), v12
+	th.vlxseg2hu.v v4, (a0), v12, v0.t
+	th.vlxseg2wu.v v4, (a0), v12
+	th.vlxseg2wu.v v4, 0(a0), v12
+	th.vlxseg2wu.v v4, (a0), v12, v0.t
+	th.vlxseg2e.v v4, (a0), v12
+	th.vlxseg2e.v v4, 0(a0), v12
+	th.vlxseg2e.v v4, (a0), v12, v0.t
+	th.vsxseg2b.v v4, (a0), v12
+	th.vsxseg2b.v v4, 0(a0), v12
+	th.vsxseg2b.v v4, (a0), v12, v0.t
+	th.vsxseg2h.v v4, (a0), v12
+	th.vsxseg2h.v v4, 0(a0), v12
+	th.vsxseg2h.v v4, (a0), v12, v0.t
+	th.vsxseg2w.v v4, (a0), v12
+	th.vsxseg2w.v v4, 0(a0), v12
+	th.vsxseg2w.v v4, (a0), v12, v0.t
+	th.vsxseg2e.v v4, (a0), v12
+	th.vsxseg2e.v v4, 0(a0), v12
+	th.vsxseg2e.v v4, (a0), v12, v0.t
+
+	th.vlxseg3b.v v4, (a0), v12
+	th.vlxseg3b.v v4, 0(a0), v12
+	th.vlxseg3b.v v4, (a0), v12, v0.t
+	th.vlxseg3h.v v4, (a0), v12
+	th.vlxseg3h.v v4, 0(a0), v12
+	th.vlxseg3h.v v4, (a0), v12, v0.t
+	th.vlxseg3w.v v4, (a0), v12
+	th.vlxseg3w.v v4, 0(a0), v12
+	th.vlxseg3w.v v4, (a0), v12, v0.t
+	th.vlxseg3bu.v v4, (a0), v12
+	th.vlxseg3bu.v v4, 0(a0), v12
+	th.vlxseg3bu.v v4, (a0), v12, v0.t
+	th.vlxseg3hu.v v4, (a0), v12
+	th.vlxseg3hu.v v4, 0(a0), v12
+	th.vlxseg3hu.v v4, (a0), v12, v0.t
+	th.vlxseg3wu.v v4, (a0), v12
+	th.vlxseg3wu.v v4, 0(a0), v12
+	th.vlxseg3wu.v v4, (a0), v12, v0.t
+	th.vlxseg3e.v v4, (a0), v12
+	th.vlxseg3e.v v4, 0(a0), v12
+	th.vlxseg3e.v v4, (a0), v12, v0.t
+	th.vsxseg3b.v v4, (a0), v12
+	th.vsxseg3b.v v4, 0(a0), v12
+	th.vsxseg3b.v v4, (a0), v12, v0.t
+	th.vsxseg3h.v v4, (a0), v12
+	th.vsxseg3h.v v4, 0(a0), v12
+	th.vsxseg3h.v v4, (a0), v12, v0.t
+	th.vsxseg3w.v v4, (a0), v12
+	th.vsxseg3w.v v4, 0(a0), v12
+	th.vsxseg3w.v v4, (a0), v12, v0.t
+	th.vsxseg3e.v v4, (a0), v12
+	th.vsxseg3e.v v4, 0(a0), v12
+	th.vsxseg3e.v v4, (a0), v12, v0.t
+
+	th.vlxseg4b.v v4, (a0), v12
+	th.vlxseg4b.v v4, 0(a0), v12
+	th.vlxseg4b.v v4, (a0), v12, v0.t
+	th.vlxseg4h.v v4, (a0), v12
+	th.vlxseg4h.v v4, 0(a0), v12
+	th.vlxseg4h.v v4, (a0), v12, v0.t
+	th.vlxseg4w.v v4, (a0), v12
+	th.vlxseg4w.v v4, 0(a0), v12
+	th.vlxseg4w.v v4, (a0), v12, v0.t
+	th.vlxseg4bu.v v4, (a0), v12
+	th.vlxseg4bu.v v4, 0(a0), v12
+	th.vlxseg4bu.v v4, (a0), v12, v0.t
+	th.vlxseg4hu.v v4, (a0), v12
+	th.vlxseg4hu.v v4, 0(a0), v12
+	th.vlxseg4hu.v v4, (a0), v12, v0.t
+	th.vlxseg4wu.v v4, (a0), v12
+	th.vlxseg4wu.v v4, 0(a0), v12
+	th.vlxseg4wu.v v4, (a0), v12, v0.t
+	th.vlxseg4e.v v4, (a0), v12
+	th.vlxseg4e.v v4, 0(a0), v12
+	th.vlxseg4e.v v4, (a0), v12, v0.t
+	th.vsxseg4b.v v4, (a0), v12
+	th.vsxseg4b.v v4, 0(a0), v12
+	th.vsxseg4b.v v4, (a0), v12, v0.t
+	th.vsxseg4h.v v4, (a0), v12
+	th.vsxseg4h.v v4, 0(a0), v12
+	th.vsxseg4h.v v4, (a0), v12, v0.t
+	th.vsxseg4w.v v4, (a0), v12
+	th.vsxseg4w.v v4, 0(a0), v12
+	th.vsxseg4w.v v4, (a0), v12, v0.t
+	th.vsxseg4e.v v4, (a0), v12
+	th.vsxseg4e.v v4, 0(a0), v12
+	th.vsxseg4e.v v4, (a0), v12, v0.t
+
+	th.vlxseg5b.v v4, (a0), v12
+	th.vlxseg5b.v v4, 0(a0), v12
+	th.vlxseg5b.v v4, (a0), v12, v0.t
+	th.vlxseg5h.v v4, (a0), v12
+	th.vlxseg5h.v v4, 0(a0), v12
+	th.vlxseg5h.v v4, (a0), v12, v0.t
+	th.vlxseg5w.v v4, (a0), v12
+	th.vlxseg5w.v v4, 0(a0), v12
+	th.vlxseg5w.v v4, (a0), v12, v0.t
+	th.vlxseg5bu.v v4, (a0), v12
+	th.vlxseg5bu.v v4, 0(a0), v12
+	th.vlxseg5bu.v v4, (a0), v12, v0.t
+	th.vlxseg5hu.v v4, (a0), v12
+	th.vlxseg5hu.v v4, 0(a0), v12
+	th.vlxseg5hu.v v4, (a0), v12, v0.t
+	th.vlxseg5wu.v v4, (a0), v12
+	th.vlxseg5wu.v v4, 0(a0), v12
+	th.vlxseg5wu.v v4, (a0), v12, v0.t
+	th.vlxseg5e.v v4, (a0), v12
+	th.vlxseg5e.v v4, 0(a0), v12
+	th.vlxseg5e.v v4, (a0), v12, v0.t
+	th.vsxseg5b.v v4, (a0), v12
+	th.vsxseg5b.v v4, 0(a0), v12
+	th.vsxseg5b.v v4, (a0), v12, v0.t
+	th.vsxseg5h.v v4, (a0), v12
+	th.vsxseg5h.v v4, 0(a0), v12
+	th.vsxseg5h.v v4, (a0), v12, v0.t
+	th.vsxseg5w.v v4, (a0), v12
+	th.vsxseg5w.v v4, 0(a0), v12
+	th.vsxseg5w.v v4, (a0), v12, v0.t
+	th.vsxseg5e.v v4, (a0), v12
+	th.vsxseg5e.v v4, 0(a0), v12
+	th.vsxseg5e.v v4, (a0), v12, v0.t
+
+	th.vlxseg6b.v v4, (a0), v12
+	th.vlxseg6b.v v4, 0(a0), v12
+	th.vlxseg6b.v v4, (a0), v12, v0.t
+	th.vlxseg6h.v v4, (a0), v12
+	th.vlxseg6h.v v4, 0(a0), v12
+	th.vlxseg6h.v v4, (a0), v12, v0.t
+	th.vlxseg6w.v v4, (a0), v12
+	th.vlxseg6w.v v4, 0(a0), v12
+	th.vlxseg6w.v v4, (a0), v12, v0.t
+	th.vlxseg6bu.v v4, (a0), v12
+	th.vlxseg6bu.v v4, 0(a0), v12
+	th.vlxseg6bu.v v4, (a0), v12, v0.t
+	th.vlxseg6hu.v v4, (a0), v12
+	th.vlxseg6hu.v v4, 0(a0), v12
+	th.vlxseg6hu.v v4, (a0), v12, v0.t
+	th.vlxseg6wu.v v4, (a0), v12
+	th.vlxseg6wu.v v4, 0(a0), v12
+	th.vlxseg6wu.v v4, (a0), v12, v0.t
+	th.vlxseg6e.v v4, (a0), v12
+	th.vlxseg6e.v v4, 0(a0), v12
+	th.vlxseg6e.v v4, (a0), v12, v0.t
+	th.vsxseg6b.v v4, (a0), v12
+	th.vsxseg6b.v v4, 0(a0), v12
+	th.vsxseg6b.v v4, (a0), v12, v0.t
+	th.vsxseg6h.v v4, (a0), v12
+	th.vsxseg6h.v v4, 0(a0), v12
+	th.vsxseg6h.v v4, (a0), v12, v0.t
+	th.vsxseg6w.v v4, (a0), v12
+	th.vsxseg6w.v v4, 0(a0), v12
+	th.vsxseg6w.v v4, (a0), v12, v0.t
+	th.vsxseg6e.v v4, (a0), v12
+	th.vsxseg6e.v v4, 0(a0), v12
+	th.vsxseg6e.v v4, (a0), v12, v0.t
+
+	th.vlxseg7b.v v4, (a0), v12
+	th.vlxseg7b.v v4, 0(a0), v12
+	th.vlxseg7b.v v4, (a0), v12, v0.t
+	th.vlxseg7h.v v4, (a0), v12
+	th.vlxseg7h.v v4, 0(a0), v12
+	th.vlxseg7h.v v4, (a0), v12, v0.t
+	th.vlxseg7w.v v4, (a0), v12
+	th.vlxseg7w.v v4, 0(a0), v12
+	th.vlxseg7w.v v4, (a0), v12, v0.t
+	th.vlxseg7bu.v v4, (a0), v12
+	th.vlxseg7bu.v v4, 0(a0), v12
+	th.vlxseg7bu.v v4, (a0), v12, v0.t
+	th.vlxseg7hu.v v4, (a0), v12
+	th.vlxseg7hu.v v4, 0(a0), v12
+	th.vlxseg7hu.v v4, (a0), v12, v0.t
+	th.vlxseg7wu.v v4, (a0), v12
+	th.vlxseg7wu.v v4, 0(a0), v12
+	th.vlxseg7wu.v v4, (a0), v12, v0.t
+	th.vlxseg7e.v v4, (a0), v12
+	th.vlxseg7e.v v4, 0(a0), v12
+	th.vlxseg7e.v v4, (a0), v12, v0.t
+	th.vsxseg7b.v v4, (a0), v12
+	th.vsxseg7b.v v4, 0(a0), v12
+	th.vsxseg7b.v v4, (a0), v12, v0.t
+	th.vsxseg7h.v v4, (a0), v12
+	th.vsxseg7h.v v4, 0(a0), v12
+	th.vsxseg7h.v v4, (a0), v12, v0.t
+	th.vsxseg7w.v v4, (a0), v12
+	th.vsxseg7w.v v4, 0(a0), v12
+	th.vsxseg7w.v v4, (a0), v12, v0.t
+	th.vsxseg7e.v v4, (a0), v12
+	th.vsxseg7e.v v4, 0(a0), v12
+	th.vsxseg7e.v v4, (a0), v12, v0.t
+
+	th.vlxseg8b.v v4, (a0), v12
+	th.vlxseg8b.v v4, 0(a0), v12
+	th.vlxseg8b.v v4, (a0), v12, v0.t
+	th.vlxseg8h.v v4, (a0), v12
+	th.vlxseg8h.v v4, 0(a0), v12
+	th.vlxseg8h.v v4, (a0), v12, v0.t
+	th.vlxseg8w.v v4, (a0), v12
+	th.vlxseg8w.v v4, 0(a0), v12
+	th.vlxseg8w.v v4, (a0), v12, v0.t
+	th.vlxseg8bu.v v4, (a0), v12
+	th.vlxseg8bu.v v4, 0(a0), v12
+	th.vlxseg8bu.v v4, (a0), v12, v0.t
+	th.vlxseg8hu.v v4, (a0), v12
+	th.vlxseg8hu.v v4, 0(a0), v12
+	th.vlxseg8hu.v v4, (a0), v12, v0.t
+	th.vlxseg8wu.v v4, (a0), v12
+	th.vlxseg8wu.v v4, 0(a0), v12
+	th.vlxseg8wu.v v4, (a0), v12, v0.t
+	th.vlxseg8e.v v4, (a0), v12
+	th.vlxseg8e.v v4, 0(a0), v12
+	th.vlxseg8e.v v4, (a0), v12, v0.t
+	th.vsxseg8b.v v4, (a0), v12
+	th.vsxseg8b.v v4, 0(a0), v12
+	th.vsxseg8b.v v4, (a0), v12, v0.t
+	th.vsxseg8h.v v4, (a0), v12
+	th.vsxseg8h.v v4, 0(a0), v12
+	th.vsxseg8h.v v4, (a0), v12, v0.t
+	th.vsxseg8w.v v4, (a0), v12
+	th.vsxseg8w.v v4, 0(a0), v12
+	th.vsxseg8w.v v4, (a0), v12, v0.t
+	th.vsxseg8e.v v4, (a0), v12
+	th.vsxseg8e.v v4, 0(a0), v12
+	th.vsxseg8e.v v4, (a0), v12, v0.t
+
+	th.vlseg2bff.v v4, (a0)
+	th.vlseg2bff.v v4, 0(a0)
+	th.vlseg2bff.v v4, (a0), v0.t
+	th.vlseg2hff.v v4, (a0)
+	th.vlseg2hff.v v4, 0(a0)
+	th.vlseg2hff.v v4, (a0), v0.t
+	th.vlseg2wff.v v4, (a0)
+	th.vlseg2wff.v v4, 0(a0)
+	th.vlseg2wff.v v4, (a0), v0.t
+	th.vlseg2buff.v v4, (a0)
+	th.vlseg2buff.v v4, 0(a0)
+	th.vlseg2buff.v v4, (a0), v0.t
+	th.vlseg2huff.v v4, (a0)
+	th.vlseg2huff.v v4, 0(a0)
+	th.vlseg2huff.v v4, (a0), v0.t
+	th.vlseg2wuff.v v4, (a0)
+	th.vlseg2wuff.v v4, 0(a0)
+	th.vlseg2wuff.v v4, (a0), v0.t
+	th.vlseg2eff.v v4, (a0)
+	th.vlseg2eff.v v4, 0(a0)
+	th.vlseg2eff.v v4, (a0), v0.t
+
+	th.vlseg3bff.v v4, (a0)
+	th.vlseg3bff.v v4, 0(a0)
+	th.vlseg3bff.v v4, (a0), v0.t
+	th.vlseg3hff.v v4, (a0)
+	th.vlseg3hff.v v4, 0(a0)
+	th.vlseg3hff.v v4, (a0), v0.t
+	th.vlseg3wff.v v4, (a0)
+	th.vlseg3wff.v v4, 0(a0)
+	th.vlseg3wff.v v4, (a0), v0.t
+	th.vlseg3buff.v v4, (a0)
+	th.vlseg3buff.v v4, 0(a0)
+	th.vlseg3buff.v v4, (a0), v0.t
+	th.vlseg3huff.v v4, (a0)
+	th.vlseg3huff.v v4, 0(a0)
+	th.vlseg3huff.v v4, (a0), v0.t
+	th.vlseg3wuff.v v4, (a0)
+	th.vlseg3wuff.v v4, 0(a0)
+	th.vlseg3wuff.v v4, (a0), v0.t
+	th.vlseg3eff.v v4, (a0)
+	th.vlseg3eff.v v4, 0(a0)
+	th.vlseg3eff.v v4, (a0), v0.t
+
+	th.vlseg4bff.v v4, (a0)
+	th.vlseg4bff.v v4, 0(a0)
+	th.vlseg4bff.v v4, (a0), v0.t
+	th.vlseg4hff.v v4, (a0)
+	th.vlseg4hff.v v4, 0(a0)
+	th.vlseg4hff.v v4, (a0), v0.t
+	th.vlseg4wff.v v4, (a0)
+	th.vlseg4wff.v v4, 0(a0)
+	th.vlseg4wff.v v4, (a0), v0.t
+	th.vlseg4buff.v v4, (a0)
+	th.vlseg4buff.v v4, 0(a0)
+	th.vlseg4buff.v v4, (a0), v0.t
+	th.vlseg4huff.v v4, (a0)
+	th.vlseg4huff.v v4, 0(a0)
+	th.vlseg4huff.v v4, (a0), v0.t
+	th.vlseg4wuff.v v4, (a0)
+	th.vlseg4wuff.v v4, 0(a0)
+	th.vlseg4wuff.v v4, (a0), v0.t
+	th.vlseg4eff.v v4, (a0)
+	th.vlseg4eff.v v4, 0(a0)
+	th.vlseg4eff.v v4, (a0), v0.t
+
+	th.vlseg5bff.v v4, (a0)
+	th.vlseg5bff.v v4, 0(a0)
+	th.vlseg5bff.v v4, (a0), v0.t
+	th.vlseg5hff.v v4, (a0)
+	th.vlseg5hff.v v4, 0(a0)
+	th.vlseg5hff.v v4, (a0), v0.t
+	th.vlseg5wff.v v4, (a0)
+	th.vlseg5wff.v v4, 0(a0)
+	th.vlseg5wff.v v4, (a0), v0.t
+	th.vlseg5buff.v v4, (a0)
+	th.vlseg5buff.v v4, 0(a0)
+	th.vlseg5buff.v v4, (a0), v0.t
+	th.vlseg5huff.v v4, (a0)
+	th.vlseg5huff.v v4, 0(a0)
+	th.vlseg5huff.v v4, (a0), v0.t
+	th.vlseg5wuff.v v4, (a0)
+	th.vlseg5wuff.v v4, 0(a0)
+	th.vlseg5wuff.v v4, (a0), v0.t
+	th.vlseg5eff.v v4, (a0)
+	th.vlseg5eff.v v4, 0(a0)
+	th.vlseg5eff.v v4, (a0), v0.t
+
+	th.vlseg6bff.v v4, (a0)
+	th.vlseg6bff.v v4, 0(a0)
+	th.vlseg6bff.v v4, (a0), v0.t
+	th.vlseg6hff.v v4, (a0)
+	th.vlseg6hff.v v4, 0(a0)
+	th.vlseg6hff.v v4, (a0), v0.t
+	th.vlseg6wff.v v4, (a0)
+	th.vlseg6wff.v v4, 0(a0)
+	th.vlseg6wff.v v4, (a0), v0.t
+	th.vlseg6buff.v v4, (a0)
+	th.vlseg6buff.v v4, 0(a0)
+	th.vlseg6buff.v v4, (a0), v0.t
+	th.vlseg6huff.v v4, (a0)
+	th.vlseg6huff.v v4, 0(a0)
+	th.vlseg6huff.v v4, (a0), v0.t
+	th.vlseg6wuff.v v4, (a0)
+	th.vlseg6wuff.v v4, 0(a0)
+	th.vlseg6wuff.v v4, (a0), v0.t
+	th.vlseg6eff.v v4, (a0)
+	th.vlseg6eff.v v4, 0(a0)
+	th.vlseg6eff.v v4, (a0), v0.t
+
+	th.vlseg7bff.v v4, (a0)
+	th.vlseg7bff.v v4, 0(a0)
+	th.vlseg7bff.v v4, (a0), v0.t
+	th.vlseg7hff.v v4, (a0)
+	th.vlseg7hff.v v4, 0(a0)
+	th.vlseg7hff.v v4, (a0), v0.t
+	th.vlseg7wff.v v4, (a0)
+	th.vlseg7wff.v v4, 0(a0)
+	th.vlseg7wff.v v4, (a0), v0.t
+	th.vlseg7buff.v v4, (a0)
+	th.vlseg7buff.v v4, 0(a0)
+	th.vlseg7buff.v v4, (a0), v0.t
+	th.vlseg7huff.v v4, (a0)
+	th.vlseg7huff.v v4, 0(a0)
+	th.vlseg7huff.v v4, (a0), v0.t
+	th.vlseg7wuff.v v4, (a0)
+	th.vlseg7wuff.v v4, 0(a0)
+	th.vlseg7wuff.v v4, (a0), v0.t
+	th.vlseg7eff.v v4, (a0)
+	th.vlseg7eff.v v4, 0(a0)
+	th.vlseg7eff.v v4, (a0), v0.t
+
+	th.vlseg8bff.v v4, (a0)
+	th.vlseg8bff.v v4, 0(a0)
+	th.vlseg8bff.v v4, (a0), v0.t
+	th.vlseg8hff.v v4, (a0)
+	th.vlseg8hff.v v4, 0(a0)
+	th.vlseg8hff.v v4, (a0), v0.t
+	th.vlseg8wff.v v4, (a0)
+	th.vlseg8wff.v v4, 0(a0)
+	th.vlseg8wff.v v4, (a0), v0.t
+	th.vlseg8buff.v v4, (a0)
+	th.vlseg8buff.v v4, 0(a0)
+	th.vlseg8buff.v v4, (a0), v0.t
+	th.vlseg8huff.v v4, (a0)
+	th.vlseg8huff.v v4, 0(a0)
+	th.vlseg8huff.v v4, (a0), v0.t
+	th.vlseg8wuff.v v4, (a0)
+	th.vlseg8wuff.v v4, 0(a0)
+	th.vlseg8wuff.v v4, (a0), v0.t
+	th.vlseg8eff.v v4, (a0)
+	th.vlseg8eff.v v4, 0(a0)
+	th.vlseg8eff.v v4, (a0), v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 792958b8925..6556de2b17d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2681,6 +2681,175 @@
 #define MASK_TH_VLHFFV   0xfdf0707f
 #define MATCH_TH_VLWFFV  0x11006007
 #define MASK_TH_VLWFFV   0xfdf0707f
+#define MATCH_TH_VLSEG2BV 0x30000007
+#define MASK_TH_VLSEG2BV 0xfdf0707f
+#define MATCH_TH_VLSEG2HV 0x30005007
+#define MASK_TH_VLSEG2HV 0xfdf0707f
+#define MATCH_TH_VLSEG2WV 0x30006007
+#define MASK_TH_VLSEG2WV 0xfdf0707f
+#define MATCH_TH_VLSEG3BV 0x50000007
+#define MASK_TH_VLSEG3BV 0xfdf0707f
+#define MATCH_TH_VLSEG3HV 0x50005007
+#define MASK_TH_VLSEG3HV 0xfdf0707f
+#define MATCH_TH_VLSEG3WV 0x50006007
+#define MASK_TH_VLSEG3WV 0xfdf0707f
+#define MATCH_TH_VLSEG4BV 0x70000007
+#define MASK_TH_VLSEG4BV 0xfdf0707f
+#define MATCH_TH_VLSEG4HV 0x70005007
+#define MASK_TH_VLSEG4HV 0xfdf0707f
+#define MATCH_TH_VLSEG4WV 0x70006007
+#define MASK_TH_VLSEG4WV 0xfdf0707f
+#define MATCH_TH_VLSEG5BV 0x90000007
+#define MASK_TH_VLSEG5BV 0xfdf0707f
+#define MATCH_TH_VLSEG5HV 0x90005007
+#define MASK_TH_VLSEG5HV 0xfdf0707f
+#define MATCH_TH_VLSEG5WV 0x90006007
+#define MASK_TH_VLSEG5WV 0xfdf0707f
+#define MATCH_TH_VLSEG6BV 0xb0000007
+#define MASK_TH_VLSEG6BV 0xfdf0707f
+#define MATCH_TH_VLSEG6HV 0xb0005007
+#define MASK_TH_VLSEG6HV 0xfdf0707f
+#define MATCH_TH_VLSEG6WV 0xb0006007
+#define MASK_TH_VLSEG6WV 0xfdf0707f
+#define MATCH_TH_VLSEG7BV 0xd0000007
+#define MASK_TH_VLSEG7BV 0xfdf0707f
+#define MATCH_TH_VLSEG7HV 0xd0005007
+#define MASK_TH_VLSEG7HV 0xfdf0707f
+#define MATCH_TH_VLSEG7WV 0xd0006007
+#define MASK_TH_VLSEG7WV 0xfdf0707f
+#define MATCH_TH_VLSEG8BV 0xf0000007
+#define MASK_TH_VLSEG8BV 0xfdf0707f
+#define MATCH_TH_VLSEG8HV 0xf0005007
+#define MASK_TH_VLSEG8HV 0xfdf0707f
+#define MATCH_TH_VLSEG8WV 0xf0006007
+#define MASK_TH_VLSEG8WV 0xfdf0707f
+#define MATCH_TH_VLSSEG2BV 0x38000007
+#define MASK_TH_VLSSEG2BV 0xfc00707f
+#define MATCH_TH_VLSSEG2HV 0x38005007
+#define MASK_TH_VLSSEG2HV 0xfc00707f
+#define MATCH_TH_VLSSEG2WV 0x38006007
+#define MASK_TH_VLSSEG2WV 0xfc00707f
+#define MATCH_TH_VLSSEG3BV 0x58000007
+#define MASK_TH_VLSSEG3BV 0xfc00707f
+#define MATCH_TH_VLSSEG3HV 0x58005007
+#define MASK_TH_VLSSEG3HV 0xfc00707f
+#define MATCH_TH_VLSSEG3WV 0x58006007
+#define MASK_TH_VLSSEG3WV 0xfc00707f
+#define MATCH_TH_VLSSEG4BV 0x78000007
+#define MASK_TH_VLSSEG4BV 0xfc00707f
+#define MATCH_TH_VLSSEG4HV 0x78005007
+#define MASK_TH_VLSSEG4HV 0xfc00707f
+#define MATCH_TH_VLSSEG4WV 0x78006007
+#define MASK_TH_VLSSEG4WV 0xfc00707f
+#define MATCH_TH_VLSSEG5BV 0x98000007
+#define MASK_TH_VLSSEG5BV 0xfc00707f
+#define MATCH_TH_VLSSEG5HV 0x98005007
+#define MASK_TH_VLSSEG5HV 0xfc00707f
+#define MATCH_TH_VLSSEG5WV 0x98006007
+#define MASK_TH_VLSSEG5WV 0xfc00707f
+#define MATCH_TH_VLSSEG6BV 0xb8000007
+#define MASK_TH_VLSSEG6BV 0xfc00707f
+#define MATCH_TH_VLSSEG6HV 0xb8005007
+#define MASK_TH_VLSSEG6HV 0xfc00707f
+#define MATCH_TH_VLSSEG6WV 0xb8006007
+#define MASK_TH_VLSSEG6WV 0xfc00707f
+#define MATCH_TH_VLSSEG7BV 0xd8000007
+#define MASK_TH_VLSSEG7BV 0xfc00707f
+#define MATCH_TH_VLSSEG7HV 0xd8005007
+#define MASK_TH_VLSSEG7HV 0xfc00707f
+#define MATCH_TH_VLSSEG7WV 0xd8006007
+#define MASK_TH_VLSSEG7WV 0xfc00707f
+#define MATCH_TH_VLSSEG8BV 0xf8000007
+#define MASK_TH_VLSSEG8BV 0xfc00707f
+#define MATCH_TH_VLSSEG8HV 0xf8005007
+#define MASK_TH_VLSSEG8HV 0xfc00707f
+#define MATCH_TH_VLSSEG8WV 0xf8006007
+#define MASK_TH_VLSSEG8WV 0xfc00707f
+#define MATCH_TH_VLXSEG2BV 0x3c000007
+#define MASK_TH_VLXSEG2BV 0xfc00707f
+#define MATCH_TH_VLXSEG2HV 0x3c005007
+#define MASK_TH_VLXSEG2HV 0xfc00707f
+#define MATCH_TH_VLXSEG2WV 0x3c006007
+#define MASK_TH_VLXSEG2WV 0xfc00707f
+#define MATCH_TH_VLXSEG3BV 0x5c000007
+#define MASK_TH_VLXSEG3BV 0xfc00707f
+#define MATCH_TH_VLXSEG3HV 0x5c005007
+#define MASK_TH_VLXSEG3HV 0xfc00707f
+#define MATCH_TH_VLXSEG3WV 0x5c006007
+#define MASK_TH_VLXSEG3WV 0xfc00707f
+#define MATCH_TH_VLXSEG4BV 0x7c000007
+#define MASK_TH_VLXSEG4BV 0xfc00707f
+#define MATCH_TH_VLXSEG4HV 0x7c005007
+#define MASK_TH_VLXSEG4HV 0xfc00707f
+#define MATCH_TH_VLXSEG4WV 0x7c006007
+#define MASK_TH_VLXSEG4WV 0xfc00707f
+#define MATCH_TH_VLXSEG5BV 0x9c000007
+#define MASK_TH_VLXSEG5BV 0xfc00707f
+#define MATCH_TH_VLXSEG5HV 0x9c005007
+#define MASK_TH_VLXSEG5HV 0xfc00707f
+#define MATCH_TH_VLXSEG5WV 0x9c006007
+#define MASK_TH_VLXSEG5WV 0xfc00707f
+#define MATCH_TH_VLXSEG6BV 0xbc000007
+#define MASK_TH_VLXSEG6BV 0xfc00707f
+#define MATCH_TH_VLXSEG6HV 0xbc005007
+#define MASK_TH_VLXSEG6HV 0xfc00707f
+#define MATCH_TH_VLXSEG6WV 0xbc006007
+#define MASK_TH_VLXSEG6WV 0xfc00707f
+#define MATCH_TH_VLXSEG7BV 0xdc000007
+#define MASK_TH_VLXSEG7BV 0xfc00707f
+#define MATCH_TH_VLXSEG7HV 0xdc005007
+#define MASK_TH_VLXSEG7HV 0xfc00707f
+#define MATCH_TH_VLXSEG7WV 0xdc006007
+#define MASK_TH_VLXSEG7WV 0xfc00707f
+#define MATCH_TH_VLXSEG8BV 0xfc000007
+#define MASK_TH_VLXSEG8BV 0xfc00707f
+#define MATCH_TH_VLXSEG8HV 0xfc005007
+#define MASK_TH_VLXSEG8HV 0xfc00707f
+#define MATCH_TH_VLXSEG8WV 0xfc006007
+#define MASK_TH_VLXSEG8WV 0xfc00707f
+#define MATCH_TH_VLSEG2BFFV 0x31000007
+#define MASK_TH_VLSEG2BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2HFFV 0x31005007
+#define MASK_TH_VLSEG2HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2WFFV 0x31006007
+#define MASK_TH_VLSEG2WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3BFFV 0x51000007
+#define MASK_TH_VLSEG3BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3HFFV 0x51005007
+#define MASK_TH_VLSEG3HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3WFFV 0x51006007
+#define MASK_TH_VLSEG3WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4BFFV 0x71000007
+#define MASK_TH_VLSEG4BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4HFFV 0x71005007
+#define MASK_TH_VLSEG4HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4WFFV 0x71006007
+#define MASK_TH_VLSEG4WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5BFFV 0x91000007
+#define MASK_TH_VLSEG5BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5HFFV 0x91005007
+#define MASK_TH_VLSEG5HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5WFFV 0x91006007
+#define MASK_TH_VLSEG5WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6BFFV 0xb1000007
+#define MASK_TH_VLSEG6BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6HFFV 0xb1005007
+#define MASK_TH_VLSEG6HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6WFFV 0xb1006007
+#define MASK_TH_VLSEG6WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7BFFV 0xd1000007
+#define MASK_TH_VLSEG7BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7HFFV 0xd1005007
+#define MASK_TH_VLSEG7HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7WFFV 0xd1006007
+#define MASK_TH_VLSEG7WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8BFFV 0xf1000007
+#define MASK_TH_VLSEG8BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8HFFV 0xf1005007
+#define MASK_TH_VLSEG8HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8WFFV 0xf1006007
+#define MASK_TH_VLSEG8WFFV 0xfdf0707f
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 54c1e8a62d9..71e4453cd43 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2281,6 +2281,286 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vlhuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
 {"th.vlwuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
 {"th.vleff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
+{"th.vlseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF },
+{"th.vlseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF },
+{"th.vlseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF },
+{"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF },
+{"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_opcode, INSN_DREF },
+{"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_opcode, INSN_DREF },
+{"th.vlseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF },
+{"th.vsseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vsseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vsseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vsseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vlseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF },
+{"th.vlseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF },
+{"th.vlseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF },
+{"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_opcode, INSN_DREF },
+{"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_opcode, INSN_DREF },
+{"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF },
+{"th.vlseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF },
+{"th.vsseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vsseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vsseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vsseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vlseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF },
+{"th.vlseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF },
+{"th.vlseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF },
+{"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_opcode, INSN_DREF },
+{"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_opcode, INSN_DREF },
+{"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_opcode, INSN_DREF },
+{"th.vlseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF },
+{"th.vsseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vsseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vsseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vsseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vlseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF },
+{"th.vlseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF },
+{"th.vlseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF },
+{"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_opcode, INSN_DREF },
+{"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_opcode, INSN_DREF },
+{"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_opcode, INSN_DREF },
+{"th.vlseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF },
+{"th.vsseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vsseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vsseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vsseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vlseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF },
+{"th.vlseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF },
+{"th.vlseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF },
+{"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_opcode, INSN_DREF },
+{"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_opcode, INSN_DREF },
+{"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_opcode, INSN_DREF },
+{"th.vlseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF },
+{"th.vsseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vsseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vsseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vsseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vlseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF },
+{"th.vlseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF },
+{"th.vlseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF },
+{"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_opcode, INSN_DREF },
+{"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_opcode, INSN_DREF },
+{"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_opcode, INSN_DREF },
+{"th.vlseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF },
+{"th.vsseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
+{"th.vsseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vsseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vsseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vlseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF },
+{"th.vlseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF },
+{"th.vlseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF },
+{"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_opcode, INSN_DREF },
+{"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_opcode, INSN_DREF },
+{"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF },
+{"th.vlseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF },
+{"th.vsseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vsseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vsseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vsseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vlsseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2BV, MASK_TH_VLSSEG2BV, match_opcode, INSN_DREF },
+{"th.vlsseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2HV, MASK_TH_VLSSEG2HV, match_opcode, INSN_DREF },
+{"th.vlsseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2WV, MASK_TH_VLSSEG2WV, match_opcode, INSN_DREF },
+{"th.vlsseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vlsseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vlsseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vlsseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vssseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vssseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vssseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vssseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vlsseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3BV, MASK_TH_VLSSEG3BV, match_opcode, INSN_DREF },
+{"th.vlsseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3HV, MASK_TH_VLSSEG3HV, match_opcode, INSN_DREF },
+{"th.vlsseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3WV, MASK_TH_VLSSEG3WV, match_opcode, INSN_DREF },
+{"th.vlsseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vlsseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vlsseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vlsseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vssseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vssseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vssseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vssseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vlsseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4BV, MASK_TH_VLSSEG4BV, match_opcode, INSN_DREF },
+{"th.vlsseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4HV, MASK_TH_VLSSEG4HV, match_opcode, INSN_DREF },
+{"th.vlsseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4WV, MASK_TH_VLSSEG4WV, match_opcode, INSN_DREF },
+{"th.vlsseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vlsseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vlsseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vlsseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vssseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vssseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vssseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vssseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vlsseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5BV, MASK_TH_VLSSEG5BV, match_opcode, INSN_DREF },
+{"th.vlsseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5HV, MASK_TH_VLSSEG5HV, match_opcode, INSN_DREF },
+{"th.vlsseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5WV, MASK_TH_VLSSEG5WV, match_opcode, INSN_DREF },
+{"th.vlsseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vlsseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vlsseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vlsseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vssseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vssseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vssseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vssseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vlsseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6BV, MASK_TH_VLSSEG6BV, match_opcode, INSN_DREF },
+{"th.vlsseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6HV, MASK_TH_VLSSEG6HV, match_opcode, INSN_DREF },
+{"th.vlsseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6WV, MASK_TH_VLSSEG6WV, match_opcode, INSN_DREF },
+{"th.vlsseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vlsseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vlsseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vlsseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vssseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vssseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vssseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vssseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vlsseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG7BV, MASK_TH_VLSSEG7BV, match_opcode, INSN_DREF },
+{"th.vlsseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG7HV, MASK_TH_VLSSEG7HV, match_opcode, INSN_DREF },
+{"th.vlsseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG7WV, MASK_TH_VLSSEG7WV, match_opcode, INSN_DREF },
+{"th.vlsseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_opcode, INSN_DREF },
+{"th.vlsseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vlsseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vlsseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vssseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
+{"th.vssseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vssseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vssseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vlsseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8BV, MASK_TH_VLSSEG8BV, match_opcode, INSN_DREF },
+{"th.vlsseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8HV, MASK_TH_VLSSEG8HV, match_opcode, INSN_DREF },
+{"th.vlsseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8WV, MASK_TH_VLSSEG8WV, match_opcode, INSN_DREF },
+{"th.vlsseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vlsseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vlsseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vlsseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vssseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vssseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vssseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vssseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vlxseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2BV, MASK_TH_VLXSEG2BV, match_opcode, INSN_DREF },
+{"th.vlxseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2HV, MASK_TH_VLXSEG2HV, match_opcode, INSN_DREF },
+{"th.vlxseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2WV, MASK_TH_VLXSEG2WV, match_opcode, INSN_DREF },
+{"th.vlxseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3BV, MASK_TH_VLXSEG3BV, match_opcode, INSN_DREF },
+{"th.vlxseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3HV, MASK_TH_VLXSEG3HV, match_opcode, INSN_DREF },
+{"th.vlxseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3WV, MASK_TH_VLXSEG3WV, match_opcode, INSN_DREF },
+{"th.vlxseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4BV, MASK_TH_VLXSEG4BV, match_opcode, INSN_DREF },
+{"th.vlxseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4HV, MASK_TH_VLXSEG4HV, match_opcode, INSN_DREF },
+{"th.vlxseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4WV, MASK_TH_VLXSEG4WV, match_opcode, INSN_DREF },
+{"th.vlxseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5BV, MASK_TH_VLXSEG5BV, match_opcode, INSN_DREF },
+{"th.vlxseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5HV, MASK_TH_VLXSEG5HV, match_opcode, INSN_DREF },
+{"th.vlxseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5WV, MASK_TH_VLXSEG5WV, match_opcode, INSN_DREF },
+{"th.vlxseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6BV, MASK_TH_VLXSEG6BV, match_opcode, INSN_DREF },
+{"th.vlxseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6HV, MASK_TH_VLXSEG6HV, match_opcode, INSN_DREF },
+{"th.vlxseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6WV, MASK_TH_VLXSEG6WV, match_opcode, INSN_DREF },
+{"th.vlxseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7BV, MASK_TH_VLXSEG7BV, match_opcode, INSN_DREF },
+{"th.vlxseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7HV, MASK_TH_VLXSEG7HV, match_opcode, INSN_DREF },
+{"th.vlxseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7WV, MASK_TH_VLXSEG7WV, match_opcode, INSN_DREF },
+{"th.vlxseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8BV, MASK_TH_VLXSEG8BV, match_opcode, INSN_DREF },
+{"th.vlxseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8HV, MASK_TH_VLXSEG8HV, match_opcode, INSN_DREF },
+{"th.vlxseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8WV, MASK_TH_VLXSEG8WV, match_opcode, INSN_DREF },
+{"th.vlxseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF },
+{"th.vlseg2bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2BFFV, MASK_TH_VLSEG2BFFV, match_opcode, INSN_DREF },
+{"th.vlseg2hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2HFFV, MASK_TH_VLSEG2HFFV, match_opcode, INSN_DREF },
+{"th.vlseg2wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2WFFV, MASK_TH_VLSEG2WFFV, match_opcode, INSN_DREF },
+{"th.vlseg2buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg2huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg2wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg2eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg3bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3BFFV, MASK_TH_VLSEG3BFFV, match_opcode, INSN_DREF },
+{"th.vlseg3hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3HFFV, MASK_TH_VLSEG3HFFV, match_opcode, INSN_DREF },
+{"th.vlseg3wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3WFFV, MASK_TH_VLSEG3WFFV, match_opcode, INSN_DREF },
+{"th.vlseg3buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg3huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg3wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg3eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg4bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4BFFV, MASK_TH_VLSEG4BFFV, match_opcode, INSN_DREF },
+{"th.vlseg4hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4HFFV, MASK_TH_VLSEG4HFFV, match_opcode, INSN_DREF },
+{"th.vlseg4wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4WFFV, MASK_TH_VLSEG4WFFV, match_opcode, INSN_DREF },
+{"th.vlseg4buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg4huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg4wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg4eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg5bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5BFFV, MASK_TH_VLSEG5BFFV, match_opcode, INSN_DREF },
+{"th.vlseg5hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5HFFV, MASK_TH_VLSEG5HFFV, match_opcode, INSN_DREF },
+{"th.vlseg5wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5WFFV, MASK_TH_VLSEG5WFFV, match_opcode, INSN_DREF },
+{"th.vlseg5buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg5huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg5wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg5eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg6bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6BFFV, MASK_TH_VLSEG6BFFV, match_opcode, INSN_DREF },
+{"th.vlseg6hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6HFFV, MASK_TH_VLSEG6HFFV, match_opcode, INSN_DREF },
+{"th.vlseg6wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6WFFV, MASK_TH_VLSEG6WFFV, match_opcode, INSN_DREF },
+{"th.vlseg6buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg6huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg6wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg6eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg7bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7BFFV, MASK_TH_VLSEG7BFFV, match_opcode, INSN_DREF },
+{"th.vlseg7hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7HFFV, MASK_TH_VLSEG7HFFV, match_opcode, INSN_DREF },
+{"th.vlseg7wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7WFFV, MASK_TH_VLSEG7WFFV, match_opcode, INSN_DREF },
+{"th.vlseg7buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg7huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg7wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg7eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg8bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8BFFV, MASK_TH_VLSEG8BFFV, match_opcode, INSN_DREF },
+{"th.vlseg8hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8HFFV, MASK_TH_VLSEG8HFFV, match_opcode, INSN_DREF },
+{"th.vlseg8wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8WFFV, MASK_TH_VLSEG8WFFV, match_opcode, INSN_DREF },
+{"th.vlseg8buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg8eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (4 preceding siblings ...)
  2023-11-18  7:05 ` [PATCH v2 05/12] RISC-V: Add load/store segment " Jin Ma
@ 2023-11-18  7:06 ` Jin Ma
  2023-11-18  7:07 ` [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
                   ` (6 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:06 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds the sub-extension "XTheadZvamo" for the
"XTheadVector" extension, and it provides AMO instructions
for T-Head VECTOR vendor extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add support
	for "XTheadZvamo" extension.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi:
	* testsuite/gas/riscv/x-thead-vector-zvamo.d: New test.
	* testsuite/gas/riscv/x-thead-vector-zvamo.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New.
	* opcode/riscv.h (enum riscv_insn_class): Add insn class.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 bfd/elfxx-riscv.c                             |  5 ++
 gas/doc/c-riscv.texi                          |  6 ++
 .../gas/riscv/x-thead-vector-zvamo.d          | 81 +++++++++++++++++++
 .../gas/riscv/x-thead-vector-zvamo.s          | 74 +++++++++++++++++
 include/opcode/riscv-opc.h                    | 37 ++++++++-
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 18 +++++
 7 files changed, 221 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e2c3ffe4b4f..97219b64011 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1374,6 +1374,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadvector",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadzvamo",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -2590,6 +2591,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadsync");
     case INSN_CLASS_XTHEADVECTOR:
       return riscv_subset_supports (rps, "xtheadvector");
+    case INSN_CLASS_XTHEADZVAMO:
+      return riscv_subset_supports (rps, "xtheadzvamo");
     case INSN_CLASS_XVENTANACONDOPS:
       return riscv_subset_supports (rps, "xventanacondops");
     default:
@@ -2836,6 +2839,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadsync";
     case INSN_CLASS_XTHEADVECTOR:
       return "xtheadvector";
+    case INSN_CLASS_XTHEADZVAMO:
+      return "xtheadzvamo";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index a7c9420bd86..763e89cc830 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -819,6 +819,12 @@ The XTheadVector extension provides instructions for thead vector.
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}.
 
+@item XTheadZvamo
+The XTheadZvamo extension is a subextension of the XTheadVector extension,
+and it provides AMO instructions for the T-Head VECTOR vendor extension.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}.
+
 @item XVentanaCondOps
 XVentanaCondOps extension provides instructions for branchless
 sequences that perform conditional arithmetic, conditional
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
new file mode 100644
index 00000000000..6b507ad66d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
@@ -0,0 +1,81 @@
+#as: -march=rv32if_xtheadvector_xtheadzvamo
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+0685e22f[ 	]+th.vamoaddw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0285e22f[ 	]+th.vamoaddw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0685f22f[ 	]+th.vamoaddd.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0285f22f[ 	]+th.vamoaddd.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0485e22f[ 	]+th.vamoaddw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0085e22f[ 	]+th.vamoaddw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0485f22f[ 	]+th.vamoaddd.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0085f22f[ 	]+th.vamoaddd.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0e85e22f[ 	]+th.vamoswapw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0a85e22f[ 	]+th.vamoswapw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0e85f22f[ 	]+th.vamoswapd.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0a85f22f[ 	]+th.vamoswapd.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+0c85e22f[ 	]+th.vamoswapw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0885e22f[ 	]+th.vamoswapw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c85f22f[ 	]+th.vamoswapd.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0885f22f[ 	]+th.vamoswapd.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+2685e22f[ 	]+th.vamoxorw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+2285e22f[ 	]+th.vamoxorw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+2685f22f[ 	]+th.vamoxord.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+2285f22f[ 	]+th.vamoxord.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+2485e22f[ 	]+th.vamoxorw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+2085e22f[ 	]+th.vamoxorw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+2485f22f[ 	]+th.vamoxord.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+2085f22f[ 	]+th.vamoxord.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6685e22f[ 	]+th.vamoandw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+6285e22f[ 	]+th.vamoandw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+6685f22f[ 	]+th.vamoandd.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+6285f22f[ 	]+th.vamoandd.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+6485e22f[ 	]+th.vamoandw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6085e22f[ 	]+th.vamoandw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6485f22f[ 	]+th.vamoandd.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6085f22f[ 	]+th.vamoandd.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4685e22f[ 	]+th.vamoorw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+4285e22f[ 	]+th.vamoorw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+4685f22f[ 	]+th.vamoord.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+4285f22f[ 	]+th.vamoord.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+4485e22f[ 	]+th.vamoorw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4085e22f[ 	]+th.vamoorw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4485f22f[ 	]+th.vamoord.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4085f22f[ 	]+th.vamoord.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8685e22f[ 	]+th.vamominw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+8285e22f[ 	]+th.vamominw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+8685f22f[ 	]+th.vamomind.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+8285f22f[ 	]+th.vamomind.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+8485e22f[ 	]+th.vamominw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8085e22f[ 	]+th.vamominw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8485f22f[ 	]+th.vamomind.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8085f22f[ 	]+th.vamomind.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a685e22f[ 	]+th.vamomaxw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+a285e22f[ 	]+th.vamomaxw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+a685f22f[ 	]+th.vamomaxd.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+a285f22f[ 	]+th.vamomaxd.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+a485e22f[ 	]+th.vamomaxw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a085e22f[ 	]+th.vamomaxw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a485f22f[ 	]+th.vamomaxd.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a085f22f[ 	]+th.vamomaxd.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c685e22f[ 	]+th.vamominuw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+c285e22f[ 	]+th.vamominuw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+c685f22f[ 	]+th.vamominud.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+c285f22f[ 	]+th.vamominud.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+c485e22f[ 	]+th.vamominuw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c085e22f[ 	]+th.vamominuw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c485f22f[ 	]+th.vamominud.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c085f22f[ 	]+th.vamominud.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e685e22f[ 	]+th.vamomaxuw.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+e285e22f[ 	]+th.vamomaxuw.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+e685f22f[ 	]+th.vamomaxud.v[ 	]+v4,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+e285f22f[ 	]+th.vamomaxud.v[ 	]+zero,v8,\(a1\),v4
+[ 	]+[0-9a-f]+:[ 	]+e485e22f[ 	]+th.vamomaxuw.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e085e22f[ 	]+th.vamomaxuw.v[ 	]+zero,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e485f22f[ 	]+th.vamomaxud.v[ 	]+v4,v8,\(a1\),v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e085f22f[ 	]+th.vamomaxud.v[ 	]+zero,v8,\(a1\),v4,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s
new file mode 100644
index 00000000000..9d55a1f0076
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s
@@ -0,0 +1,74 @@
+	th.vamoaddw.v v4, v8, (a1), v4
+	th.vamoaddw.v x0, v8, (a1), v4
+	th.vamoaddd.v v4, v8, (a1), v4
+	th.vamoaddd.v x0, v8, (a1), v4
+	th.vamoaddw.v v4, v8, (a1), v4, v0.t
+	th.vamoaddw.v x0, v8, (a1), v4, v0.t
+	th.vamoaddd.v v4, v8, (a1), v4, v0.t
+	th.vamoaddd.v x0, v8, (a1), v4, v0.t
+	th.vamoswapw.v v4, v8, (a1), v4
+	th.vamoswapw.v x0, v8, (a1), v4
+	th.vamoswapd.v v4, v8, (a1), v4
+	th.vamoswapd.v x0, v8, (a1), v4
+	th.vamoswapw.v v4, v8, (a1), v4, v0.t
+	th.vamoswapw.v x0, v8, (a1), v4, v0.t
+	th.vamoswapd.v v4, v8, (a1), v4, v0.t
+	th.vamoswapd.v x0, v8, (a1), v4, v0.t
+
+	th.vamoxorw.v v4, v8, (a1), v4
+	th.vamoxorw.v x0, v8, (a1), v4
+	th.vamoxord.v v4, v8, (a1), v4
+	th.vamoxord.v x0, v8, (a1), v4
+	th.vamoxorw.v v4, v8, (a1), v4, v0.t
+	th.vamoxorw.v x0, v8, (a1), v4, v0.t
+	th.vamoxord.v v4, v8, (a1), v4, v0.t
+	th.vamoxord.v x0, v8, (a1), v4, v0.t
+	th.vamoandw.v v4, v8, (a1), v4
+	th.vamoandw.v x0, v8, (a1), v4
+	th.vamoandd.v v4, v8, (a1), v4
+	th.vamoandd.v x0, v8, (a1), v4
+	th.vamoandw.v v4, v8, (a1), v4, v0.t
+	th.vamoandw.v x0, v8, (a1), v4, v0.t
+	th.vamoandd.v v4, v8, (a1), v4, v0.t
+	th.vamoandd.v x0, v8, (a1), v4, v0.t
+	th.vamoorw.v v4, v8, (a1), v4
+	th.vamoorw.v x0, v8, (a1), v4
+	th.vamoord.v v4, v8, (a1), v4
+	th.vamoord.v x0, v8, (a1), v4
+	th.vamoorw.v v4, v8, (a1), v4, v0.t
+	th.vamoorw.v x0, v8, (a1), v4, v0.t
+	th.vamoord.v v4, v8, (a1), v4, v0.t
+	th.vamoord.v x0, v8, (a1), v4, v0.t
+
+	th.vamominw.v v4, v8, (a1), v4
+	th.vamominw.v x0, v8, (a1), v4
+	th.vamomind.v v4, v8, (a1), v4
+	th.vamomind.v x0, v8, (a1), v4
+	th.vamominw.v v4, v8, (a1), v4, v0.t
+	th.vamominw.v x0, v8, (a1), v4, v0.t
+	th.vamomind.v v4, v8, (a1), v4, v0.t
+	th.vamomind.v x0, v8, (a1), v4, v0.t
+	th.vamomaxw.v v4, v8, (a1), v4
+	th.vamomaxw.v x0, v8, (a1), v4
+	th.vamomaxd.v v4, v8, (a1), v4
+	th.vamomaxd.v x0, v8, (a1), v4
+	th.vamomaxw.v v4, v8, (a1), v4, v0.t
+	th.vamomaxw.v x0, v8, (a1), v4, v0.t
+	th.vamomaxd.v v4, v8, (a1), v4, v0.t
+	th.vamomaxd.v x0, v8, (a1), v4, v0.t
+	th.vamominuw.v v4, v8, (a1), v4
+	th.vamominuw.v x0, v8, (a1), v4
+	th.vamominud.v v4, v8, (a1), v4
+	th.vamominud.v x0, v8, (a1), v4
+	th.vamominuw.v v4, v8, (a1), v4, v0.t
+	th.vamominuw.v x0, v8, (a1), v4, v0.t
+	th.vamominud.v v4, v8, (a1), v4, v0.t
+	th.vamominud.v x0, v8, (a1), v4, v0.t
+	th.vamomaxuw.v v4, v8, (a1), v4
+	th.vamomaxuw.v x0, v8, (a1), v4
+	th.vamomaxud.v v4, v8, (a1), v4
+	th.vamomaxud.v x0, v8, (a1), v4
+	th.vamomaxuw.v v4, v8, (a1), v4, v0.t
+	th.vamomaxuw.v x0, v8, (a1), v4, v0.t
+	th.vamomaxud.v v4, v8, (a1), v4, v0.t
+	th.vamomaxud.v x0, v8, (a1), v4, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6556de2b17d..58618a46b4d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2849,7 +2849,42 @@
 #define MASK_TH_VLSEG8HFFV 0xfdf0707f
 #define MATCH_TH_VLSEG8WFFV 0xf1006007
 #define MASK_TH_VLSEG8WFFV 0xfdf0707f
-
+#define MATCH_TH_VAMOADDWV 0x0000602f
+#define MASK_TH_VAMOADDWV 0xf800707f
+#define MATCH_TH_VAMOADDDV 0x0000702f
+#define MASK_TH_VAMOADDDV 0xf800707f
+#define MATCH_TH_VAMOSWAPWV 0x0800602f
+#define MASK_TH_VAMOSWAPWV 0xf800707f
+#define MATCH_TH_VAMOSWAPDV 0x0800702f
+#define MASK_TH_VAMOSWAPDV 0xf800707f
+#define MATCH_TH_VAMOXORWV 0x2000602f
+#define MASK_TH_VAMOXORWV 0xf800707f
+#define MATCH_TH_VAMOXORDV 0x2000702f
+#define MASK_TH_VAMOXORDV 0xf800707f
+#define MATCH_TH_VAMOANDWV 0x6000602f
+#define MASK_TH_VAMOANDWV 0xf800707f
+#define MATCH_TH_VAMOANDDV 0x6000702f
+#define MASK_TH_VAMOANDDV 0xf800707f
+#define MATCH_TH_VAMOORWV 0x4000602f
+#define MASK_TH_VAMOORWV 0xf800707f
+#define MATCH_TH_VAMOORDV 0x4000702f
+#define MASK_TH_VAMOORDV 0xf800707f
+#define MATCH_TH_VAMOMINWV 0x8000602f
+#define MASK_TH_VAMOMINWV 0xf800707f
+#define MATCH_TH_VAMOMINDV 0x8000702f
+#define MASK_TH_VAMOMINDV 0xf800707f
+#define MATCH_TH_VAMOMAXWV 0xa000602f
+#define MASK_TH_VAMOMAXWV 0xf800707f
+#define MATCH_TH_VAMOMAXDV 0xa000702f
+#define MASK_TH_VAMOMAXDV 0xf800707f
+#define MATCH_TH_VAMOMINUWV 0xc000602f
+#define MASK_TH_VAMOMINUWV 0xf800707f
+#define MATCH_TH_VAMOMINUDV 0xc000702f
+#define MASK_TH_VAMOMINUDV 0xf800707f
+#define MATCH_TH_VAMOMAXUWV 0xe000602f
+#define MASK_TH_VAMOMAXUWV 0xf800707f
+#define MATCH_TH_VAMOMAXUDV 0xe000702f
+#define MASK_TH_VAMOMAXUDV 0xf800707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a26ef8abf12..3099c9e256c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -468,6 +468,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
   INSN_CLASS_XTHEADVECTOR,
+  INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
 };
 
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 71e4453cd43..51b9956ad96 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2561,6 +2561,24 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF },
 {"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF },
 {"th.vlseg8eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF },
+{"th.vamoaddw.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDWV, MASK_TH_VAMOADDWV, match_opcode, INSN_DREF},
+{"th.vamoaddd.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDDV, MASK_TH_VAMOADDDV, match_opcode, INSN_DREF},
+{"th.vamoswapw.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPWV, MASK_TH_VAMOSWAPWV, match_opcode, INSN_DREF},
+{"th.vamoswapd.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPDV, MASK_TH_VAMOSWAPDV, match_opcode, INSN_DREF},
+{"th.vamoxorw.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORWV, MASK_TH_VAMOXORWV, match_opcode, INSN_DREF},
+{"th.vamoxord.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORDV, MASK_TH_VAMOXORDV, match_opcode, INSN_DREF},
+{"th.vamoandw.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDWV, MASK_TH_VAMOANDWV, match_opcode, INSN_DREF},
+{"th.vamoandd.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDDV, MASK_TH_VAMOANDDV, match_opcode, INSN_DREF},
+{"th.vamoorw.v",    0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORWV, MASK_TH_VAMOORWV, match_opcode, INSN_DREF},
+{"th.vamoord.v",    0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORDV, MASK_TH_VAMOORDV, match_opcode, INSN_DREF},
+{"th.vamominw.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINWV, MASK_TH_VAMOMINWV, match_opcode, INSN_DREF},
+{"th.vamomind.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINDV, MASK_TH_VAMOMINDV, match_opcode, INSN_DREF},
+{"th.vamomaxw.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXWV, MASK_TH_VAMOMAXWV, match_opcode, INSN_DREF},
+{"th.vamomaxd.v",   0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXDV, MASK_TH_VAMOMAXDV, match_opcode, INSN_DREF},
+{"th.vamominuw.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUWV, MASK_TH_VAMOMINUWV, match_opcode, INSN_DREF},
+{"th.vamominud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF},
+{"th.vamomaxuw.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF},
+{"th.vamomaxud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (5 preceding siblings ...)
  2023-11-18  7:06 ` [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
@ 2023-11-18  7:07 ` Jin Ma
  2023-11-18  7:07 ` [PATCH v2 08/12] RISC-V: Add fixed-point " Jin Ma
                   ` (5 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:07 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds integer arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	integer arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VADCVVM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 322 ++++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 335 +++++++++++++++++++++++
 include/opcode/riscv-opc.h               |  12 +
 opcodes/riscv-opc.c                      | 143 ++++++++++
 4 files changed, 812 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 90ea839457a..c5ad56e1e58 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -982,3 +982,325 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+e3057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+e1057207[ 	]+th.vlseg8eff.v[ 	]+v4,\(a0\),v0.t
+[ 	]+[0-9a-f]+:[ 	]+02860257[ 	]+th.vadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0285c257[ 	]+th.vadd.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0287b257[ 	]+th.vadd.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+02883257[ 	]+th.vadd.vi[ 	]+v4,v8,-16
+[ 	]+[0-9a-f]+:[ 	]+00860257[ 	]+th.vadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0085c257[ 	]+th.vadd.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0087b257[ 	]+th.vadd.vi[ 	]+v4,v8,15,v0.t
+[ 	]+[0-9a-f]+:[ 	]+00883257[ 	]+th.vadd.vi[ 	]+v4,v8,-16,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0a860257[ 	]+th.vsub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0a85c257[ 	]+th.vsub.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0e85c257[ 	]+th.vrsub.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0e87b257[ 	]+th.vrsub.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+0e883257[ 	]+th.vrsub.vi[ 	]+v4,v8,-16
+[ 	]+[0-9a-f]+:[ 	]+08860257[ 	]+th.vsub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0885c257[ 	]+th.vsub.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c85c257[ 	]+th.vrsub.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c87b257[ 	]+th.vrsub.vi[ 	]+v4,v8,15,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c883257[ 	]+th.vrsub.vi[ 	]+v4,v8,-16,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c6806257[ 	]+th.vwcvt.x.x.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+c2806257[ 	]+th.vwcvtu.x.x.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+c4806257[ 	]+th.vwcvt.x.x.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c0806257[ 	]+th.vwcvtu.x.x.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c2862257[ 	]+th.vwaddu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c285e257[ 	]+th.vwaddu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+c0862257[ 	]+th.vwaddu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c085e257[ 	]+th.vwaddu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ca862257[ 	]+th.vwsubu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ca85e257[ 	]+th.vwsubu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+c8862257[ 	]+th.vwsubu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c885e257[ 	]+th.vwsubu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c6862257[ 	]+th.vwadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c685e257[ 	]+th.vwadd.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+c4862257[ 	]+th.vwadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c485e257[ 	]+th.vwadd.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ce862257[ 	]+th.vwsub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ce85e257[ 	]+th.vwsub.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+cc862257[ 	]+th.vwsub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+cc85e257[ 	]+th.vwsub.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d2862257[ 	]+th.vwaddu.wv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d285e257[ 	]+th.vwaddu.wx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+d0862257[ 	]+th.vwaddu.wv[ 	]+v4,v8,v12,v0.t
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+[ 	]+[0-9a-f]+:[ 	]+d8862257[ 	]+th.vwsubu.wv[ 	]+v4,v8,v12,v0.t
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+[ 	]+[0-9a-f]+:[ 	]+4285c257[ 	]+th.vadc.vxm[ 	]+v4,v8,a1,v0
+[ 	]+[0-9a-f]+:[ 	]+4287b257[ 	]+th.vadc.vim[ 	]+v4,v8,15,v0
+[ 	]+[0-9a-f]+:[ 	]+42883257[ 	]+th.vadc.vim[ 	]+v4,v8,-16,v0
+[ 	]+[0-9a-f]+:[ 	]+46860257[ 	]+th.vmadc.vvm[ 	]+v4,v8,v12,v0
+[ 	]+[0-9a-f]+:[ 	]+4685c257[ 	]+th.vmadc.vxm[ 	]+v4,v8,a1,v0
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+[ 	]+[0-9a-f]+:[ 	]+2c883257[ 	]+th.vxor.vi[ 	]+v4,v8,-16,v0.t
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+[ 	]+[0-9a-f]+:[ 	]+a080b257[ 	]+th.vsrl.vi[ 	]+v4,v8,1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a08fb257[ 	]+th.vsrl.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a6860257[ 	]+th.vsra.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+a685c257[ 	]+th.vsra.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+a680b257[ 	]+th.vsra.vi[ 	]+v4,v8,1
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+[ 	]+[0-9a-f]+:[ 	]+a4860257[ 	]+th.vsra.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a485c257[ 	]+th.vsra.vx[ 	]+v4,v8,a1,v0.t
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+[ 	]+[0-9a-f]+:[ 	]+ac862257[ 	]+th.vnmsub.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac85e257[ 	]+th.vnmsub.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f2862257[ 	]+th.vwmaccu.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f285e257[ 	]+th.vwmaccu.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+f0862257[ 	]+th.vwmaccu.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f085e257[ 	]+th.vwmaccu.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f6862257[ 	]+th.vwmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f685e257[ 	]+th.vwmacc.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+f4862257[ 	]+th.vwmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f485e257[ 	]+th.vwmacc.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+fa862257[ 	]+th.vwmaccsu.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+fa85e257[ 	]+th.vwmaccsu.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+f8862257[ 	]+th.vwmaccsu.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f885e257[ 	]+th.vwmaccsu.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+fe85e257[ 	]+th.vwmaccus.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+fc85e257[ 	]+th.vwmaccus.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+82862257[ 	]+th.vdivu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8285e257[ 	]+th.vdivu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+80862257[ 	]+th.vdivu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8085e257[ 	]+th.vdivu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+86862257[ 	]+th.vdiv.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8685e257[ 	]+th.vdiv.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+84862257[ 	]+th.vdiv.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8485e257[ 	]+th.vdiv.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8a862257[ 	]+th.vremu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8a85e257[ 	]+th.vremu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+88862257[ 	]+th.vremu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8885e257[ 	]+th.vremu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8e862257[ 	]+th.vrem.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8e85e257[ 	]+th.vrem.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+8c862257[ 	]+th.vrem.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8c85e257[ 	]+th.vrem.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5c860257[ 	]+th.vmerge.vvm[ 	]+v4,v8,v12,v0
+[ 	]+[0-9a-f]+:[ 	]+5c85c257[ 	]+th.vmerge.vxm[ 	]+v4,v8,a1,v0
+[ 	]+[0-9a-f]+:[ 	]+5c87b257[ 	]+th.vmerge.vim[ 	]+v4,v8,15,v0
+[ 	]+[0-9a-f]+:[ 	]+5c883257[ 	]+th.vmerge.vim[ 	]+v4,v8,-16,v0
+[ 	]+[0-9a-f]+:[ 	]+5e060457[ 	]+th.vmv.v.v[ 	]+v8,v12
+[ 	]+[0-9a-f]+:[ 	]+5e05c457[ 	]+th.vmv.v.x[ 	]+v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5e07b457[ 	]+th.vmv.v.i[ 	]+v8,15
+[ 	]+[0-9a-f]+:[ 	]+5e083457[ 	]+th.vmv.v.i[ 	]+v8,-16
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index d356c016c2f..9235de70694 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1005,3 +1005,338 @@
 	th.vlseg8eff.v v4, (a0)
 	th.vlseg8eff.v v4, 0(a0)
 	th.vlseg8eff.v v4, (a0), v0.t
+
+	th.vadd.vv v4, v8, v12
+	th.vadd.vx v4, v8, a1
+	th.vadd.vi v4, v8, 15
+	th.vadd.vi v4, v8, -16
+	th.vadd.vv v4, v8, v12, v0.t
+	th.vadd.vx v4, v8, a1, v0.t
+	th.vadd.vi v4, v8, 15, v0.t
+	th.vadd.vi v4, v8, -16, v0.t
+	th.vsub.vv v4, v8, v12
+	th.vsub.vx v4, v8, a1
+	th.vrsub.vx v4, v8, a1
+	th.vrsub.vi v4, v8, 15
+	th.vrsub.vi v4, v8, -16
+	th.vsub.vv v4, v8, v12, v0.t
+	th.vsub.vx v4, v8, a1, v0.t
+	th.vrsub.vx v4, v8, a1, v0.t
+	th.vrsub.vi v4, v8, 15, v0.t
+	th.vrsub.vi v4, v8, -16, v0.t
+
+	# Aliases
+	th.vwcvt.x.x.v v4, v8
+	th.vwcvtu.x.x.v v4, v8
+	th.vwcvt.x.x.v v4, v8, v0.t
+	th.vwcvtu.x.x.v v4, v8, v0.t
+
+	th.vwaddu.vv v4, v8, v12
+	th.vwaddu.vx v4, v8, a1
+	th.vwaddu.vv v4, v8, v12, v0.t
+	th.vwaddu.vx v4, v8, a1, v0.t
+	th.vwsubu.vv v4, v8, v12
+	th.vwsubu.vx v4, v8, a1
+	th.vwsubu.vv v4, v8, v12, v0.t
+	th.vwsubu.vx v4, v8, a1, v0.t
+	th.vwadd.vv v4, v8, v12
+	th.vwadd.vx v4, v8, a1
+	th.vwadd.vv v4, v8, v12, v0.t
+	th.vwadd.vx v4, v8, a1, v0.t
+	th.vwsub.vv v4, v8, v12
+	th.vwsub.vx v4, v8, a1
+	th.vwsub.vv v4, v8, v12, v0.t
+	th.vwsub.vx v4, v8, a1, v0.t
+	th.vwaddu.wv v4, v8, v12
+	th.vwaddu.wx v4, v8, a1
+	th.vwaddu.wv v4, v8, v12, v0.t
+	th.vwaddu.wx v4, v8, a1, v0.t
+	th.vwsubu.wv v4, v8, v12
+	th.vwsubu.wx v4, v8, a1
+	th.vwsubu.wv v4, v8, v12, v0.t
+	th.vwsubu.wx v4, v8, a1, v0.t
+	th.vwadd.wv v4, v8, v12
+	th.vwadd.wx v4, v8, a1
+	th.vwadd.wv v4, v8, v12, v0.t
+	th.vwadd.wx v4, v8, a1, v0.t
+	th.vwsub.wv v4, v8, v12
+	th.vwsub.wx v4, v8, a1
+	th.vwsub.wv v4, v8, v12, v0.t
+	th.vwsub.wx v4, v8, a1, v0.t
+
+	th.vadc.vvm v4, v8, v12, v0
+	th.vadc.vxm v4, v8, a1, v0
+	th.vadc.vim v4, v8, 15, v0
+	th.vadc.vim v4, v8, -16, v0
+	th.vmadc.vvm v4, v8, v12, v0
+	th.vmadc.vxm v4, v8, a1, v0
+	th.vmadc.vim v4, v8, 15, v0
+	th.vmadc.vim v4, v8, -16, v0
+	th.vsbc.vvm v4, v8, v12, v0
+	th.vsbc.vxm v4, v8, a1, v0
+	th.vmsbc.vvm v4, v8, v12, v0
+	th.vmsbc.vxm v4, v8, a1, v0
+
+	# Aliases
+	th.vnot.v v4, v8
+	th.vnot.v v4, v8, v0.t
+
+	th.vand.vv v4, v8, v12
+	th.vand.vx v4, v8, a1
+	th.vand.vi v4, v8, 15
+	th.vand.vi v4, v8, -16
+	th.vand.vv v4, v8, v12, v0.t
+	th.vand.vx v4, v8, a1, v0.t
+	th.vand.vi v4, v8, 15, v0.t
+	th.vand.vi v4, v8, -16, v0.t
+	th.vor.vv v4, v8, v12
+	th.vor.vx v4, v8, a1
+	th.vor.vi v4, v8, 15
+	th.vor.vi v4, v8, -16
+	th.vor.vv v4, v8, v12, v0.t
+	th.vor.vx v4, v8, a1, v0.t
+	th.vor.vi v4, v8, 15, v0.t
+	th.vor.vi v4, v8, -16, v0.t
+	th.vxor.vv v4, v8, v12
+	th.vxor.vx v4, v8, a1
+	th.vxor.vi v4, v8, 15
+	th.vxor.vi v4, v8, -16
+	th.vxor.vv v4, v8, v12, v0.t
+	th.vxor.vx v4, v8, a1, v0.t
+	th.vxor.vi v4, v8, 15, v0.t
+	th.vxor.vi v4, v8, -16, v0.t
+
+	th.vsll.vv v4, v8, v12
+	th.vsll.vx v4, v8, a1
+	th.vsll.vi v4, v8, 1
+	th.vsll.vi v4, v8, 31
+	th.vsll.vv v4, v8, v12, v0.t
+	th.vsll.vx v4, v8, a1, v0.t
+	th.vsll.vi v4, v8, 1, v0.t
+	th.vsll.vi v4, v8, 31, v0.t
+	th.vsrl.vv v4, v8, v12
+	th.vsrl.vx v4, v8, a1
+	th.vsrl.vi v4, v8, 1
+	th.vsrl.vi v4, v8, 31
+	th.vsrl.vv v4, v8, v12, v0.t
+	th.vsrl.vx v4, v8, a1, v0.t
+	th.vsrl.vi v4, v8, 1, v0.t
+	th.vsrl.vi v4, v8, 31, v0.t
+	th.vsra.vv v4, v8, v12
+	th.vsra.vx v4, v8, a1
+	th.vsra.vi v4, v8, 1
+	th.vsra.vi v4, v8, 31
+	th.vsra.vv v4, v8, v12, v0.t
+	th.vsra.vx v4, v8, a1, v0.t
+	th.vsra.vi v4, v8, 1, v0.t
+	th.vsra.vi v4, v8, 31, v0.t
+
+	th.vnsrl.vv v4, v8, v12
+	th.vnsrl.vx v4, v8, a1
+	th.vnsrl.vi v4, v8, 1
+	th.vnsrl.vi v4, v8, 31
+	th.vnsrl.vv v4, v8, v12, v0.t
+	th.vnsrl.vx v4, v8, a1, v0.t
+	th.vnsrl.vi v4, v8, 1, v0.t
+	th.vnsrl.vi v4, v8, 31, v0.t
+	th.vnsra.vv v4, v8, v12
+	th.vnsra.vx v4, v8, a1
+	th.vnsra.vi v4, v8, 1
+	th.vnsra.vi v4, v8, 31
+	th.vnsra.vv v4, v8, v12, v0.t
+	th.vnsra.vx v4, v8, a1, v0.t
+	th.vnsra.vi v4, v8, 1, v0.t
+	th.vnsra.vi v4, v8, 31, v0.t
+
+	# Aliases
+	th.vmsgt.vv v4, v8, v12
+	th.vmsgtu.vv v4, v8, v12
+	th.vmsge.vv v4, v8, v12
+	th.vmsgeu.vv v4, v8, v12
+	th.vmsgt.vv v4, v8, v12, v0.t
+	th.vmsgtu.vv v4, v8, v12, v0.t
+	th.vmsge.vv v4, v8, v12, v0.t
+	th.vmsgeu.vv v4, v8, v12, v0.t
+	th.vmslt.vi v4, v8, 16
+	th.vmslt.vi v4, v8, -15
+	th.vmsltu.vi v4, v8, 16
+	th.vmsltu.vi v4, v8, -15
+	th.vmsge.vi v4, v8, 16
+	th.vmsge.vi v4, v8, -15
+	th.vmsgeu.vi v4, v8, 16
+	th.vmsgeu.vi v4, v8, -15
+	th.vmslt.vi v4, v8, 16, v0.t
+	th.vmslt.vi v4, v8, -15, v0.t
+	th.vmsltu.vi v4, v8, 16, v0.t
+	th.vmsltu.vi v4, v8, -15, v0.t
+	th.vmsge.vi v4, v8, 16, v0.t
+	th.vmsge.vi v4, v8, -15, v0.t
+	th.vmsgeu.vi v4, v8, 16, v0.t
+	th.vmsgeu.vi v4, v8, -15, v0.t
+
+	# Macros
+	th.vmsge.vx v4, v8, a1
+	th.vmsgeu.vx v4, v8, a1
+	th.vmsge.vx v8, v12, a2, v0.t
+	th.vmsgeu.vx v8, v12, a2, v0.t
+	th.vmsge.vx v4, v8, a1, v0.t, v12
+	th.vmsgeu.vx v4, v8, a1, v0.t, v12
+
+	th.vmseq.vv v4, v8, v12
+	th.vmseq.vx v4, v8, a1
+	th.vmseq.vi v4, v8, 15
+	th.vmseq.vi v4, v8, -16
+	th.vmseq.vv v4, v8, v12, v0.t
+	th.vmseq.vx v4, v8, a1, v0.t
+	th.vmseq.vi v4, v8, 15, v0.t
+	th.vmseq.vi v4, v8, -16, v0.t
+	th.vmsne.vv v4, v8, v12
+	th.vmsne.vx v4, v8, a1
+	th.vmsne.vi v4, v8, 15
+	th.vmsne.vi v4, v8, -16
+	th.vmsne.vv v4, v8, v12, v0.t
+	th.vmsne.vx v4, v8, a1, v0.t
+	th.vmsne.vi v4, v8, 15, v0.t
+	th.vmsne.vi v4, v8, -16, v0.t
+	th.vmsltu.vv v4, v8, v12
+	th.vmsltu.vx v4, v8, a1
+	th.vmsltu.vv v4, v8, v12, v0.t
+	th.vmsltu.vx v4, v8, a1, v0.t
+	th.vmslt.vv v4, v8, v12
+	th.vmslt.vx v4, v8, a1
+	th.vmslt.vv v4, v8, v12, v0.t
+	th.vmslt.vx v4, v8, a1, v0.t
+	th.vmsleu.vv v4, v8, v12
+	th.vmsleu.vx v4, v8, a1
+	th.vmsleu.vi v4, v8, 15
+	th.vmsleu.vi v4, v8, -16
+	th.vmsleu.vv v4, v8, v12, v0.t
+	th.vmsleu.vx v4, v8, a1, v0.t
+	th.vmsleu.vi v4, v8, 15, v0.t
+	th.vmsleu.vi v4, v8, -16, v0.t
+	th.vmsle.vv v4, v8, v12
+	th.vmsle.vx v4, v8, a1
+	th.vmsle.vi v4, v8, 15
+	th.vmsle.vi v4, v8, -16
+	th.vmsle.vv v4, v8, v12, v0.t
+	th.vmsle.vx v4, v8, a1, v0.t
+	th.vmsle.vi v4, v8, 15, v0.t
+	th.vmsle.vi v4, v8, -16, v0.t
+	th.vmsgtu.vx v4, v8, a1
+	th.vmsgtu.vi v4, v8, 15
+	th.vmsgtu.vi v4, v8, -16
+	th.vmsgtu.vx v4, v8, a1, v0.t
+	th.vmsgtu.vi v4, v8, 15, v0.t
+	th.vmsgtu.vi v4, v8, -16, v0.t
+	th.vmsgt.vx v4, v8, a1
+	th.vmsgt.vi v4, v8, 15
+	th.vmsgt.vi v4, v8, -16
+	th.vmsgt.vx v4, v8, a1, v0.t
+	th.vmsgt.vi v4, v8, 15, v0.t
+	th.vmsgt.vi v4, v8, -16, v0.t
+
+	th.vminu.vv v4, v8, v12
+	th.vminu.vx v4, v8, a1
+	th.vminu.vv v4, v8, v12, v0.t
+	th.vminu.vx v4, v8, a1, v0.t
+	th.vmin.vv v4, v8, v12
+	th.vmin.vx v4, v8, a1
+	th.vmin.vv v4, v8, v12, v0.t
+	th.vmin.vx v4, v8, a1, v0.t
+	th.vmaxu.vv v4, v8, v12
+	th.vmaxu.vx v4, v8, a1
+	th.vmaxu.vv v4, v8, v12, v0.t
+	th.vmaxu.vx v4, v8, a1, v0.t
+	th.vmax.vv v4, v8, v12
+	th.vmax.vx v4, v8, a1
+	th.vmax.vv v4, v8, v12, v0.t
+	th.vmax.vx v4, v8, a1, v0.t
+
+	th.vmul.vv v4, v8, v12
+	th.vmul.vx v4, v8, a1
+	th.vmul.vv v4, v8, v12, v0.t
+	th.vmul.vx v4, v8, a1, v0.t
+	th.vmulh.vv v4, v8, v12
+	th.vmulh.vx v4, v8, a1
+	th.vmulh.vv v4, v8, v12, v0.t
+	th.vmulh.vx v4, v8, a1, v0.t
+	th.vmulhu.vv v4, v8, v12
+	th.vmulhu.vx v4, v8, a1
+	th.vmulhu.vv v4, v8, v12, v0.t
+	th.vmulhu.vx v4, v8, a1, v0.t
+	th.vmulhsu.vv v4, v8, v12
+	th.vmulhsu.vx v4, v8, a1
+	th.vmulhsu.vv v4, v8, v12, v0.t
+	th.vmulhsu.vx v4, v8, a1, v0.t
+
+	th.vwmul.vv v4, v8, v12
+	th.vwmul.vx v4, v8, a1
+	th.vwmul.vv v4, v8, v12, v0.t
+	th.vwmul.vx v4, v8, a1, v0.t
+	th.vwmulu.vv v4, v8, v12
+	th.vwmulu.vx v4, v8, a1
+	th.vwmulu.vv v4, v8, v12, v0.t
+	th.vwmulu.vx v4, v8, a1, v0.t
+	th.vwmulsu.vv v4, v8, v12
+	th.vwmulsu.vx v4, v8, a1
+	th.vwmulsu.vv v4, v8, v12, v0.t
+	th.vwmulsu.vx v4, v8, a1, v0.t
+
+	th.vmacc.vv v4, v12, v8
+	th.vmacc.vx v4, a1, v8
+	th.vmacc.vv v4, v12, v8, v0.t
+	th.vmacc.vx v4, a1, v8, v0.t
+	th.vnmsac.vv v4, v12, v8
+	th.vnmsac.vx v4, a1, v8
+	th.vnmsac.vv v4, v12, v8, v0.t
+	th.vnmsac.vx v4, a1, v8, v0.t
+	th.vmadd.vv v4, v12, v8
+	th.vmadd.vx v4, a1, v8
+	th.vmadd.vv v4, v12, v8, v0.t
+	th.vmadd.vx v4, a1, v8, v0.t
+	th.vnmsub.vv v4, v12, v8
+	th.vnmsub.vx v4, a1, v8
+	th.vnmsub.vv v4, v12, v8, v0.t
+	th.vnmsub.vx v4, a1, v8, v0.t
+
+	th.vwmaccu.vv v4, v12, v8
+	th.vwmaccu.vx v4, a1, v8
+	th.vwmaccu.vv v4, v12, v8, v0.t
+	th.vwmaccu.vx v4, a1, v8, v0.t
+	th.vwmacc.vv v4, v12, v8
+	th.vwmacc.vx v4, a1, v8
+	th.vwmacc.vv v4, v12, v8, v0.t
+	th.vwmacc.vx v4, a1, v8, v0.t
+	th.vwmaccsu.vv v4, v12, v8
+	th.vwmaccsu.vx v4, a1, v8
+	th.vwmaccsu.vv v4, v12, v8, v0.t
+	th.vwmaccsu.vx v4, a1, v8, v0.t
+	th.vwmaccus.vx v4, a1, v8
+	th.vwmaccus.vx v4, a1, v8, v0.t
+
+	th.vdivu.vv v4, v8, v12
+	th.vdivu.vx v4, v8, a1
+	th.vdivu.vv v4, v8, v12, v0.t
+	th.vdivu.vx v4, v8, a1, v0.t
+	th.vdiv.vv v4, v8, v12
+	th.vdiv.vx v4, v8, a1
+	th.vdiv.vv v4, v8, v12, v0.t
+	th.vdiv.vx v4, v8, a1, v0.t
+	th.vremu.vv v4, v8, v12
+	th.vremu.vx v4, v8, a1
+	th.vremu.vv v4, v8, v12, v0.t
+	th.vremu.vx v4, v8, a1, v0.t
+	th.vrem.vv v4, v8, v12
+	th.vrem.vx v4, v8, a1
+	th.vrem.vv v4, v8, v12, v0.t
+	th.vrem.vx v4, v8, a1, v0.t
+
+	th.vmerge.vvm v4, v8, v12, v0
+	th.vmerge.vxm v4, v8, a1, v0
+	th.vmerge.vim v4, v8, 15, v0
+	th.vmerge.vim v4, v8, -16, v0
+
+	th.vmv.v.v v8, v12
+	th.vmv.v.x v8, a1
+	th.vmv.v.i v8, 15
+	th.vmv.v.i v8, -16
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 58618a46b4d..df4b7abcedb 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2885,6 +2885,18 @@
 #define MASK_TH_VAMOMAXUWV 0xf800707f
 #define MATCH_TH_VAMOMAXUDV 0xe000702f
 #define MASK_TH_VAMOMAXUDV 0xf800707f
+#define MATCH_TH_VADCVVM 0x42000057
+#define MASK_TH_VADCVVM 0xfe00707f
+#define MATCH_TH_VADCVXM 0x42004057
+#define MASK_TH_VADCVXM 0xfe00707f
+#define MATCH_TH_VADCVIM 0x42003057
+#define MASK_TH_VADCVIM 0xfe00707f
+#define MATCH_TH_VSBCVVM 0x4a000057
+#define MASK_TH_VSBCVVM 0xfe00707f
+#define MATCH_TH_VSBCVXM 0x4a004057
+#define MASK_TH_VSBCVXM 0xfe00707f
+#define MATCH_TH_VWMACCSUVV 0xf8002057
+#define MASK_TH_VWMACCSUVV 0xfc00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 51b9956ad96..b0061ebb3f7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2579,6 +2579,149 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vamominud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF},
 {"th.vamomaxuw.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF},
 {"th.vamomaxud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF},
+{"th.vadd.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
+{"th.vadd.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
+{"th.vadd.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
+{"th.vsub.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
+{"th.vsub.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
+{"th.vrsub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
+{"th.vrsub.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
+{"th.vwcvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS },
+{"th.vwcvtu.x.x.v",0,INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS },
+{"th.vwaddu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 },
+{"th.vwaddu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 },
+{"th.vwsubu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 },
+{"th.vwsubu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 },
+{"th.vwadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 },
+{"th.vwadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 },
+{"th.vwsub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 },
+{"th.vwsub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 },
+{"th.vwaddu.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 },
+{"th.vwaddu.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 },
+{"th.vwsubu.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 },
+{"th.vwsubu.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 },
+{"th.vwadd.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 },
+{"th.vwadd.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 },
+{"th.vwsub.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 },
+{"th.vwsub.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 },
+{"th.vadc.vvm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_TH_VADCVVM, MASK_TH_VADCVVM, match_opcode, 0 },
+{"th.vadc.vxm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_TH_VADCVXM, MASK_TH_VADCVXM, match_opcode, 0 },
+{"th.vadc.vim",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_TH_VADCVIM, MASK_TH_VADCVIM, match_opcode, 0 },
+{"th.vmadc.vvm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
+{"th.vmadc.vxm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
+{"th.vmadc.vim",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
+{"th.vsbc.vvm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_TH_VSBCVVM, MASK_TH_VSBCVVM, match_opcode, 0 },
+{"th.vsbc.vxm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_TH_VSBCVXM, MASK_TH_VSBCVXM, match_opcode, 0 },
+{"th.vmsbc.vvm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
+{"th.vmsbc.vxm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
+{"th.vnot.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
+{"th.vand.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
+{"th.vand.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
+{"th.vand.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
+{"th.vor.vv",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
+{"th.vor.vx",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
+{"th.vor.vi",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
+{"th.vxor.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
+{"th.vxor.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
+{"th.vxor.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
+{"th.vsll.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
+{"th.vsll.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
+{"th.vsll.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
+{"th.vsrl.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
+{"th.vsrl.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
+{"th.vsrl.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
+{"th.vsra.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
+{"th.vsra.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
+{"th.vsra.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
+{"th.vnsrl.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 },
+{"th.vnsrl.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 },
+{"th.vnsrl.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 },
+{"th.vnsra.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_opcode, 0 },
+{"th.vnsra.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 },
+{"th.vnsra.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 },
+{"th.vmseq.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
+{"th.vmseq.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
+{"th.vmseq.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
+{"th.vmsne.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
+{"th.vmsne.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
+{"th.vmsne.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
+{"th.vmsltu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
+{"th.vmsltu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
+{"th.vmslt.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
+{"th.vmslt.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
+{"th.vmsleu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
+{"th.vmsleu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
+{"th.vmsleu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
+{"th.vmsle.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
+{"th.vmsle.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
+{"th.vmsle.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
+{"th.vmsgtu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
+{"th.vmsgtu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
+{"th.vmsgt.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
+{"th.vmsgt.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
+{"th.vmsgt.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
+{"th.vmsgtu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
+{"th.vmsge.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
+{"th.vmslt.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
+{"th.vmsltu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vx",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsge.vx",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vminu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
+{"th.vminu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
+{"th.vmin.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
+{"th.vmin.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
+{"th.vmaxu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
+{"th.vmaxu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
+{"th.vmax.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
+{"th.vmax.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
+{"th.vmul.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
+{"th.vmul.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
+{"th.vmulh.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
+{"th.vmulh.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
+{"th.vmulhu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
+{"th.vmulhu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
+{"th.vmulhsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
+{"th.vmulhsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
+{"th.vwmul.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 },
+{"th.vwmul.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 },
+{"th.vwmulu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 },
+{"th.vwmulu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 },
+{"th.vwmulsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 },
+{"th.vwmulsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 },
+{"th.vmacc.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
+{"th.vmacc.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
+{"th.vnmsac.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
+{"th.vnmsac.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
+{"th.vmadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
+{"th.vmadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
+{"th.vnmsub.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
+{"th.vnmsub.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
+{"th.vwmaccu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0},
+{"th.vwmaccu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0},
+{"th.vwmacc.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0},
+{"th.vwmacc.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0},
+{"th.vwmaccsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_TH_VWMACCSUVV, MASK_TH_VWMACCSUVV, match_opcode, 0},
+{"th.vwmaccsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_opcode, 0},
+{"th.vwmaccus.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_opcode, 0},
+{"th.vdivu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
+{"th.vdivu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
+{"th.vdiv.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
+{"th.vdiv.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
+{"th.vremu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
+{"th.vremu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
+{"th.vrem.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
+{"th.vrem.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
+{"th.vmerge.vvm", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
+{"th.vmerge.vxm", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
+{"th.vmerge.vim", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
+{"th.vmv.v.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
+{"th.vmv.v.x",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
+{"th.vmv.v.i",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 08/12] RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (6 preceding siblings ...)
  2023-11-18  7:07 ` [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
@ 2023-11-18  7:07 ` Jin Ma
  2023-11-18  7:07 ` [PATCH v2 09/12] RISC-V: Add floating-point " Jin Ma
                   ` (4 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:07 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	fixed-point arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 86 ++++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 92 ++++++++++++++++++++++++
 include/opcode/riscv-opc.h               | 12 ++++
 opcodes/riscv-opc.c                      | 36 ++++++++++
 4 files changed, 226 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index c5ad56e1e58..bbcf6d4890a 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1304,3 +1304,89 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+5e05c457[ 	]+th.vmv.v.x[ 	]+v8,a1
 [ 	]+[0-9a-f]+:[ 	]+5e07b457[ 	]+th.vmv.v.i[ 	]+v8,15
 [ 	]+[0-9a-f]+:[ 	]+5e083457[ 	]+th.vmv.v.i[ 	]+v8,-16
+[ 	]+[0-9a-f]+:[ 	]+82860257[ 	]+th.vsaddu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8285c257[ 	]+th.vsaddu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+8287b257[ 	]+th.vsaddu.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+82883257[ 	]+th.vsaddu.vi[ 	]+v4,v8,-16
+[ 	]+[0-9a-f]+:[ 	]+80860257[ 	]+th.vsaddu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8085c257[ 	]+th.vsaddu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8087b257[ 	]+th.vsaddu.vi[ 	]+v4,v8,15,v0.t
+[ 	]+[0-9a-f]+:[ 	]+80883257[ 	]+th.vsaddu.vi[ 	]+v4,v8,-16,v0.t
+[ 	]+[0-9a-f]+:[ 	]+86860257[ 	]+th.vsadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8685c257[ 	]+th.vsadd.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+8687b257[ 	]+th.vsadd.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+86883257[ 	]+th.vsadd.vi[ 	]+v4,v8,-16
+[ 	]+[0-9a-f]+:[ 	]+84860257[ 	]+th.vsadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8485c257[ 	]+th.vsadd.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8487b257[ 	]+th.vsadd.vi[ 	]+v4,v8,15,v0.t
+[ 	]+[0-9a-f]+:[ 	]+84883257[ 	]+th.vsadd.vi[ 	]+v4,v8,-16,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8a860257[ 	]+th.vssubu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8a85c257[ 	]+th.vssubu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+88860257[ 	]+th.vssubu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8885c257[ 	]+th.vssubu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8e860257[ 	]+th.vssub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+8e85c257[ 	]+th.vssub.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+8c860257[ 	]+th.vssub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8c85c257[ 	]+th.vssub.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+92860257[ 	]+th.vaadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9285c257[ 	]+th.vaadd.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+9287b257[ 	]+th.vaadd.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+92883257[ 	]+th.vaadd.vi[ 	]+v4,v8,-16
+[ 	]+[0-9a-f]+:[ 	]+90860257[ 	]+th.vaadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9085c257[ 	]+th.vaadd.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9087b257[ 	]+th.vaadd.vi[ 	]+v4,v8,15,v0.t
+[ 	]+[0-9a-f]+:[ 	]+90883257[ 	]+th.vaadd.vi[ 	]+v4,v8,-16,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9a860257[ 	]+th.vasub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9a85c257[ 	]+th.vasub.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+98860257[ 	]+th.vasub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9885c257[ 	]+th.vasub.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9e860257[ 	]+th.vsmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9e85c257[ 	]+th.vsmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+9c860257[ 	]+th.vsmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9c85c257[ 	]+th.vsmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f2860257[ 	]+th.vwsmaccu.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f285c257[ 	]+th.vwsmaccu.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+f6860257[ 	]+th.vwsmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f685c257[ 	]+th.vwsmacc.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+fa860257[ 	]+th.vwsmaccsu.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+fa85c257[ 	]+th.vwsmaccsu.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+fe85c257[ 	]+th.vwsmaccus.vx[ 	]+v4,a1,v8
+[ 	]+[0-9a-f]+:[ 	]+f0860257[ 	]+th.vwsmaccu.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f085c257[ 	]+th.vwsmaccu.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f4860257[ 	]+th.vwsmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f485c257[ 	]+th.vwsmacc.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f8860257[ 	]+th.vwsmaccsu.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f885c257[ 	]+th.vwsmaccsu.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+fc85c257[ 	]+th.vwsmaccus.vx[ 	]+v4,a1,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+aa860257[ 	]+th.vssrl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+aa85c257[ 	]+th.vssrl.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+aa80b257[ 	]+th.vssrl.vi[ 	]+v4,v8,1
+[ 	]+[0-9a-f]+:[ 	]+aa8fb257[ 	]+th.vssrl.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+a8860257[ 	]+th.vssrl.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a885c257[ 	]+th.vssrl.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a880b257[ 	]+th.vssrl.vi[ 	]+v4,v8,1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a88fb257[ 	]+th.vssrl.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ae860257[ 	]+th.vssra.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ae85c257[ 	]+th.vssra.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+ae80b257[ 	]+th.vssra.vi[ 	]+v4,v8,1
+[ 	]+[0-9a-f]+:[ 	]+ae8fb257[ 	]+th.vssra.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+ac860257[ 	]+th.vssra.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac85c257[ 	]+th.vssra.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac80b257[ 	]+th.vssra.vi[ 	]+v4,v8,1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac8fb257[ 	]+th.vssra.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ba860257[ 	]+th.vnclipu.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ba85c257[ 	]+th.vnclipu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+ba80b257[ 	]+th.vnclipu.vi[ 	]+v4,v8,1
+[ 	]+[0-9a-f]+:[ 	]+ba8fb257[ 	]+th.vnclipu.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+b8860257[ 	]+th.vnclipu.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b885c257[ 	]+th.vnclipu.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b880b257[ 	]+th.vnclipu.vi[ 	]+v4,v8,1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b88fb257[ 	]+th.vnclipu.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+be860257[ 	]+th.vnclip.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be85c257[ 	]+th.vnclip.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+be80b257[ 	]+th.vnclip.vi[ 	]+v4,v8,1
+[ 	]+[0-9a-f]+:[ 	]+be8fb257[ 	]+th.vnclip.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+bc860257[ 	]+th.vnclip.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+bc85c257[ 	]+th.vnclip.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+bc80b257[ 	]+th.vnclip.vi[ 	]+v4,v8,1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+bc8fb257[ 	]+th.vnclip.vi[ 	]+v4,v8,31,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 9235de70694..97a0e1a5d79 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1340,3 +1340,95 @@
 	th.vmv.v.x v8, a1
 	th.vmv.v.i v8, 15
 	th.vmv.v.i v8, -16
+
+	th.vsaddu.vv v4, v8, v12
+	th.vsaddu.vx v4, v8, a1
+	th.vsaddu.vi v4, v8, 15
+	th.vsaddu.vi v4, v8, -16
+	th.vsaddu.vv v4, v8, v12, v0.t
+	th.vsaddu.vx v4, v8, a1, v0.t
+	th.vsaddu.vi v4, v8, 15, v0.t
+	th.vsaddu.vi v4, v8, -16, v0.t
+	th.vsadd.vv v4, v8, v12
+	th.vsadd.vx v4, v8, a1
+	th.vsadd.vi v4, v8, 15
+	th.vsadd.vi v4, v8, -16
+	th.vsadd.vv v4, v8, v12, v0.t
+	th.vsadd.vx v4, v8, a1, v0.t
+	th.vsadd.vi v4, v8, 15, v0.t
+	th.vsadd.vi v4, v8, -16, v0.t
+	th.vssubu.vv v4, v8, v12
+	th.vssubu.vx v4, v8, a1
+	th.vssubu.vv v4, v8, v12, v0.t
+	th.vssubu.vx v4, v8, a1, v0.t
+	th.vssub.vv v4, v8, v12
+	th.vssub.vx v4, v8, a1
+	th.vssub.vv v4, v8, v12, v0.t
+	th.vssub.vx v4, v8, a1, v0.t
+
+	th.vaadd.vv v4, v8, v12
+	th.vaadd.vx v4, v8, a1
+	th.vaadd.vi v4, v8, 15
+	th.vaadd.vi v4, v8, -16
+	th.vaadd.vv v4, v8, v12, v0.t
+	th.vaadd.vx v4, v8, a1, v0.t
+	th.vaadd.vi v4, v8, 15, v0.t
+	th.vaadd.vi v4, v8, -16, v0.t
+	th.vasub.vv v4, v8, v12
+	th.vasub.vx v4, v8, a1
+	th.vasub.vv v4, v8, v12, v0.t
+	th.vasub.vx v4, v8, a1, v0.t
+
+	th.vsmul.vv v4, v8, v12
+	th.vsmul.vx v4, v8, a1
+	th.vsmul.vv v4, v8, v12, v0.t
+	th.vsmul.vx v4, v8, a1, v0.t
+
+	th.vwsmaccu.vv v4, v12, v8
+	th.vwsmaccu.vx v4, a1, v8
+	th.vwsmacc.vv v4, v12, v8
+	th.vwsmacc.vx v4, a1, v8
+	th.vwsmaccsu.vv v4, v12, v8
+	th.vwsmaccsu.vx v4, a1, v8
+	th.vwsmaccus.vx v4, a1, v8
+	th.vwsmaccu.vv v4, v12, v8, v0.t
+	th.vwsmaccu.vx v4, a1, v8, v0.t
+	th.vwsmacc.vv v4, v12, v8, v0.t
+	th.vwsmacc.vx v4, a1, v8, v0.t
+	th.vwsmaccsu.vv v4, v12, v8, v0.t
+	th.vwsmaccsu.vx v4, a1, v8, v0.t
+	th.vwsmaccus.vx v4, a1, v8, v0.t
+
+	th.vssrl.vv v4, v8, v12
+	th.vssrl.vx v4, v8, a1
+	th.vssrl.vi v4, v8, 1
+	th.vssrl.vi v4, v8, 31
+	th.vssrl.vv v4, v8, v12, v0.t
+	th.vssrl.vx v4, v8, a1, v0.t
+	th.vssrl.vi v4, v8, 1, v0.t
+	th.vssrl.vi v4, v8, 31, v0.t
+	th.vssra.vv v4, v8, v12
+	th.vssra.vx v4, v8, a1
+	th.vssra.vi v4, v8, 1
+	th.vssra.vi v4, v8, 31
+	th.vssra.vv v4, v8, v12, v0.t
+	th.vssra.vx v4, v8, a1, v0.t
+	th.vssra.vi v4, v8, 1, v0.t
+	th.vssra.vi v4, v8, 31, v0.t
+
+	th.vnclipu.vv v4, v8, v12
+	th.vnclipu.vx v4, v8, a1
+	th.vnclipu.vi v4, v8, 1
+	th.vnclipu.vi v4, v8, 31
+	th.vnclipu.vv v4, v8, v12, v0.t
+	th.vnclipu.vx v4, v8, a1, v0.t
+	th.vnclipu.vi v4, v8, 1, v0.t
+	th.vnclipu.vi v4, v8, 31, v0.t
+	th.vnclip.vv v4, v8, v12
+	th.vnclip.vx v4, v8, a1
+	th.vnclip.vi v4, v8, 1
+	th.vnclip.vi v4, v8, 31
+	th.vnclip.vv v4, v8, v12, v0.t
+	th.vnclip.vx v4, v8, a1, v0.t
+	th.vnclip.vi v4, v8, 1, v0.t
+	th.vnclip.vi v4, v8, 31, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index df4b7abcedb..5cca4c5bb43 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2897,6 +2897,18 @@
 #define MASK_TH_VSBCVXM 0xfe00707f
 #define MATCH_TH_VWMACCSUVV 0xf8002057
 #define MASK_TH_VWMACCSUVV 0xfc00707f
+#define MATCH_TH_VAADDVV 0x90000057
+#define MASK_TH_VAADDVV 0xfc00707f
+#define MATCH_TH_VAADDVX 0x90004057
+#define MASK_TH_VAADDVX 0xfc00707f
+#define MATCH_TH_VAADDVI 0x90003057
+#define MASK_TH_VAADDVI 0xfc00707f
+#define MATCH_TH_VASUBVV 0x98000057
+#define MASK_TH_VASUBVV 0xfc00707f
+#define MATCH_TH_VASUBVX 0x98004057
+#define MASK_TH_VASUBVX 0xfc00707f
+#define MATCH_TH_VWSMACCSUVV 0xf8000057
+#define MASK_TH_VWSMACCSUVV 0xfc00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b0061ebb3f7..6a8d41df0e6 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2722,6 +2722,42 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vmv.v.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
 {"th.vmv.v.x",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
 {"th.vmv.v.i",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+{"th.vsaddu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
+{"th.vsaddu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
+{"th.vsaddu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
+{"th.vsadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
+{"th.vsadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
+{"th.vsadd.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
+{"th.vssubu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
+{"th.vssubu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
+{"th.vssub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
+{"th.vssub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
+{"th.vaadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 },
+{"th.vaadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 },
+{"th.vaadd.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 },
+{"th.vasub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 },
+{"th.vasub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 },
+{"th.vsmul.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
+{"th.vsmul.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
+{"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_opcode, 0 },
+{"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_opcode, 0 },
+{"th.vwsmacc.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_opcode, 0 },
+{"th.vwsmacc.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_opcode, 0 },
+{"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 },
+{"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_opcode, 0 },
+{"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_opcode, 0 },
+{"th.vssrl.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
+{"th.vssrl.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
+{"th.vssrl.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
+{"th.vssra.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
+{"th.vssra.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
+{"th.vssra.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
+{"th.vnclipu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 },
+{"th.vnclipu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 },
+{"th.vnclipu.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 },
+{"th.vnclip.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
+{"th.vnclip.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
+{"th.vnclip.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 09/12] RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (7 preceding siblings ...)
  2023-11-18  7:07 ` [PATCH v2 08/12] RISC-V: Add fixed-point " Jin Ma
@ 2023-11-18  7:07 ` Jin Ma
  2023-11-18  7:08 ` [PATCH v2 10/12] RISC-V: Add reductions " Jin Ma
                   ` (3 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:07 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	floating-point arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 170 ++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 188 +++++++++++++++++++++++
 include/opcode/riscv-opc.h               |  36 +++++
 opcodes/riscv-opc.c                      |  86 +++++++++++
 4 files changed, 480 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index bbcf6d4890a..178e2465110 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1390,3 +1390,173 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+bc85c257[ 	]+th.vnclip.vx[ 	]+v4,v8,a1,v0.t
 [ 	]+[0-9a-f]+:[ 	]+bc80b257[ 	]+th.vnclip.vi[ 	]+v4,v8,1,v0.t
 [ 	]+[0-9a-f]+:[ 	]+bc8fb257[ 	]+th.vnclip.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+02861257[ 	]+th.vfadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+02865257[ 	]+th.vfadd.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+00861257[ 	]+th.vfadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+00865257[ 	]+th.vfadd.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0a861257[ 	]+th.vfsub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0a865257[ 	]+th.vfsub.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+08861257[ 	]+th.vfsub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+08865257[ 	]+th.vfsub.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9e865257[ 	]+th.vfrsub.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+9c865257[ 	]+th.vfrsub.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c2861257[ 	]+th.vfwadd.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c2865257[ 	]+th.vfwadd.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+c0861257[ 	]+th.vfwadd.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c0865257[ 	]+th.vfwadd.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ca861257[ 	]+th.vfwsub.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+ca865257[ 	]+th.vfwsub.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+c8861257[ 	]+th.vfwsub.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c8865257[ 	]+th.vfwsub.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d2861257[ 	]+th.vfwadd.wv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+d2865257[ 	]+th.vfwadd.wf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+d0861257[ 	]+th.vfwadd.wv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d0865257[ 	]+th.vfwadd.wf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+da861257[ 	]+th.vfwsub.wv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+da865257[ 	]+th.vfwsub.wf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+d8861257[ 	]+th.vfwsub.wv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+d8865257[ 	]+th.vfwsub.wf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+92861257[ 	]+th.vfmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+92865257[ 	]+th.vfmul.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+90861257[ 	]+th.vfmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+90865257[ 	]+th.vfmul.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+82861257[ 	]+th.vfdiv.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+82865257[ 	]+th.vfdiv.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+80861257[ 	]+th.vfdiv.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+80865257[ 	]+th.vfdiv.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+86865257[ 	]+th.vfrdiv.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+84865257[ 	]+th.vfrdiv.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e2861257[ 	]+th.vfwmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+e2865257[ 	]+th.vfwmul.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+e0861257[ 	]+th.vfwmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+e0865257[ 	]+th.vfwmul.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a2861257[ 	]+th.vfmadd.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+a2865257[ 	]+th.vfmadd.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+a6861257[ 	]+th.vfnmadd.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+a6865257[ 	]+th.vfnmadd.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+aa861257[ 	]+th.vfmsub.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+aa865257[ 	]+th.vfmsub.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+ae861257[ 	]+th.vfnmsub.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+ae865257[ 	]+th.vfnmsub.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+a0861257[ 	]+th.vfmadd.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a0865257[ 	]+th.vfmadd.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a4861257[ 	]+th.vfnmadd.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a4865257[ 	]+th.vfnmadd.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a8861257[ 	]+th.vfmsub.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+a8865257[ 	]+th.vfmsub.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac861257[ 	]+th.vfnmsub.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ac865257[ 	]+th.vfnmsub.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b2861257[ 	]+th.vfmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+b2865257[ 	]+th.vfmacc.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+b6861257[ 	]+th.vfnmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+b6865257[ 	]+th.vfnmacc.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+ba861257[ 	]+th.vfmsac.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+ba865257[ 	]+th.vfmsac.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+be861257[ 	]+th.vfnmsac.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+be865257[ 	]+th.vfnmsac.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+b0861257[ 	]+th.vfmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b0865257[ 	]+th.vfmacc.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b4861257[ 	]+th.vfnmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b4865257[ 	]+th.vfnmacc.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b8861257[ 	]+th.vfmsac.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b8865257[ 	]+th.vfmsac.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+bc861257[ 	]+th.vfnmsac.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+bc865257[ 	]+th.vfnmsac.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f2861257[ 	]+th.vfwmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f2865257[ 	]+th.vfwmacc.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+f6861257[ 	]+th.vfwnmacc.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+f6865257[ 	]+th.vfwnmacc.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+fa861257[ 	]+th.vfwmsac.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+fa865257[ 	]+th.vfwmsac.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+fe861257[ 	]+th.vfwnmsac.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+fe865257[ 	]+th.vfwnmsac.vf[ 	]+v4,fa2,v8
+[ 	]+[0-9a-f]+:[ 	]+f0861257[ 	]+th.vfwmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f0865257[ 	]+th.vfwmacc.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f4861257[ 	]+th.vfwnmacc.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f4865257[ 	]+th.vfwnmacc.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f8861257[ 	]+th.vfwmsac.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+f8865257[ 	]+th.vfwmsac.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+fc861257[ 	]+th.vfwnmsac.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+fc865257[ 	]+th.vfwnmsac.vf[ 	]+v4,fa2,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8e801257[ 	]+th.vfsqrt.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8c801257[ 	]+th.vfsqrt.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+12861257[ 	]+th.vfmin.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+12865257[ 	]+th.vfmin.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+1a861257[ 	]+th.vfmax.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1a865257[ 	]+th.vfmax.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+10861257[ 	]+th.vfmin.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+10865257[ 	]+th.vfmin.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+18861257[ 	]+th.vfmax.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+18865257[ 	]+th.vfmax.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+22861257[ 	]+th.vfsgnj.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+22865257[ 	]+th.vfsgnj.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+26861257[ 	]+th.vfsgnjn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+26865257[ 	]+th.vfsgnjn.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+2a861257[ 	]+th.vfsgnjx.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+2a865257[ 	]+th.vfsgnjx.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+20861257[ 	]+th.vfsgnj.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+20865257[ 	]+th.vfsgnj.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+24861257[ 	]+th.vfsgnjn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+24865257[ 	]+th.vfsgnjn.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+28861257[ 	]+th.vfsgnjx.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+28865257[ 	]+th.vfsgnjx.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6ec41257[ 	]+th.vmflt.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+66c41257[ 	]+th.vmfle.vv[ 	]+v4,v12,v8
+[ 	]+[0-9a-f]+:[ 	]+6cc41257[ 	]+th.vmflt.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+64c41257[ 	]+th.vmfle.vv[ 	]+v4,v12,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62861257[ 	]+th.vmfeq.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+62865257[ 	]+th.vmfeq.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+72861257[ 	]+th.vmfne.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+72865257[ 	]+th.vmfne.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+6e861257[ 	]+th.vmflt.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6e865257[ 	]+th.vmflt.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+66861257[ 	]+th.vmfle.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+66865257[ 	]+th.vmfle.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+76865257[ 	]+th.vmfgt.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+7e865257[ 	]+th.vmfge.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+60861257[ 	]+th.vmfeq.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+60865257[ 	]+th.vmfeq.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+70861257[ 	]+th.vmfne.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+70865257[ 	]+th.vmfne.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6c861257[ 	]+th.vmflt.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6c865257[ 	]+th.vmflt.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+64861257[ 	]+th.vmfle.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+64865257[ 	]+th.vmfle.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+74865257[ 	]+th.vmfgt.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+7c865257[ 	]+th.vmfge.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6a861257[ 	]+th.vmford.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6a865257[ 	]+th.vmford.vf[ 	]+v4,v8,fa2
+[ 	]+[0-9a-f]+:[ 	]+68861257[ 	]+th.vmford.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+68865257[ 	]+th.vmford.vf[ 	]+v4,v8,fa2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8e881257[ 	]+th.vfclass.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8c881257[ 	]+th.vfclass.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5c865257[ 	]+th.vfmerge.vfm[ 	]+v4,v8,fa2,v0
+[ 	]+[0-9a-f]+:[ 	]+5e05d257[ 	]+th.vfmv.v.f[ 	]+v4,fa1
+[ 	]+[0-9a-f]+:[ 	]+8a801257[ 	]+th.vfcvt.xu.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a809257[ 	]+th.vfcvt.x.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a811257[ 	]+th.vfcvt.f.xu.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a819257[ 	]+th.vfcvt.f.x.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+88801257[ 	]+th.vfcvt.xu.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88809257[ 	]+th.vfcvt.x.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88811257[ 	]+th.vfcvt.f.xu.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88819257[ 	]+th.vfcvt.f.x.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8a841257[ 	]+th.vfwcvt.xu.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a849257[ 	]+th.vfwcvt.x.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a851257[ 	]+th.vfwcvt.f.xu.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a859257[ 	]+th.vfwcvt.f.x.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a861257[ 	]+th.vfwcvt.f.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+88841257[ 	]+th.vfwcvt.xu.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88849257[ 	]+th.vfwcvt.x.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88851257[ 	]+th.vfwcvt.f.xu.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88859257[ 	]+th.vfwcvt.f.x.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88861257[ 	]+th.vfwcvt.f.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+8a881257[ 	]+th.vfncvt.xu.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a889257[ 	]+th.vfncvt.x.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a891257[ 	]+th.vfncvt.f.xu.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a899257[ 	]+th.vfncvt.f.x.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a8a1257[ 	]+th.vfncvt.f.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+88881257[ 	]+th.vfncvt.xu.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88889257[ 	]+th.vfncvt.x.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88891257[ 	]+th.vfncvt.f.xu.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+88899257[ 	]+th.vfncvt.f.x.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+888a1257[ 	]+th.vfncvt.f.f.v[ 	]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 97a0e1a5d79..92e90068b7f 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1432,3 +1432,191 @@
 	th.vnclip.vx v4, v8, a1, v0.t
 	th.vnclip.vi v4, v8, 1, v0.t
 	th.vnclip.vi v4, v8, 31, v0.t
+
+	th.vfadd.vv v4, v8, v12
+	th.vfadd.vf v4, v8, fa2
+	th.vfadd.vv v4, v8, v12, v0.t
+	th.vfadd.vf v4, v8, fa2, v0.t
+	th.vfsub.vv v4, v8, v12
+	th.vfsub.vf v4, v8, fa2
+	th.vfsub.vv v4, v8, v12, v0.t
+	th.vfsub.vf v4, v8, fa2, v0.t
+	th.vfrsub.vf v4, v8, fa2
+	th.vfrsub.vf v4, v8, fa2, v0.t
+
+	th.vfwadd.vv v4, v8, v12
+	th.vfwadd.vf v4, v8, fa2
+	th.vfwadd.vv v4, v8, v12, v0.t
+	th.vfwadd.vf v4, v8, fa2, v0.t
+	th.vfwsub.vv v4, v8, v12
+	th.vfwsub.vf v4, v8, fa2
+	th.vfwsub.vv v4, v8, v12, v0.t
+	th.vfwsub.vf v4, v8, fa2, v0.t
+	th.vfwadd.wv v4, v8, v12
+	th.vfwadd.wf v4, v8, fa2
+	th.vfwadd.wv v4, v8, v12, v0.t
+	th.vfwadd.wf v4, v8, fa2, v0.t
+	th.vfwsub.wv v4, v8, v12
+	th.vfwsub.wf v4, v8, fa2
+	th.vfwsub.wv v4, v8, v12, v0.t
+	th.vfwsub.wf v4, v8, fa2, v0.t
+
+	th.vfmul.vv v4, v8, v12
+	th.vfmul.vf v4, v8, fa2
+	th.vfmul.vv v4, v8, v12, v0.t
+	th.vfmul.vf v4, v8, fa2, v0.t
+	th.vfdiv.vv v4, v8, v12
+	th.vfdiv.vf v4, v8, fa2
+	th.vfdiv.vv v4, v8, v12, v0.t
+	th.vfdiv.vf v4, v8, fa2, v0.t
+	th.vfrdiv.vf v4, v8, fa2
+	th.vfrdiv.vf v4, v8, fa2, v0.t
+
+	th.vfwmul.vv v4, v8, v12
+	th.vfwmul.vf v4, v8, fa2
+	th.vfwmul.vv v4, v8, v12, v0.t
+	th.vfwmul.vf v4, v8, fa2, v0.t
+
+	th.vfmadd.vv v4, v12, v8
+	th.vfmadd.vf v4, fa2, v8
+	th.vfnmadd.vv v4, v12, v8
+	th.vfnmadd.vf v4, fa2, v8
+	th.vfmsub.vv v4, v12, v8
+	th.vfmsub.vf v4, fa2, v8
+	th.vfnmsub.vv v4, v12, v8
+	th.vfnmsub.vf v4, fa2, v8
+	th.vfmadd.vv v4, v12, v8, v0.t
+	th.vfmadd.vf v4, fa2, v8, v0.t
+	th.vfnmadd.vv v4, v12, v8, v0.t
+	th.vfnmadd.vf v4, fa2, v8, v0.t
+	th.vfmsub.vv v4, v12, v8, v0.t
+	th.vfmsub.vf v4, fa2, v8, v0.t
+	th.vfnmsub.vv v4, v12, v8, v0.t
+	th.vfnmsub.vf v4, fa2, v8, v0.t
+	th.vfmacc.vv v4, v12, v8
+	th.vfmacc.vf v4, fa2, v8
+	th.vfnmacc.vv v4, v12, v8
+	th.vfnmacc.vf v4, fa2, v8
+	th.vfmsac.vv v4, v12, v8
+	th.vfmsac.vf v4, fa2, v8
+	th.vfnmsac.vv v4, v12, v8
+	th.vfnmsac.vf v4, fa2, v8
+	th.vfmacc.vv v4, v12, v8, v0.t
+	th.vfmacc.vf v4, fa2, v8, v0.t
+	th.vfnmacc.vv v4, v12, v8, v0.t
+	th.vfnmacc.vf v4, fa2, v8, v0.t
+	th.vfmsac.vv v4, v12, v8, v0.t
+	th.vfmsac.vf v4, fa2, v8, v0.t
+	th.vfnmsac.vv v4, v12, v8, v0.t
+	th.vfnmsac.vf v4, fa2, v8, v0.t
+
+	th.vfwmacc.vv v4, v12, v8
+	th.vfwmacc.vf v4, fa2, v8
+	th.vfwnmacc.vv v4, v12, v8
+	th.vfwnmacc.vf v4, fa2, v8
+	th.vfwmsac.vv v4, v12, v8
+	th.vfwmsac.vf v4, fa2, v8
+	th.vfwnmsac.vv v4, v12, v8
+	th.vfwnmsac.vf v4, fa2, v8
+	th.vfwmacc.vv v4, v12, v8, v0.t
+	th.vfwmacc.vf v4, fa2, v8, v0.t
+	th.vfwnmacc.vv v4, v12, v8, v0.t
+	th.vfwnmacc.vf v4, fa2, v8, v0.t
+	th.vfwmsac.vv v4, v12, v8, v0.t
+	th.vfwmsac.vf v4, fa2, v8, v0.t
+	th.vfwnmsac.vv v4, v12, v8, v0.t
+	th.vfwnmsac.vf v4, fa2, v8, v0.t
+
+	th.vfsqrt.v v4, v8
+	th.vfsqrt.v v4, v8, v0.t
+
+	th.vfmin.vv v4, v8, v12
+	th.vfmin.vf v4, v8, fa2
+	th.vfmax.vv v4, v8, v12
+	th.vfmax.vf v4, v8, fa2
+	th.vfmin.vv v4, v8, v12, v0.t
+	th.vfmin.vf v4, v8, fa2, v0.t
+	th.vfmax.vv v4, v8, v12, v0.t
+	th.vfmax.vf v4, v8, fa2, v0.t
+
+	th.vfsgnj.vv v4, v8, v12
+	th.vfsgnj.vf v4, v8, fa2
+	th.vfsgnjn.vv v4, v8, v12
+	th.vfsgnjn.vf v4, v8, fa2
+	th.vfsgnjx.vv v4, v8, v12
+	th.vfsgnjx.vf v4, v8, fa2
+	th.vfsgnj.vv v4, v8, v12, v0.t
+	th.vfsgnj.vf v4, v8, fa2, v0.t
+	th.vfsgnjn.vv v4, v8, v12, v0.t
+	th.vfsgnjn.vf v4, v8, fa2, v0.t
+	th.vfsgnjx.vv v4, v8, v12, v0.t
+	th.vfsgnjx.vf v4, v8, fa2, v0.t
+
+	# Aliases
+	th.vmfgt.vv v4, v8, v12
+	th.vmfge.vv v4, v8, v12
+	th.vmfgt.vv v4, v8, v12, v0.t
+	th.vmfge.vv v4, v8, v12, v0.t
+
+	th.vmfeq.vv v4, v8, v12
+	th.vmfeq.vf v4, v8, fa2
+	th.vmfne.vv v4, v8, v12
+	th.vmfne.vf v4, v8, fa2
+	th.vmflt.vv v4, v8, v12
+	th.vmflt.vf v4, v8, fa2
+	th.vmfle.vv v4, v8, v12
+	th.vmfle.vf v4, v8, fa2
+	th.vmfgt.vf v4, v8, fa2
+	th.vmfge.vf v4, v8, fa2
+	th.vmfeq.vv v4, v8, v12, v0.t
+	th.vmfeq.vf v4, v8, fa2, v0.t
+	th.vmfne.vv v4, v8, v12, v0.t
+	th.vmfne.vf v4, v8, fa2, v0.t
+	th.vmflt.vv v4, v8, v12, v0.t
+	th.vmflt.vf v4, v8, fa2, v0.t
+	th.vmfle.vv v4, v8, v12, v0.t
+	th.vmfle.vf v4, v8, fa2, v0.t
+	th.vmfgt.vf v4, v8, fa2, v0.t
+	th.vmfge.vf v4, v8, fa2, v0.t
+
+	th.vmford.vv v4, v8, v12
+	th.vmford.vf v4, v8, fa2
+	th.vmford.vv v4, v8, v12, v0.t
+	th.vmford.vf v4, v8, fa2, v0.t
+
+	th.vfclass.v v4, v8
+	th.vfclass.v v4, v8, v0.t
+
+	th.vfmerge.vfm v4, v8, fa2, v0
+	th.vfmv.v.f v4, fa1
+
+	th.vfcvt.xu.f.v v4, v8
+	th.vfcvt.x.f.v v4, v8
+	th.vfcvt.f.xu.v v4, v8
+	th.vfcvt.f.x.v v4, v8
+	th.vfcvt.xu.f.v v4, v8, v0.t
+	th.vfcvt.x.f.v v4, v8, v0.t
+	th.vfcvt.f.xu.v v4, v8, v0.t
+	th.vfcvt.f.x.v v4, v8, v0.t
+
+	th.vfwcvt.xu.f.v v4, v8
+	th.vfwcvt.x.f.v v4, v8
+	th.vfwcvt.f.xu.v v4, v8
+	th.vfwcvt.f.x.v v4, v8
+	th.vfwcvt.f.f.v v4, v8
+	th.vfwcvt.xu.f.v v4, v8, v0.t
+	th.vfwcvt.x.f.v v4, v8, v0.t
+	th.vfwcvt.f.xu.v v4, v8, v0.t
+	th.vfwcvt.f.x.v v4, v8, v0.t
+	th.vfwcvt.f.f.v v4, v8, v0.t
+
+	th.vfncvt.xu.f.v v4, v8
+	th.vfncvt.x.f.v v4, v8
+	th.vfncvt.f.xu.v v4, v8
+	th.vfncvt.f.x.v v4, v8
+	th.vfncvt.f.f.v v4, v8
+	th.vfncvt.xu.f.v v4, v8, v0.t
+	th.vfncvt.x.f.v v4, v8, v0.t
+	th.vfncvt.f.xu.v v4, v8, v0.t
+	th.vfncvt.f.x.v v4, v8, v0.t
+	th.vfncvt.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 5cca4c5bb43..2e5b4fe63ee 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2909,6 +2909,42 @@
 #define MASK_TH_VASUBVX 0xfc00707f
 #define MATCH_TH_VWSMACCSUVV 0xf8000057
 #define MASK_TH_VWSMACCSUVV 0xfc00707f
+#define MATCH_TH_VFSQRTV 0x8c001057
+#define MASK_TH_VFSQRTV 0xfc0ff07f
+#define MATCH_TH_VMFORDVV 0x68001057
+#define MASK_TH_VMFORDVV 0xfc00707f
+#define MATCH_TH_VMFORDVF 0x68005057
+#define MASK_TH_VMFORDVF 0xfc00707f
+#define MATCH_TH_VFCLASSV 0x8c081057
+#define MASK_TH_VFCLASSV 0xfc0ff07f
+#define MATCH_TH_VFCVTXUFV 0x88001057
+#define MASK_TH_VFCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFCVTXFV 0x88009057
+#define MASK_TH_VFCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXUV 0x88011057
+#define MASK_TH_VFCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXV 0x88019057
+#define MASK_TH_VFCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXUFV 0x88041057
+#define MASK_TH_VFWCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXFV 0x88049057
+#define MASK_TH_VFWCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXUV 0x88051057
+#define MASK_TH_VFWCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXV 0x88059057
+#define MASK_TH_VFWCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFFV 0x88061057
+#define MASK_TH_VFWCVTFFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXUFV 0x88081057
+#define MASK_TH_VFNCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXFV 0x88089057
+#define MASK_TH_VFNCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXUV 0x88091057
+#define MASK_TH_VFNCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXV 0x88099057
+#define MASK_TH_VFNCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFFV 0x880a1057
+#define MASK_TH_VFNCVTFFV 0xfc0ff07f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6a8d41df0e6..31689a63948 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2758,6 +2758,92 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vnclip.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
 {"th.vnclip.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
 {"th.vnclip.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
+{"th.vfadd.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
+{"th.vfadd.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
+{"th.vfsub.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
+{"th.vfsub.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
+{"th.vfrsub.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
+{"th.vfwadd.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0},
+{"th.vfwadd.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0},
+{"th.vfwsub.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0},
+{"th.vfwsub.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0},
+{"th.vfwadd.wv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0},
+{"th.vfwsub.wv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0},
+{"th.vfwadd.wf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0},
+{"th.vfwsub.wf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0},
+{"th.vfmul.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
+{"th.vfmul.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
+{"th.vfdiv.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
+{"th.vfdiv.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
+{"th.vfrdiv.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
+{"th.vfwmul.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0},
+{"th.vfwmul.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0},
+{"th.vfmadd.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
+{"th.vfmadd.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
+{"th.vfnmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
+{"th.vfnmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
+{"th.vfmsub.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
+{"th.vfmsub.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
+{"th.vfnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
+{"th.vfnmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
+{"th.vfmacc.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
+{"th.vfmacc.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
+{"th.vfnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
+{"th.vfnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
+{"th.vfmsac.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
+{"th.vfmsac.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
+{"th.vfnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
+{"th.vfnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
+{"th.vfwmacc.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0},
+{"th.vfwmacc.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0},
+{"th.vfwnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0},
+{"th.vfwnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0},
+{"th.vfwmsac.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0},
+{"th.vfwmsac.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0},
+{"th.vfwnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0},
+{"th.vfwnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0},
+{"th.vfsqrt.v",   0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFSQRTV, MASK_TH_VFSQRTV, match_opcode, 0},
+{"th.vfmin.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
+{"th.vfmin.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
+{"th.vfmax.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
+{"th.vfmax.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
+{"th.vfsgnj.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
+{"th.vfsgnj.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
+{"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
+{"th.vfsgnjn.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
+{"th.vfsgnjx.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
+{"th.vfsgnjx.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
+{"th.vmfeq.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
+{"th.vmfeq.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
+{"th.vmfne.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
+{"th.vmfne.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
+{"th.vmflt.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
+{"th.vmflt.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
+{"th.vmfle.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
+{"th.vmfle.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
+{"th.vmfgt.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
+{"th.vmfge.vf",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
+{"th.vmfgt.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
+{"th.vmfge.vv",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
+{"th.vmford.vv",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFORDVV, MASK_TH_VMFORDVV, match_opcode, 0},
+{"th.vmford.vf",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFORDVF, MASK_TH_VMFORDVF, match_opcode, 0},
+{"th.vfclass.v",  0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCLASSV, MASK_TH_VFCLASSV, match_opcode, 0},
+{"th.vfmerge.vfm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+{"th.vfmv.v.f",   0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+{"th.vfcvt.xu.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXUFV, MASK_TH_VFCVTXUFV, match_opcode, 0},
+{"th.vfcvt.x.f.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXFV, MASK_TH_VFCVTXFV, match_opcode, 0},
+{"th.vfcvt.f.xu.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXUV, MASK_TH_VFCVTFXUV, match_opcode, 0},
+{"th.vfcvt.f.x.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXV, MASK_TH_VFCVTFXV, match_opcode, 0},
+{"th.vfwcvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXUFV, MASK_TH_VFWCVTXUFV, match_opcode, 0},
+{"th.vfwcvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXFV, MASK_TH_VFWCVTXFV, match_opcode, 0},
+{"th.vfwcvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXUV, MASK_TH_VFWCVTFXUV, match_opcode, 0},
+{"th.vfwcvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXV, MASK_TH_VFWCVTFXV, match_opcode, 0},
+{"th.vfwcvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFFV, MASK_TH_VFWCVTFFV, match_opcode, 0},
+{"th.vfncvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXUFV, MASK_TH_VFNCVTXUFV, match_opcode, 0},
+{"th.vfncvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXFV, MASK_TH_VFNCVTXFV, match_opcode, 0},
+{"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
+{"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
+{"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 10/12] RISC-V: Add reductions instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (8 preceding siblings ...)
  2023-11-18  7:07 ` [PATCH v2 09/12] RISC-V: Add floating-point " Jin Ma
@ 2023-11-18  7:08 ` Jin Ma
  2023-11-18  7:08 ` [PATCH v2 11/12] RISC-V: Add vector mask " Jin Ma
                   ` (2 subsequent siblings)
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:08 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds reductions instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	reductions instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 32 +++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 36 ++++++++++++++++++++++++
 opcodes/riscv-opc.c                      | 16 +++++++++++
 3 files changed, 84 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 178e2465110..2c80eeb13e5 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1560,3 +1560,35 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+88891257[ 	]+th.vfncvt.f.xu.v[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+88899257[ 	]+th.vfncvt.f.x.v[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+888a1257[ 	]+th.vfncvt.f.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+02862257[ 	]+th.vredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1a842257[ 	]+th.vredmaxu.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+1e842257[ 	]+th.vredmax.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+12842257[ 	]+th.vredminu.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+16842257[ 	]+th.vredmin.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+06862257[ 	]+th.vredand.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0a862257[ 	]+th.vredor.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0e862257[ 	]+th.vredxor.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+00862257[ 	]+th.vredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+18842257[ 	]+th.vredmaxu.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+1c842257[ 	]+th.vredmax.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+10842257[ 	]+th.vredminu.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+14842257[ 	]+th.vredmin.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04862257[ 	]+th.vredand.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+08862257[ 	]+th.vredor.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c862257[ 	]+th.vredxor.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c2860257[ 	]+th.vwredsumu.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6860257[ 	]+th.vwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+th.vwredsumu.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+th.vwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+th.vfredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+th.vfredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+th.vfredmax.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+th.vfredmin.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+th.vfredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+th.vfredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+th.vfredmax.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+th.vfredmin.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+th.vfwredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+th.vfwredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 92e90068b7f..71f83a25dc6 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1620,3 +1620,39 @@
 	th.vfncvt.f.xu.v v4, v8, v0.t
 	th.vfncvt.f.x.v v4, v8, v0.t
 	th.vfncvt.f.f.v v4, v8, v0.t
+
+	th.vredsum.vs v4, v8, v12
+	th.vredmaxu.vs v4, v8, v8
+	th.vredmax.vs v4, v8, v8
+	th.vredminu.vs v4, v8, v8
+	th.vredmin.vs v4, v8, v8
+	th.vredand.vs v4, v8, v12
+	th.vredor.vs v4, v8, v12
+	th.vredxor.vs v4, v8, v12
+	th.vredsum.vs v4, v8, v12, v0.t
+	th.vredmaxu.vs v4, v8, v8, v0.t
+	th.vredmax.vs v4, v8, v8, v0.t
+	th.vredminu.vs v4, v8, v8, v0.t
+	th.vredmin.vs v4, v8, v8, v0.t
+	th.vredand.vs v4, v8, v12, v0.t
+	th.vredor.vs v4, v8, v12, v0.t
+	th.vredxor.vs v4, v8, v12, v0.t
+
+	th.vwredsumu.vs v4, v8, v12
+	th.vwredsum.vs v4, v8, v12
+	th.vwredsumu.vs v4, v8, v12, v0.t
+	th.vwredsum.vs v4, v8, v12, v0.t
+
+	th.vfredosum.vs v4, v8, v12
+	th.vfredsum.vs v4, v8, v12
+	th.vfredmax.vs v4, v8, v12
+	th.vfredmin.vs v4, v8, v12
+	th.vfredosum.vs v4, v8, v12, v0.t
+	th.vfredsum.vs v4, v8, v12, v0.t
+	th.vfredmax.vs v4, v8, v12, v0.t
+	th.vfredmin.vs v4, v8, v12, v0.t
+
+	th.vfwredosum.vs v4, v8, v12
+	th.vfwredsum.vs v4, v8, v12
+	th.vfwredosum.vs v4, v8, v12, v0.t
+	th.vfwredsum.vs v4, v8, v12, v0.t
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 31689a63948..2dde9ca4a0a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2844,6 +2844,22 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
 {"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
 {"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
+{"th.vredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
+{"th.vredmaxu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
+{"th.vredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
+{"th.vredminu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
+{"th.vredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
+{"th.vredand.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
+{"th.vredor.vs",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
+{"th.vredxor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
+{"th.vwredsumu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
+{"th.vwredsum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
+{"th.vfredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
+{"th.vfredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
+{"th.vfredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
+{"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
+{"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
+{"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 11/12] RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (9 preceding siblings ...)
  2023-11-18  7:08 ` [PATCH v2 10/12] RISC-V: Add reductions " Jin Ma
@ 2023-11-18  7:08 ` Jin Ma
  2023-11-18  7:08 ` [PATCH v2 12/12] RISC-V: Add vector permutation " Jin Ma
  2023-11-23  2:37 ` [PATCH v2 00/12] RISC-V: Add " Nelson Chu
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:08 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds mask instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	mask instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 26 ++++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 30 ++++++++++++++++++++++++
 include/opcode/riscv-opc.h               | 14 +++++++++++
 opcodes/riscv-opc.c                      | 19 +++++++++++++++
 4 files changed, 89 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 2c80eeb13e5..03d8ede7c77 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1592,3 +1592,29 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+th.vfwredosum.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+th.vmcpy.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+th.vmclr.m[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+th.vmset.m[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+th.vmnot.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+th.vmand.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+th.vmnand.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+th.vmandnot.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+th.vmxor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+th.vmor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+th.vmnor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+th.vmornot.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+th.vmxnor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+52c02557[ 	]+th.vmpopc.m[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+56c02557[ 	]+th.vmfirst.m[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+5a80a257[ 	]+th.vmsbf.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5a81a257[ 	]+th.vmsif.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5a812257[ 	]+th.vmsof.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5a882257[ 	]+th.viota.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5a08a257[ 	]+th.vid.v[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+50c02557[ 	]+th.vmpopc.m[ 	]+a0,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+54c02557[ 	]+th.vmfirst.m[ 	]+a0,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5880a257[ 	]+th.vmsbf.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5881a257[ 	]+th.vmsif.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+58812257[ 	]+th.vmsof.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+58882257[ 	]+th.viota.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5808a257[ 	]+th.vid.v[ 	]+v4,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 71f83a25dc6..1c1c27cb6d8 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1656,3 +1656,33 @@
 	th.vfwredsum.vs v4, v8, v12
 	th.vfwredosum.vs v4, v8, v12, v0.t
 	th.vfwredsum.vs v4, v8, v12, v0.t
+
+	# Aliases
+	th.vmcpy.m v4, v8
+	th.vmclr.m v4
+	th.vmset.m v4
+	th.vmnot.m v4, v8
+
+	th.vmand.mm v4, v8, v12
+	th.vmnand.mm v4, v8, v12
+	th.vmandnot.mm v4, v8, v12
+	th.vmxor.mm v4, v8, v12
+	th.vmor.mm v4, v8, v12
+	th.vmnor.mm v4, v8, v12
+	th.vmornot.mm v4, v8, v12
+	th.vmxnor.mm v4, v8, v12
+
+	th.vmpopc.m a0, v12
+	th.vmfirst.m a0, v12
+	th.vmsbf.m v4, v8
+	th.vmsif.m v4, v8
+	th.vmsof.m v4, v8
+	th.viota.m v4, v8
+	th.vid.v v4
+	th.vmpopc.m a0, v12, v0.t
+	th.vmfirst.m a0, v12, v0.t
+	th.vmsbf.m v4, v8, v0.t
+	th.vmsif.m v4, v8, v0.t
+	th.vmsof.m v4, v8, v0.t
+	th.viota.m v4, v8, v0.t
+	th.vid.v v4, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2e5b4fe63ee..9b4288c8ee2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2945,6 +2945,20 @@
 #define MASK_TH_VFNCVTFXV 0xfc0ff07f
 #define MATCH_TH_VFNCVTFFV 0x880a1057
 #define MASK_TH_VFNCVTFFV 0xfc0ff07f
+#define MATCH_TH_VMPOPCM 0x50002057
+#define MASK_TH_VMPOPCM 0xfc0ff07f
+#define MATCH_TH_VMFIRSTM 0x54002057
+#define MASK_TH_VMFIRSTM 0xfc0ff07f
+#define MATCH_TH_VMSBFM 0x5800a057
+#define MASK_TH_VMSBFM 0xfc0ff07f
+#define MATCH_TH_VMSIFM 0x5801a057
+#define MASK_TH_VMSIFM 0xfc0ff07f
+#define MATCH_TH_VMSOFM 0x58012057
+#define MASK_TH_VMSOFM 0xfc0ff07f
+#define MATCH_TH_VIOTAM 0x58082057
+#define MASK_TH_VIOTAM 0xfc0ff07f
+#define MATCH_TH_VIDV 0x5808a057
+#define MASK_TH_VIDV 0xfdfff07f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2dde9ca4a0a..b9b47cf849e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2860,6 +2860,25 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
 {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
 {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
+{"th.vmcpy.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmclr.m",    0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmset.m",    0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmnot.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmand.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
+{"th.vmnand.mm",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
+{"th.vmandnot.mm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
+{"th.vmxor.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
+{"th.vmor.mm",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
+{"th.vmnor.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
+{"th.vmornot.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
+{"th.vmxnor.mm",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
+{"th.vmpopc.m",   0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMPOPCM, MASK_TH_VMPOPCM, match_opcode, 0},
+{"th.vmfirst.m",  0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMFIRSTM, MASK_TH_VMFIRSTM, match_opcode, 0},
+{"th.vmsbf.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSBFM, MASK_TH_VMSBFM, match_opcode, 0},
+{"th.vmsif.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSIFM, MASK_TH_VMSIFM, match_opcode, 0},
+{"th.vmsof.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0},
+{"th.viota.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0},
+{"th.vid.v",      0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 12/12] RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (10 preceding siblings ...)
  2023-11-18  7:08 ` [PATCH v2 11/12] RISC-V: Add vector mask " Jin Ma
@ 2023-11-18  7:08 ` Jin Ma
  2023-11-23  2:37 ` [PATCH v2 00/12] RISC-V: Add " Nelson Chu
  12 siblings, 0 replies; 14+ messages in thread
From: Jin Ma @ 2023-11-18  7:08 UTC (permalink / raw)
  To: binutils, nelson; +Cc: christoph.muellner, lifang_xia, jinma.contrib, Jin Ma

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	permutation instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 30 +++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 38 ++++++++++++++++++++++++
 include/opcode/riscv-opc.h               | 10 +++++++
 opcodes/riscv-opc.c                      | 15 ++++++++++
 4 files changed, 93 insertions(+)

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 03d8ede7c77..014c2fdb80d 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1618,3 +1618,33 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+58812257[ 	]+th.vmsof.m[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+58882257[ 	]+th.viota.m[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+5808a257[ 	]+th.vid.v[ 	]+v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+32c02557[ 	]+th.vmv.x.s[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+32c62557[ 	]+th.vext.x.v[ 	]+a0,v12,a2
+[ 	]+[0-9a-f]+:[ 	]+36056257[ 	]+th.vmv.s.x[ 	]+v4,a0
+[ 	]+[0-9a-f]+:[ 	]+32801557[ 	]+th.vfmv.f.s[ 	]+fa0,v8
+[ 	]+[0-9a-f]+:[ 	]+3605d257[ 	]+th.vfmv.s.f[ 	]+v4,fa1
+[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+th.vslideup.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+th.vslideup.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+th.vslideup.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+th.vslidedown.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+th.vslidedown.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+th.vslidedown.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+th.vslideup.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+th.vslideup.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+th.vslideup.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+th.vslidedown.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+th.vslidedown.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+th.vslidedown.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+th.vslide1up.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+th.vslide1down.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+th.vslide1up.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+th.vslide1down.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+th.vrgather.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+th.vrgather.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+th.vrgather.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+th.vrgather.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+th.vrgather.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+th.vrgather.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+th.vrgather.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+th.vrgather.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+th.vcompress.vm[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 1c1c27cb6d8..3a4dea38c8b 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1686,3 +1686,41 @@
 	th.vmsof.m v4, v8, v0.t
 	th.viota.m v4, v8, v0.t
 	th.vid.v v4, v0.t
+
+	# Alias
+	th.vmv.x.s a0, v12
+
+	th.vext.x.v a0, v12, a2
+	th.vmv.s.x v4, a0
+
+	th.vfmv.f.s fa0, v8
+	th.vfmv.s.f v4, fa1
+
+	th.vslideup.vx v4, v8, a1
+	th.vslideup.vi v4, v8, 0
+	th.vslideup.vi v4, v8, 31
+	th.vslidedown.vx v4, v8, a1
+	th.vslidedown.vi v4, v8, 0
+	th.vslidedown.vi v4, v8, 31
+	th.vslideup.vx v4, v8, a1, v0.t
+	th.vslideup.vi v4, v8, 0, v0.t
+	th.vslideup.vi v4, v8, 31, v0.t
+	th.vslidedown.vx v4, v8, a1, v0.t
+	th.vslidedown.vi v4, v8, 0, v0.t
+	th.vslidedown.vi v4, v8, 31, v0.t
+
+	th.vslide1up.vx v4, v8, a1
+	th.vslide1down.vx v4, v8, a1
+	th.vslide1up.vx v4, v8, a1, v0.t
+	th.vslide1down.vx v4, v8, a1, v0.t
+
+	th.vrgather.vv v4, v8, v12
+	th.vrgather.vx v4, v8, a1
+	th.vrgather.vi v4, v8, 0
+	th.vrgather.vi v4, v8, 31
+	th.vrgather.vv v4, v8, v12, v0.t
+	th.vrgather.vx v4, v8, a1, v0.t
+	th.vrgather.vi v4, v8, 0, v0.t
+	th.vrgather.vi v4, v8, 31, v0.t
+
+	th.vcompress.vm v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9b4288c8ee2..1e417217b7d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2959,6 +2959,16 @@
 #define MASK_TH_VIOTAM 0xfc0ff07f
 #define MATCH_TH_VIDV 0x5808a057
 #define MASK_TH_VIDV 0xfdfff07f
+#define MATCH_TH_VMVXS 0x32002057
+#define MASK_TH_VMVXS 0xfe0ff07f
+#define MATCH_TH_VEXTXV 0x32002057
+#define MASK_TH_VEXTXV 0xfe00707f
+#define MATCH_TH_VMVSX 0x36006057
+#define MASK_TH_VMVSX 0xfff0707f
+#define MATCH_TH_VFMVFS 0x32001057
+#define MASK_TH_VFMVFS 0xfe0ff07f
+#define MATCH_TH_VFMVSF 0x36005057
+#define MASK_TH_VFMVSF 0xfff0707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b9b47cf849e..fcba49972f0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2879,6 +2879,21 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vmsof.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0},
 {"th.viota.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0},
 {"th.vid.v",      0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0},
+{"th.vmv.x.s",    0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS},
+{"th.vext.x.v",   0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0},
+{"th.vmv.s.x",    0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0},
+{"th.vfmv.f.s",   0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0},
+{"th.vfmv.s.f",   0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0},
+{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0},
+{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0},
+{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
+{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
+{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0},
+{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
+{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0},
+{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0},
+{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0},
+{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-- 
2.17.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension.
  2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
                   ` (11 preceding siblings ...)
  2023-11-18  7:08 ` [PATCH v2 12/12] RISC-V: Add vector permutation " Jin Ma
@ 2023-11-23  2:37 ` Nelson Chu
  12 siblings, 0 replies; 14+ messages in thread
From: Nelson Chu @ 2023-11-23  2:37 UTC (permalink / raw)
  To: Jin Ma; +Cc: binutils, christoph.muellner, lifang_xia, jinma.contrib

[-- Attachment #1: Type: text/plain, Size: 4285 bytes --]

Generally the OP_CUSTOM_0/1/2/3 are reserved for vendor/custom/non-standard
usage.  Non-standard extensions that use space that’s reserved for standard
extensions are considered to be “non-conforming”.  We discourage (but not
disallow) non-conforming extensions, since it is highly likely that future
standard extensions will reclaim space used by them.  However, the t-head
vector is kind of different, according to my understanding, it's actually
rvv 0.7.  Since we don't have plans to support multi-version encodings, and
the reasons that t-head released rvv 0.7 are complicated, we recommended
them to use vendor/non-standard extensions to solve this problem.  Since
the patches make sure that t-head vector and standard vector won't be
enabled at the same time, the conflicted encodings should work well in
current implementation.

Anyway, committed.

Thanks
Nelson


On Sat, Nov 18, 2023 at 2:49 PM Jin Ma <jinma@linux.alibaba.com> wrote:

> V1 -> V2:
>
> V2 adopted the review comments of Nelson and modified the
> instructions encoding of vendor: Reuse the instruction
> encoding of the "V" extension as much as possible and
> remove redundant instructions encoding.
>
> V1:
>
> T-Head has a range of vendor-specific instructions ([2]).
> Therefore it makes sense to group them into smaller chunks
> in form of vendor extensions.
>
> This patch adds the "XTheadVector" extension, a collection of
> T-Head-specific vector instructions. The 'th' prefix and the
> "XTheadVector" extension are documented in a PR for the RISC-V
> toolchain conventions ([1]).
>
> Here are some things that need to be explained:
> The "XTheadVector" extension is not a custom-extension, but
> a non-standard non-conforming extension. The encoding space
> of the "TheadVector" instructions overlaps with those of
> the 'V' extension. This encoding space conflict is not on
> purpose, but the result of issues in the past that have
> been resolved since. Therefore, the "XTheadVector" extension
> and the 'V' extension are in conflict.
>
> [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
> [2]
> https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
>
> Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
>
> ---
>  bfd/elfxx-riscv.c                             |   17 +
>  gas/NEWS                                      |    3 +
>  gas/config/tc-riscv.c                         |    4 +
>  gas/doc/c-riscv.texi                          |   11 +
>  .../gas/riscv/x-thead-vector-csr-warn.d       |    3 +
>  .../gas/riscv/x-thead-vector-csr-warn.l       |   16 +
>  gas/testsuite/gas/riscv/x-thead-vector-csr.d  |   21 +
>  gas/testsuite/gas/riscv/x-thead-vector-csr.s  |   13 +
>  gas/testsuite/gas/riscv/x-thead-vector-fail.d |    3 +
>  gas/testsuite/gas/riscv/x-thead-vector-fail.l |    2 +
>  .../gas/riscv/x-thead-vector-zvamo.d          |   81 +
>  .../gas/riscv/x-thead-vector-zvamo.s          |   74 +
>  gas/testsuite/gas/riscv/x-thead-vector.d      | 1650 ++++++++++++++++
>  gas/testsuite/gas/riscv/x-thead-vector.s      | 1726 +++++++++++++++++
>  include/opcode/riscv-opc.h                    |  328 ++++
>  include/opcode/riscv.h                        |    2 +
>  opcodes/riscv-dis.c                           |   14 +-
>  opcodes/riscv-opc.c                           |  661 +++++++
>  18 files changed, 4627 insertions(+), 2 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s
>
> --
> 2.17.1
>
>

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2023-11-23  2:37 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-18  6:49 [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension Jin Ma
2023-11-18  6:53 ` [PATCH v2 01/12] " Jin Ma
2023-11-18  6:58 ` [PATCH v2 02/12] RISC-V: Add CSRs for " Jin Ma
2023-11-18  7:04 ` [PATCH v2 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
2023-11-18  7:04 ` [PATCH v2 04/12] RISC-V: Add load/store " Jin Ma
2023-11-18  7:05 ` [PATCH v2 05/12] RISC-V: Add load/store segment " Jin Ma
2023-11-18  7:06 ` [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
2023-11-18  7:07 ` [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
2023-11-18  7:07 ` [PATCH v2 08/12] RISC-V: Add fixed-point " Jin Ma
2023-11-18  7:07 ` [PATCH v2 09/12] RISC-V: Add floating-point " Jin Ma
2023-11-18  7:08 ` [PATCH v2 10/12] RISC-V: Add reductions " Jin Ma
2023-11-18  7:08 ` [PATCH v2 11/12] RISC-V: Add vector mask " Jin Ma
2023-11-18  7:08 ` [PATCH v2 12/12] RISC-V: Add vector permutation " Jin Ma
2023-11-23  2:37 ` [PATCH v2 00/12] RISC-V: Add " Nelson Chu

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