From: Jan Beulich <jbeulich@suse.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: Jan Beulich via Binutils <binutils@sourceware.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Andreas Schwab <schwab@linux-m68k.org>
Subject: Re: [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation
Date: Tue, 25 Apr 2023 10:52:23 +0200 [thread overview]
Message-ID: <34bd2f40-b9d3-3de1-25b4-3f29cefd06e3@suse.com> (raw)
In-Reply-To: <CAPpQWtDA5W94up0s6==8=nxtKE8-i_1=ChyNzeee0mGys-NoJg@mail.gmail.com>
On 25.04.2023 10:44, Nelson Chu wrote:
> Thanks for the information, Andreas. The riscv-asm should be the right
> place to see the expected behaviors, and discuss the related stuff :-)
Just to clarify: Is this a request to replace this patch by one insisting
on the use of a parenthesis? If so, I can certainly do that, and commit
only the remaining patches (as per your other reply).
Jan
> On Tue, Apr 25, 2023 at 4:37 PM Andreas Schwab <schwab@linux-m68k.org>
> wrote:
>
>> On Mär 10 2023, Jan Beulich via Binutils wrote:
>>
>>> With a blank being okay as a separator, constructs like
>>>
>>> lui t0, %hi sym
>>> lui t0, %hi 0x1000
>>>
>>> are accepted. But then it makes little sense to not also accept e.g.
>>>
>>> lui t0, %hi +sym
>>> lui t0, %hi -0x1000
>>
>> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
>> always includes the parens around the expression, and I don't think it
>> should be accepted without them.
>>
>> --
>> Andreas Schwab, schwab@linux-m68k.org
>> GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
>> "And now for something completely different."
>>
>
next prev parent reply other threads:[~2023-04-25 8:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:23 [PATCH v2 0/7] RISC-V/gas: insn operand parsing Jan Beulich
2023-03-10 9:25 ` [PATCH v2 1/7] RISC-V: minor effort reduction in relocation specifier parsing Jan Beulich
2023-03-10 11:24 ` Jan Beulich
2023-03-10 9:26 ` [PATCH v2 2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() Jan Beulich
2023-03-10 9:26 ` [PATCH v2 3/7] RISC-V: avoid redundant and misleading/wrong error messages Jan Beulich
2023-03-10 9:27 ` [PATCH v2 4/7] RISC-V: don't recognize bogus relocations Jan Beulich
2023-03-10 9:27 ` [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation Jan Beulich
2023-04-25 8:13 ` Nelson Chu
2023-04-25 8:37 ` Andreas Schwab
2023-04-25 8:44 ` Nelson Chu
2023-04-25 8:52 ` Jan Beulich [this message]
2023-04-28 1:29 ` Nelson Chu
2023-04-28 6:05 ` Jan Beulich
2023-04-28 8:03 ` Fangrui Song
2023-05-11 11:27 ` Jan Beulich
2023-03-10 9:27 ` [PATCH v2 6/7] RISC-V: test for expected / no unexpected symbols Jan Beulich
2023-03-10 9:28 ` [PATCH v2 7/7] RISC-V: adjust logic to avoid register name symbols Jan Beulich
2023-04-25 8:40 ` [PATCH v2 0/7] RISC-V/gas: insn operand parsing Nelson Chu
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