From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson@rivosinc.com>
Subject: [PATCH v2 4/7] RISC-V: don't recognize bogus relocations
Date: Fri, 10 Mar 2023 10:27:05 +0100 [thread overview]
Message-ID: <ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com> (raw)
In-Reply-To: <ba68222c-7de6-280d-e98e-503e3c27addc@suse.com>
With my_getSmallExpression() consistently and silently failing on
relocation operators not fitting an insn, it is no longer necessary to
hand it percent_op_itype[] "just in case" (i.e. to avoid errors when a
subsequent parsing attempt for another operand combination might
succeed). This also eliminates the latent problem of percent_op_itype[]
and percent_op_stype[] growing a non-identical set of recognized
relocation operators.
---
v2: New.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2517,7 +2517,7 @@ riscv_ip (char *str, struct riscv_cl_ins
imm_expr->X_op = O_absent;
*imm_reloc = BFD_RELOC_UNUSED;
- p = percent_op_itype;
+ p = percent_op_null;
for (oparg = insn->args;; ++oparg)
{
@@ -3233,7 +3233,6 @@ riscv_ip (char *str, struct riscv_cl_ins
p = percent_op_rtype;
goto alu_op;
case '0': /* AMO displacement, which must be zero. */
- p = percent_op_null;
load_store:
if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
continue;
next prev parent reply other threads:[~2023-03-10 9:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:23 [PATCH v2 0/7] RISC-V/gas: insn operand parsing Jan Beulich
2023-03-10 9:25 ` [PATCH v2 1/7] RISC-V: minor effort reduction in relocation specifier parsing Jan Beulich
2023-03-10 11:24 ` Jan Beulich
2023-03-10 9:26 ` [PATCH v2 2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() Jan Beulich
2023-03-10 9:26 ` [PATCH v2 3/7] RISC-V: avoid redundant and misleading/wrong error messages Jan Beulich
2023-03-10 9:27 ` Jan Beulich [this message]
2023-03-10 9:27 ` [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation Jan Beulich
2023-04-25 8:13 ` Nelson Chu
2023-04-25 8:37 ` Andreas Schwab
2023-04-25 8:44 ` Nelson Chu
2023-04-25 8:52 ` Jan Beulich
2023-04-28 1:29 ` Nelson Chu
2023-04-28 6:05 ` Jan Beulich
2023-04-28 8:03 ` Fangrui Song
2023-05-11 11:27 ` Jan Beulich
2023-03-10 9:27 ` [PATCH v2 6/7] RISC-V: test for expected / no unexpected symbols Jan Beulich
2023-03-10 9:28 ` [PATCH v2 7/7] RISC-V: adjust logic to avoid register name symbols Jan Beulich
2023-04-25 8:40 ` [PATCH v2 0/7] RISC-V/gas: insn operand parsing Nelson Chu
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