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From: Nelson Chu <nelson@rivosinc.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>
Subject: Re: [PATCH v2 0/7] RISC-V/gas: insn operand parsing
Date: Tue, 25 Apr 2023 16:40:23 +0800	[thread overview]
Message-ID: <CAPpQWtBYvTFEQ7GFodeDS9Z-+LngZkiN5kX6cfc5eJ572_86Aw@mail.gmail.com> (raw)
In-Reply-To: <ba68222c-7de6-280d-e98e-503e3c27addc@suse.com>

[-- Attachment #1: Type: text/plain, Size: 1651 bytes --]

Hi Jan,

On Fri, Mar 10, 2023 at 5:24 PM Jan Beulich <jbeulich@suse.com> wrote:

> (v1 series was "re-work register named symbols avoidance logic")
>
> This addresses some of the anomalies I've observed. There continue to
> be questions towards consistent overall behavior - see remarks in the
> individual patches.
>
> An assembler with the full series in place was used in a gcc 12.2.0
> testsuite run (cross build on x86, so no execution tests), resulting
> in no new test failures (there were a number of pre-existing ones,
> though).
>
> 1: minor effort reduction in relocation specifier parsing
> 2: drop "percent_op" parameter from my_getOpcodeExpression()
> 3: avoid redundant and misleading/wrong error messages
> 4: don't recognize bogus relocations
> 5: relax post-relocation-operator separator expectation
>

Except this one I'm not sure if we should accept or not, others look good
to me.  The gcc/binutils regressions of riscv-gnu-toolchain looks good with
this whole series, including the fifth patch, so I guess that is because
the current codegen and inline assembly developers are all expect () after
the %hi/%pcrel_hi/... modifiers.  I don't know if we should relax the usage
of modifiers here, but at least the regressions prove that there should be
no effect for now, even if we commit the patch.  The only thing is that we
may have different behaviors as llvm, but since llvm only accepts the ()
after the modifiers, we have already behaved a little differently.

Thanks
Nelson


> 6: test for expected / no unexpected symbols
> 7: adjust logic to avoid register name symbols
>
> Jan
>

      parent reply	other threads:[~2023-04-25  8:40 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-10  9:23 Jan Beulich
2023-03-10  9:25 ` [PATCH v2 1/7] RISC-V: minor effort reduction in relocation specifier parsing Jan Beulich
2023-03-10 11:24   ` Jan Beulich
2023-03-10  9:26 ` [PATCH v2 2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() Jan Beulich
2023-03-10  9:26 ` [PATCH v2 3/7] RISC-V: avoid redundant and misleading/wrong error messages Jan Beulich
2023-03-10  9:27 ` [PATCH v2 4/7] RISC-V: don't recognize bogus relocations Jan Beulich
2023-03-10  9:27 ` [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation Jan Beulich
2023-04-25  8:13   ` Nelson Chu
2023-04-25  8:37   ` Andreas Schwab
2023-04-25  8:44     ` Nelson Chu
2023-04-25  8:52       ` Jan Beulich
2023-04-28  1:29         ` Nelson Chu
2023-04-28  6:05           ` Jan Beulich
2023-04-28  8:03             ` Fangrui Song
2023-05-11 11:27     ` Jan Beulich
2023-03-10  9:27 ` [PATCH v2 6/7] RISC-V: test for expected / no unexpected symbols Jan Beulich
2023-03-10  9:28 ` [PATCH v2 7/7] RISC-V: adjust logic to avoid register name symbols Jan Beulich
2023-04-25  8:40 ` Nelson Chu [this message]

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