From: Fangrui Song <i@maskray.me>
To: Jan Beulich <jbeulich@suse.com>
Cc: Nelson Chu <nelson@rivosinc.com>,
Jan Beulich via Binutils <binutils@sourceware.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Andreas Schwab <schwab@linux-m68k.org>
Subject: Re: [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation
Date: Fri, 28 Apr 2023 01:03:46 -0700 [thread overview]
Message-ID: <DS7PR12MB57654E08251C64C7F5DBB5A6CB6B9@DS7PR12MB5765.namprd12.prod.outlook.com> (raw)
In-Reply-To: <119b3b40-aec0-cc5c-2732-13f4626460f7@suse.com>
On Thu, Apr 27, 2023 at 11:05 PM Jan Beulich via Binutils
<binutils@sourceware.org> wrote:
>
> On 28.04.2023 03:29, Nelson Chu wrote:
> > Sorry for missing this one. No, not a request. I'm fine with both, since
> > this patch won't break the risc-gnu-toolchain regression, so most of the
> > stuff already used looks good. It seems that the risc v-asm doesn't say we
> > "must '' use a parenthesis after the modifiers, it just shows examples that
> > all use it.
>
> Hmm, interesting. My interpretation of especially the table in the doc (not
> so much the examples) would be that it pretty much mandates parentheses. One
> might even go as far as taking it to mandate no blank between reloc specifier
> and paren (but I wouldn't feel well going that far without it being said
> explicitly). So my plan was to make the alternative patch, and then leave it
> to you (incl other maintainers) to decide (with my personal preference being
> the yet to be created alternative one, now that I've seen the doc).
>
> Jan
I agree that rejecting `%hi sym` shall be a reasonable change in gas.
The LLVM integrated assembler (used by Clang and llvm-mc) rejects the
syntax.
% cat a.s
lui t0, %hi sym
% clang --target=riscv64 -c a.s
a.s:1:18: error: expected '('
lui t0, %hi sym
^
a.s:1:18: error: unknown operand
lui t0, %hi sym
^
next prev parent reply other threads:[~2023-04-28 8:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:23 [PATCH v2 0/7] RISC-V/gas: insn operand parsing Jan Beulich
2023-03-10 9:25 ` [PATCH v2 1/7] RISC-V: minor effort reduction in relocation specifier parsing Jan Beulich
2023-03-10 11:24 ` Jan Beulich
2023-03-10 9:26 ` [PATCH v2 2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() Jan Beulich
2023-03-10 9:26 ` [PATCH v2 3/7] RISC-V: avoid redundant and misleading/wrong error messages Jan Beulich
2023-03-10 9:27 ` [PATCH v2 4/7] RISC-V: don't recognize bogus relocations Jan Beulich
2023-03-10 9:27 ` [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation Jan Beulich
2023-04-25 8:13 ` Nelson Chu
2023-04-25 8:37 ` Andreas Schwab
2023-04-25 8:44 ` Nelson Chu
2023-04-25 8:52 ` Jan Beulich
2023-04-28 1:29 ` Nelson Chu
2023-04-28 6:05 ` Jan Beulich
2023-04-28 8:03 ` Fangrui Song [this message]
2023-05-11 11:27 ` Jan Beulich
2023-03-10 9:27 ` [PATCH v2 6/7] RISC-V: test for expected / no unexpected symbols Jan Beulich
2023-03-10 9:28 ` [PATCH v2 7/7] RISC-V: adjust logic to avoid register name symbols Jan Beulich
2023-04-25 8:40 ` [PATCH v2 0/7] RISC-V/gas: insn operand parsing Nelson Chu
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