From: Jan Beulich <jbeulich@suse.com>
To: Andreas Schwab <schwab@linux-m68k.org>, Nelson Chu <nelson@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Jan Beulich via Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation
Date: Thu, 11 May 2023 13:27:54 +0200 [thread overview]
Message-ID: <feb85628-e114-aa36-6d16-9471a9590cb0@suse.com> (raw)
In-Reply-To: <87354otl13.fsf@igel.home>
On 25.04.2023 10:37, Andreas Schwab wrote:
> On Mär 10 2023, Jan Beulich via Binutils wrote:
>
>> With a blank being okay as a separator, constructs like
>>
>> lui t0, %hi sym
>> lui t0, %hi 0x1000
>>
>> are accepted. But then it makes little sense to not also accept e.g.
>>
>> lui t0, %hi +sym
>> lui t0, %hi -0x1000
>
> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
> always includes the parens around the expression, and I don't think it
> should be accepted without them.
Just to mention it: Someone (validly) said that much of this code (and
the underlying syntax) was derived from MIPS. Just now it happened that
I had to look at the MIPS testsuite for a different reason, when it
caught my eye that they're actually testing cases like the earlier two
above (and I'm pretty sure they would similarly fail on the latter two).
Jan
next prev parent reply other threads:[~2023-05-11 11:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:23 [PATCH v2 0/7] RISC-V/gas: insn operand parsing Jan Beulich
2023-03-10 9:25 ` [PATCH v2 1/7] RISC-V: minor effort reduction in relocation specifier parsing Jan Beulich
2023-03-10 11:24 ` Jan Beulich
2023-03-10 9:26 ` [PATCH v2 2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() Jan Beulich
2023-03-10 9:26 ` [PATCH v2 3/7] RISC-V: avoid redundant and misleading/wrong error messages Jan Beulich
2023-03-10 9:27 ` [PATCH v2 4/7] RISC-V: don't recognize bogus relocations Jan Beulich
2023-03-10 9:27 ` [PATCH v2 5/7] RISC-V: relax post-relocation-operator separator expectation Jan Beulich
2023-04-25 8:13 ` Nelson Chu
2023-04-25 8:37 ` Andreas Schwab
2023-04-25 8:44 ` Nelson Chu
2023-04-25 8:52 ` Jan Beulich
2023-04-28 1:29 ` Nelson Chu
2023-04-28 6:05 ` Jan Beulich
2023-04-28 8:03 ` Fangrui Song
2023-05-11 11:27 ` Jan Beulich [this message]
2023-03-10 9:27 ` [PATCH v2 6/7] RISC-V: test for expected / no unexpected symbols Jan Beulich
2023-03-10 9:28 ` [PATCH v2 7/7] RISC-V: adjust logic to avoid register name symbols Jan Beulich
2023-04-25 8:40 ` [PATCH v2 0/7] RISC-V/gas: insn operand parsing Nelson Chu
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