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From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 3/5] x86: support AVX10.1/512
Date: Mon, 28 Aug 2023 09:09:28 +0200	[thread overview]
Message-ID: <3dc8a453-eb31-1caa-c003-4bee60bf0863@suse.com> (raw)
In-Reply-To: <SA1PR11MB5946F716CCACFDB2987C63FCECE0A@SA1PR11MB5946.namprd11.prod.outlook.com>

On 28.08.2023 08:59, Jiang, Haochen wrote:
>> But of course the question remains on whether this is needed in the first
>> place. Personally I'd favor making AES a prereq of VAES (and PCLMULQDQ one
>> of VPCLMULQDQ); if we decided to go that route, I'd make that change a
> 
> For PCLMULQDQ and VPCLMULQDQ, the imply should be ok. Actually, I have
> added that in GCC in April, but I forgot to check Binutils at that time:
> 
> https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=4246611d1915f1664c01f286dbeb946dd06e2a4d
> 
> For AES/VAES, I am conservative on that at that time because not all the insts are
> included in VAES:
> 
> https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=24a8acc1662c37003a7b54814bf840019fec2190
> 
> But I suppose the reason why AESIMC/AESKEYGENASSIST are not included might
> be one key length is 128 bit while generating/transforming two at the same time
> and putting them into ymm register is not quite needed.

Plus VAES is going to be of less use without those two insns, so assuming
AES to also be there if VAES is ought to be sufficiently "natural". Yet
as said, it would be quite nice if the SDM could make such "connections"
explicit.

> I am both ok on whether to imply or not since it would be simple if implied.

Okay, I'll tentatively add a new prereq patch then, but before posting v2
I'd like to give H.J. the opportunity to voice an opinion.

Jan

  reply	other threads:[~2023-08-28  7:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-25 12:43 [PATCH 0/5] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-08-25 12:44 ` [PATCH 1/5] x86: correct source used for two non-AVX512 VEXWIG tests Jan Beulich
2023-08-25 12:45 ` [PATCH 2/5] x86: rename CpuPCLMUL Jan Beulich
2023-08-25 12:46 ` [PATCH 3/5] x86: support AVX10.1/512 Jan Beulich
2023-08-28  2:34   ` Jiang, Haochen
2023-08-28  6:45     ` Jan Beulich
2023-08-28  6:59       ` Jiang, Haochen
2023-08-28  7:09         ` Jan Beulich [this message]
2023-08-29 16:18           ` H.J. Lu
2023-08-30  1:10             ` Jiang, Haochen
2023-08-30  7:47               ` Jan Beulich
2023-08-30 15:28                 ` H.J. Lu
2023-09-01  8:41                   ` Jan Beulich
2023-09-01  8:52                     ` Jiang, Haochen
2023-09-01  9:57                       ` Jan Beulich
2023-09-05  7:04                         ` Jiang, Haochen
2023-09-05  7:25                           ` Jan Beulich
2023-08-25 12:47 ` [PATCH 4/5] x86: unindent most of set_cpu_arch() Jan Beulich
2023-08-25 12:47 ` [PATCH 5/5] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-08-29 16:26   ` H.J. Lu
2023-08-30  7:57     ` Jan Beulich
2023-08-30 15:25       ` H.J. Lu
2023-08-30 16:16         ` Jan Beulich
2023-08-30 18:00           ` H.J. Lu
2023-08-31  5:56             ` Jiang, Haochen
2023-08-31  7:18               ` Jan Beulich
2023-09-01  6:21                 ` Jiang, Haochen

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