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From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>, "H.J. Lu" <hjl.tools@gmail.com>
Cc: Binutils <binutils@sourceware.org>
Subject: RE: [PATCH 3/5] x86: support AVX10.1/512
Date: Fri, 1 Sep 2023 08:52:01 +0000	[thread overview]
Message-ID: <SA1PR11MB5946EAE74DAAAA73F0CD0EBDECE4A@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <b64908a7-95a3-d612-352a-c9f16be5667f@suse.com>



> >>> AVX10 should not imply them. However, I suppose we are talking about
> >>> the relation between AES/VAES and PCLMULQDQ/VPCLMULQDQ.
> >>
> >> Correct. Some change needs to be done; the question is whether as
> >> posted, or whether with a prereq patch adding those two connections
> >> (with, as said before, me intending to go the latter route unless I
> >> hear otherwise).
> >
> > I agree.  VAES should imply AES and VPCLMULQDQ should imply
> > PCLMULQDQ.
> 
> Actually there's something similar with AVX10 itself: AVX512F includes
> equivalents right away of what comes under separate extensions for AVX:
> F16C and FMA. AVX10, otoh, is presently specified to only guarantee
> AVX and AVX2. Does that mean that VEX-encoded vfm{add,sub}* and ps<-ph
> conversion insns aren't guaranteed to also be available? Doesn't seem
> logical to me, so I'm inclined to make FMA and F16C prereqs of AVX10.1
> as well (or alternatively of AVX512F, but I think this would have
> undesirable effects). AVX2 isn't an explicit prereq only because it
> already is one of AVX512F.

I suppose AVX10 should only enable EVEX encoding,  they have nothing
to do with the VEX encoding.

For those independent VEX ISAs, if AVX512F is not enabling it, AVX10 neither.

Actually, not only F16C and FMA, under AVX10, ISAs like AVX-VNNI, AVX-IFMA
are also not enabled.

Thx,
Haochen

> 
> Jan

  reply	other threads:[~2023-09-01  8:52 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-25 12:43 [PATCH 0/5] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-08-25 12:44 ` [PATCH 1/5] x86: correct source used for two non-AVX512 VEXWIG tests Jan Beulich
2023-08-25 12:45 ` [PATCH 2/5] x86: rename CpuPCLMUL Jan Beulich
2023-08-25 12:46 ` [PATCH 3/5] x86: support AVX10.1/512 Jan Beulich
2023-08-28  2:34   ` Jiang, Haochen
2023-08-28  6:45     ` Jan Beulich
2023-08-28  6:59       ` Jiang, Haochen
2023-08-28  7:09         ` Jan Beulich
2023-08-29 16:18           ` H.J. Lu
2023-08-30  1:10             ` Jiang, Haochen
2023-08-30  7:47               ` Jan Beulich
2023-08-30 15:28                 ` H.J. Lu
2023-09-01  8:41                   ` Jan Beulich
2023-09-01  8:52                     ` Jiang, Haochen [this message]
2023-09-01  9:57                       ` Jan Beulich
2023-09-05  7:04                         ` Jiang, Haochen
2023-09-05  7:25                           ` Jan Beulich
2023-08-25 12:47 ` [PATCH 4/5] x86: unindent most of set_cpu_arch() Jan Beulich
2023-08-25 12:47 ` [PATCH 5/5] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-08-29 16:26   ` H.J. Lu
2023-08-30  7:57     ` Jan Beulich
2023-08-30 15:25       ` H.J. Lu
2023-08-30 16:16         ` Jan Beulich
2023-08-30 18:00           ` H.J. Lu
2023-08-31  5:56             ` Jiang, Haochen
2023-08-31  7:18               ` Jan Beulich
2023-09-01  6:21                 ` Jiang, Haochen

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