From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "H.J. Lu" <hjl.tools@gmail.com>, "Beulich, Jan" <JBeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: RE: [PATCH 5/5] x86: support AVX10.1 vector size restrictions
Date: Thu, 31 Aug 2023 05:56:25 +0000 [thread overview]
Message-ID: <SA1PR11MB594658AB8B2D8C9D6E9782ECECE5A@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAMe9rOrFuKS2TTQ0rHmuz5yFF4eh3F1JY3-++fjo9ONSp=_AkQ@mail.gmail.com>
> > >> I agree it isn't necessary, but as expressed before I view it as desirable.
> > >> Apart from the sentence you quoted the spec later also says "There are
> > >> currently no plans to support an Intel AVX10/128 implementation." For my
> > >> choice of also supporting the 128-bit restriction I'd like to put emphasis
> > >> on "currently". I think I said before that emulation environments (qemu,
> > >> sde to name just two well-known examples) are free to implement such
> > >> further restricted ISAs without then becoming out-of-spec.
> > >>
> > >> Plus supporting this mode right away has made me make certain adjustments
> > >> in what I'd call more clean a way, which I view as desirable as well.
> > >
> > > Since AVX10 spec doesn't specify if mask registers should be limited to
> > > 16 bits for AVX10/128, doing it in assembler is premature.
> >
> > It's hard to see why they would remain wider. The more that they were 16
> > bits only in AVX512F.
> >
> > Plus of course nobody needs to use the options to enforce the 128-bit
> > limit. The way I've coded it, it matches what the specification says.
> >
>
> AVX10 spec only has
>
> Quadword opmask instructions will only be supported on processors
> supporting vector lengths of 512 bits.
>
> It doesn't say anything about 32-bit mask. 32-bit mask can be useful
> even with 16 byte vector.
>
> --
> H.J.
The concern form my side is if there is an extreme case that overloads
registers, we might need to spill 32-bit register to 32-bit mask register
in the compiler.
Another minor concern is if there is finally a AVX10/128, although I do
not see that could happen, if we get a wrong choice here, it will take
some more time to correct the final assembler on the user side, which
I mean on the real OS.
However, I suppose both ok for me whether to allow 32-bit mask since
AVX10/128 is nowhere near in the future and it is a toy code to play with.
We could be some kind of conservative at first by just allowing 16-bit
mask register. Also, the code change is quite easy and no much worry on
changing that.
Thx,
Haochen
next prev parent reply other threads:[~2023-08-31 5:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 12:43 [PATCH 0/5] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-08-25 12:44 ` [PATCH 1/5] x86: correct source used for two non-AVX512 VEXWIG tests Jan Beulich
2023-08-25 12:45 ` [PATCH 2/5] x86: rename CpuPCLMUL Jan Beulich
2023-08-25 12:46 ` [PATCH 3/5] x86: support AVX10.1/512 Jan Beulich
2023-08-28 2:34 ` Jiang, Haochen
2023-08-28 6:45 ` Jan Beulich
2023-08-28 6:59 ` Jiang, Haochen
2023-08-28 7:09 ` Jan Beulich
2023-08-29 16:18 ` H.J. Lu
2023-08-30 1:10 ` Jiang, Haochen
2023-08-30 7:47 ` Jan Beulich
2023-08-30 15:28 ` H.J. Lu
2023-09-01 8:41 ` Jan Beulich
2023-09-01 8:52 ` Jiang, Haochen
2023-09-01 9:57 ` Jan Beulich
2023-09-05 7:04 ` Jiang, Haochen
2023-09-05 7:25 ` Jan Beulich
2023-08-25 12:47 ` [PATCH 4/5] x86: unindent most of set_cpu_arch() Jan Beulich
2023-08-25 12:47 ` [PATCH 5/5] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-08-29 16:26 ` H.J. Lu
2023-08-30 7:57 ` Jan Beulich
2023-08-30 15:25 ` H.J. Lu
2023-08-30 16:16 ` Jan Beulich
2023-08-30 18:00 ` H.J. Lu
2023-08-31 5:56 ` Jiang, Haochen [this message]
2023-08-31 7:18 ` Jan Beulich
2023-09-01 6:21 ` Jiang, Haochen
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